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89b765c7 SR |
1 | /* |
2 | * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ | |
3 | * | |
4 | * Based on davinci_dvevm.h. Original Copyrights follow: | |
5 | * | |
6 | * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> | |
7 | * | |
1a459660 | 8 | * SPDX-License-Identifier: GPL-2.0+ |
89b765c7 SR |
9 | */ |
10 | ||
11 | #ifndef __CONFIG_H | |
12 | #define __CONFIG_H | |
13 | ||
14 | /* | |
15 | * Board | |
16 | */ | |
3d248d37 | 17 | #define CONFIG_DRIVER_TI_EMAC |
63777665 LP |
18 | /* check if direct NOR boot config is used */ |
19 | #ifndef CONFIG_DIRECT_NOR_BOOT | |
d73a8a1b | 20 | #define CONFIG_USE_SPIFLASH |
63777665 | 21 | #endif |
89b765c7 | 22 | |
1506b0a8 | 23 | |
89b765c7 SR |
24 | /* |
25 | * SoC Configuration | |
26 | */ | |
27 | #define CONFIG_MACH_DAVINCI_DA850_EVM | |
89b765c7 | 28 | #define CONFIG_SOC_DA8XX /* TI DA8xx SoC */ |
52b0f877 | 29 | #define CONFIG_SOC_DA850 /* TI DA850 SoC */ |
b67d8816 | 30 | #define CONFIG_SYS_EXCEPTION_VECTORS_HIGH |
89b765c7 SR |
31 | #define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID) |
32 | #define CONFIG_SYS_OSCIN_FREQ 24000000 | |
33 | #define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE | |
34 | #define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID) | |
6b873dca SG |
35 | #define CONFIG_SYS_DA850_PLL_INIT |
36 | #define CONFIG_SYS_DA850_DDR_INIT | |
89b765c7 | 37 | |
63777665 LP |
38 | #ifdef CONFIG_DIRECT_NOR_BOOT |
39 | #define CONFIG_ARCH_CPU_INIT | |
40 | #define CONFIG_DA8XX_GPIO | |
41 | #define CONFIG_SYS_TEXT_BASE 0x60000000 | |
42 | #define CONFIG_SYS_DV_NOR_BOOT_CFG (0x11) | |
43 | #define CONFIG_DA850_LOWLEVEL | |
44 | #else | |
45 | #define CONFIG_SYS_TEXT_BASE 0xc1080000 | |
46 | #endif | |
47 | ||
89b765c7 SR |
48 | /* |
49 | * Memory Info | |
50 | */ | |
51 | #define CONFIG_SYS_MALLOC_LEN (0x10000 + 1*1024*1024) /* malloc() len */ | |
89b765c7 SR |
52 | #define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */ |
53 | #define PHYS_SDRAM_1_SIZE (64 << 20) /* SDRAM size 64MB */ | |
97003756 | 54 | #define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/ |
89b765c7 SR |
55 | |
56 | /* memtest start addr */ | |
57 | #define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM_1 + 0x2000000) | |
58 | ||
59 | /* memtest will be run on 16MB */ | |
60 | #define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + 0x2000000 + 16*1024*1024) | |
61 | ||
62 | #define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ | |
89b765c7 | 63 | |
3d2c8e6c CR |
64 | #define CONFIG_SYS_DA850_SYSCFG_SUSPSRC ( \ |
65 | DAVINCI_SYSCFG_SUSPSRC_TIMER0 | \ | |
66 | DAVINCI_SYSCFG_SUSPSRC_SPI1 | \ | |
67 | DAVINCI_SYSCFG_SUSPSRC_UART2 | \ | |
68 | DAVINCI_SYSCFG_SUSPSRC_EMAC | \ | |
69 | DAVINCI_SYSCFG_SUSPSRC_I2C) | |
70 | ||
71 | /* | |
72 | * PLL configuration | |
73 | */ | |
74 | #define CONFIG_SYS_DV_CLKMODE 0 | |
75 | #define CONFIG_SYS_DA850_PLL0_POSTDIV 1 | |
76 | #define CONFIG_SYS_DA850_PLL0_PLLDIV1 0x8000 | |
77 | #define CONFIG_SYS_DA850_PLL0_PLLDIV2 0x8001 | |
78 | #define CONFIG_SYS_DA850_PLL0_PLLDIV3 0x8002 | |
79 | #define CONFIG_SYS_DA850_PLL0_PLLDIV4 0x8003 | |
80 | #define CONFIG_SYS_DA850_PLL0_PLLDIV5 0x8002 | |
81 | #define CONFIG_SYS_DA850_PLL0_PLLDIV6 CONFIG_SYS_DA850_PLL0_PLLDIV1 | |
82 | #define CONFIG_SYS_DA850_PLL0_PLLDIV7 0x8005 | |
83 | ||
84 | #define CONFIG_SYS_DA850_PLL1_POSTDIV 1 | |
85 | #define CONFIG_SYS_DA850_PLL1_PLLDIV1 0x8000 | |
86 | #define CONFIG_SYS_DA850_PLL1_PLLDIV2 0x8001 | |
87 | #define CONFIG_SYS_DA850_PLL1_PLLDIV3 0x8002 | |
88 | ||
89 | #define CONFIG_SYS_DA850_PLL0_PLLM 24 | |
90 | #define CONFIG_SYS_DA850_PLL1_PLLM 21 | |
91 | ||
92 | /* | |
93 | * DDR2 memory configuration | |
94 | */ | |
95 | #define CONFIG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \ | |
96 | DV_DDR_PHY_EXT_STRBEN | \ | |
97 | (0x4 << DV_DDR_PHY_RD_LATENCY_SHIFT)) | |
98 | ||
99 | #define CONFIG_SYS_DA850_DDR2_SDBCR ( \ | |
100 | (1 << DV_DDR_SDCR_MSDRAMEN_SHIFT) | \ | |
101 | (1 << DV_DDR_SDCR_DDREN_SHIFT) | \ | |
102 | (1 << DV_DDR_SDCR_SDRAMEN_SHIFT) | \ | |
103 | (1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT) | \ | |
104 | (0x3 << DV_DDR_SDCR_CL_SHIFT) | \ | |
105 | (0x2 << DV_DDR_SDCR_IBANK_SHIFT) | \ | |
106 | (0x2 << DV_DDR_SDCR_PAGESIZE_SHIFT)) | |
107 | ||
108 | /* SDBCR2 is only used if IBANK_POS bit in SDBCR is set */ | |
109 | #define CONFIG_SYS_DA850_DDR2_SDBCR2 0 | |
110 | ||
111 | #define CONFIG_SYS_DA850_DDR2_SDTIMR ( \ | |
112 | (14 << DV_DDR_SDTMR1_RFC_SHIFT) | \ | |
113 | (2 << DV_DDR_SDTMR1_RP_SHIFT) | \ | |
114 | (2 << DV_DDR_SDTMR1_RCD_SHIFT) | \ | |
115 | (1 << DV_DDR_SDTMR1_WR_SHIFT) | \ | |
116 | (5 << DV_DDR_SDTMR1_RAS_SHIFT) | \ | |
117 | (8 << DV_DDR_SDTMR1_RC_SHIFT) | \ | |
118 | (1 << DV_DDR_SDTMR1_RRD_SHIFT) | \ | |
119 | (0 << DV_DDR_SDTMR1_WTR_SHIFT)) | |
120 | ||
121 | #define CONFIG_SYS_DA850_DDR2_SDTIMR2 ( \ | |
122 | (7 << DV_DDR_SDTMR2_RASMAX_SHIFT) | \ | |
123 | (0 << DV_DDR_SDTMR2_XP_SHIFT) | \ | |
124 | (0 << DV_DDR_SDTMR2_ODT_SHIFT) | \ | |
125 | (17 << DV_DDR_SDTMR2_XSNR_SHIFT) | \ | |
126 | (199 << DV_DDR_SDTMR2_XSRD_SHIFT) | \ | |
127 | (0 << DV_DDR_SDTMR2_RTP_SHIFT) | \ | |
128 | (0 << DV_DDR_SDTMR2_CKE_SHIFT)) | |
129 | ||
130 | #define CONFIG_SYS_DA850_DDR2_SDRCR 0x00000494 | |
131 | #define CONFIG_SYS_DA850_DDR2_PBBPR 0x30 | |
132 | ||
89b765c7 SR |
133 | /* |
134 | * Serial Driver info | |
135 | */ | |
136 | #define CONFIG_SYS_NS16550 | |
137 | #define CONFIG_SYS_NS16550_SERIAL | |
138 | #define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size */ | |
139 | #define CONFIG_SYS_NS16550_COM1 DAVINCI_UART2_BASE /* Base address of UART2 */ | |
140 | #define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID) | |
141 | #define CONFIG_CONS_INDEX 1 /* use UART0 for console */ | |
142 | #define CONFIG_BAUDRATE 115200 /* Default baud rate */ | |
89b765c7 | 143 | |
d73a8a1b | 144 | #define CONFIG_SPI |
d73a8a1b | 145 | #define CONFIG_SPI_FLASH_STMICRO |
8cf47399 | 146 | #define CONFIG_SPI_FLASH_WINBOND |
df166cc9 | 147 | #define CONFIG_CMD_SF |
d73a8a1b SB |
148 | #define CONFIG_DAVINCI_SPI |
149 | #define CONFIG_SYS_SPI_BASE DAVINCI_SPI1_BASE | |
150 | #define CONFIG_SYS_SPI_CLK clk_get(DAVINCI_SPI1_CLKID) | |
151 | #define CONFIG_SF_DEFAULT_SPEED 30000000 | |
152 | #define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED | |
153 | ||
42612104 LP |
154 | #ifdef CONFIG_USE_SPIFLASH |
155 | #define CONFIG_SPL_SPI_SUPPORT | |
156 | #define CONFIG_SPL_SPI_FLASH_SUPPORT | |
157 | #define CONFIG_SPL_SPI_LOAD | |
42612104 | 158 | #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x8000 |
2a10f8b9 | 159 | #define CONFIG_SYS_SPI_U_BOOT_SIZE 0x40000 |
42612104 LP |
160 | #endif |
161 | ||
89b765c7 SR |
162 | /* |
163 | * I2C Configuration | |
164 | */ | |
e8459dcc VA |
165 | #define CONFIG_SYS_I2C |
166 | #define CONFIG_SYS_I2C_DAVINCI | |
167 | #define CONFIG_SYS_DAVINCI_I2C_SPEED 25000 | |
168 | #define CONFIG_SYS_DAVINCI_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */ | |
d2607401 | 169 | #define CONFIG_SYS_I2C_EXPANDER_ADDR 0x20 |
89b765c7 | 170 | |
6b2c6468 BG |
171 | /* |
172 | * Flash & Environment | |
173 | */ | |
174 | #ifdef CONFIG_USE_NAND | |
175 | #undef CONFIG_ENV_IS_IN_FLASH | |
176 | #define CONFIG_NAND_DAVINCI | |
177 | #define CONFIG_SYS_NO_FLASH | |
178 | #define CONFIG_ENV_IS_IN_NAND /* U-Boot env in NAND Flash */ | |
179 | #define CONFIG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */ | |
180 | #define CONFIG_ENV_SIZE (128 << 10) | |
181 | #define CONFIG_SYS_NAND_USE_FLASH_BBT | |
182 | #define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST | |
183 | #define CONFIG_SYS_NAND_PAGE_2K | |
184 | #define CONFIG_SYS_NAND_CS 3 | |
185 | #define CONFIG_SYS_NAND_BASE DAVINCI_ASYNC_EMIF_DATA_CE3_BASE | |
34fa0706 EB |
186 | #define CONFIG_SYS_NAND_MASK_CLE 0x10 |
187 | #define CONFIG_SYS_NAND_MASK_ALE 0x8 | |
6b2c6468 BG |
188 | #undef CONFIG_SYS_NAND_HW_ECC |
189 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ | |
122f9c9b LP |
190 | #define CONFIG_SYS_NAND_HW_ECC_OOBFIRST |
191 | #define CONFIG_SYS_NAND_5_ADDR_CYCLE | |
192 | #define CONFIG_SYS_NAND_PAGE_SIZE (2 << 10) | |
193 | #define CONFIG_SYS_NAND_BLOCK_SIZE (128 << 10) | |
194 | #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x28000 | |
195 | #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x60000 | |
196 | #define CONFIG_SYS_NAND_U_BOOT_DST 0xc1080000 | |
197 | #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST | |
198 | #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_DST - \ | |
199 | CONFIG_SYS_NAND_U_BOOT_SIZE - \ | |
200 | CONFIG_SYS_MALLOC_LEN - \ | |
201 | GENERATED_GBL_DATA_SIZE) | |
202 | #define CONFIG_SYS_NAND_ECCPOS { \ | |
203 | 24, 25, 26, 27, 28, \ | |
204 | 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, \ | |
205 | 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, \ | |
206 | 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, \ | |
207 | 59, 60, 61, 62, 63 } | |
208 | #define CONFIG_SYS_NAND_PAGE_COUNT 64 | |
209 | #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 | |
210 | #define CONFIG_SYS_NAND_ECCSIZE 512 | |
211 | #define CONFIG_SYS_NAND_ECCBYTES 10 | |
212 | #define CONFIG_SYS_NAND_OOBSIZE 64 | |
213 | #define CONFIG_SPL_NAND_SUPPORT | |
6f2f01b9 SW |
214 | #define CONFIG_SPL_NAND_BASE |
215 | #define CONFIG_SPL_NAND_DRIVERS | |
216 | #define CONFIG_SPL_NAND_ECC | |
122f9c9b LP |
217 | #define CONFIG_SPL_NAND_SIMPLE |
218 | #define CONFIG_SPL_NAND_LOAD | |
6b2c6468 BG |
219 | #endif |
220 | ||
3d248d37 BG |
221 | /* |
222 | * Network & Ethernet Configuration | |
223 | */ | |
224 | #ifdef CONFIG_DRIVER_TI_EMAC | |
3d248d37 | 225 | #define CONFIG_MII |
3d248d37 BG |
226 | #define CONFIG_BOOTP_DNS |
227 | #define CONFIG_BOOTP_DNS2 | |
228 | #define CONFIG_BOOTP_SEND_HOSTNAME | |
229 | #define CONFIG_NET_RETRY_COUNT 10 | |
3d248d37 BG |
230 | #endif |
231 | ||
1506b0a8 NN |
232 | #ifdef CONFIG_USE_NOR |
233 | #define CONFIG_ENV_IS_IN_FLASH | |
234 | #define CONFIG_FLASH_CFI_DRIVER | |
235 | #define CONFIG_SYS_FLASH_CFI | |
236 | #define CONFIG_SYS_FLASH_PROTECTION | |
237 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of flash banks */ | |
238 | #define CONFIG_SYS_FLASH_SECT_SZ (128 << 10) /* 128KB */ | |
239 | #define CONFIG_ENV_OFFSET (CONFIG_SYS_FLASH_SECT_SZ * 3) | |
240 | #define CONFIG_ENV_SIZE (10 << 10) /* 10KB */ | |
241 | #define CONFIG_SYS_FLASH_BASE DAVINCI_ASYNC_EMIF_DATA_CE2_BASE | |
242 | #define PHYS_FLASH_SIZE (8 << 20) /* Flash size 8MB */ | |
243 | #define CONFIG_SYS_MAX_FLASH_SECT ((PHYS_FLASH_SIZE/CONFIG_SYS_FLASH_SECT_SZ)\ | |
244 | + 3) | |
245 | #define CONFIG_ENV_SECT_SIZE CONFIG_SYS_FLASH_SECT_SZ | |
246 | #endif | |
247 | ||
d73a8a1b SB |
248 | #ifdef CONFIG_USE_SPIFLASH |
249 | #undef CONFIG_ENV_IS_IN_FLASH | |
250 | #undef CONFIG_ENV_IS_IN_NAND | |
251 | #define CONFIG_ENV_IS_IN_SPI_FLASH | |
252 | #define CONFIG_ENV_SIZE (64 << 10) | |
2a10f8b9 | 253 | #define CONFIG_ENV_OFFSET (512 << 10) |
d73a8a1b SB |
254 | #define CONFIG_ENV_SECT_SIZE (64 << 10) |
255 | #define CONFIG_SYS_NO_FLASH | |
256 | #endif | |
257 | ||
89b765c7 SR |
258 | /* |
259 | * U-Boot general configuration | |
260 | */ | |
2a10f8b9 | 261 | #define CONFIG_SYS_GENERIC_BOARD |
cf2c24e3 | 262 | #define CONFIG_MISC_INIT_R |
ae5c77dd | 263 | #define CONFIG_BOARD_EARLY_INIT_F |
89b765c7 | 264 | #define CONFIG_BOOTFILE "uImage" /* Boot file name */ |
89b765c7 SR |
265 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
266 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) | |
267 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
268 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */ | |
269 | #define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x700000) | |
270 | #define CONFIG_VERSION_VARIABLE | |
271 | #define CONFIG_AUTO_COMPLETE | |
272 | #define CONFIG_SYS_HUSH_PARSER | |
89b765c7 SR |
273 | #define CONFIG_CMDLINE_EDITING |
274 | #define CONFIG_SYS_LONGHELP | |
275 | #define CONFIG_CRC32_VERIFY | |
276 | #define CONFIG_MX_CYCLIC | |
2a10f8b9 | 277 | #define CONFIG_OF_LIBFDT |
89b765c7 SR |
278 | |
279 | /* | |
280 | * Linux Information | |
281 | */ | |
59e0d611 | 282 | #define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100) |
cf2c24e3 | 283 | #define CONFIG_HWCONFIG /* enable hwconfig */ |
89b765c7 | 284 | #define CONFIG_CMDLINE_TAG |
4f6fc15b | 285 | #define CONFIG_REVISION_TAG |
89b765c7 SR |
286 | #define CONFIG_SETUP_MEMORY_TAGS |
287 | #define CONFIG_BOOTARGS \ | |
288 | "mem=32M console=ttyS2,115200n8 root=/dev/mtdblock2 rw noinitrd ip=dhcp" | |
289 | #define CONFIG_BOOTDELAY 3 | |
cf2c24e3 | 290 | #define CONFIG_EXTRA_ENV_SETTINGS "hwconfig=dsp:wake=yes" |
89b765c7 SR |
291 | |
292 | /* | |
293 | * U-Boot commands | |
294 | */ | |
89b765c7 SR |
295 | #define CONFIG_CMD_ENV |
296 | #define CONFIG_CMD_ASKENV | |
297 | #define CONFIG_CMD_DHCP | |
298 | #define CONFIG_CMD_DIAG | |
299 | #define CONFIG_CMD_MII | |
300 | #define CONFIG_CMD_PING | |
301 | #define CONFIG_CMD_SAVES | |
89b765c7 | 302 | |
8f5d4687 HM |
303 | #ifdef CONFIG_CMD_BDI |
304 | #define CONFIG_CLOCKS | |
305 | #endif | |
306 | ||
89b765c7 | 307 | #ifndef CONFIG_DRIVER_TI_EMAC |
89b765c7 SR |
308 | #undef CONFIG_CMD_DHCP |
309 | #undef CONFIG_CMD_MII | |
310 | #undef CONFIG_CMD_PING | |
311 | #endif | |
312 | ||
6b2c6468 | 313 | #ifdef CONFIG_USE_NAND |
6b2c6468 | 314 | #define CONFIG_CMD_NAND |
771d028a BG |
315 | |
316 | #define CONFIG_CMD_MTDPARTS | |
317 | #define CONFIG_MTD_DEVICE | |
318 | #define CONFIG_MTD_PARTITIONS | |
319 | #define CONFIG_LZO | |
320 | #define CONFIG_RBTREE | |
321 | #define CONFIG_CMD_UBI | |
322 | #define CONFIG_CMD_UBIFS | |
6b2c6468 BG |
323 | #endif |
324 | ||
d73a8a1b | 325 | #ifdef CONFIG_USE_SPIFLASH |
d73a8a1b | 326 | #define CONFIG_CMD_SPI |
d73a8a1b SB |
327 | #endif |
328 | ||
89b765c7 SR |
329 | #if !defined(CONFIG_USE_NAND) && \ |
330 | !defined(CONFIG_USE_NOR) && \ | |
331 | !defined(CONFIG_USE_SPIFLASH) | |
332 | #define CONFIG_ENV_IS_NOWHERE | |
333 | #define CONFIG_SYS_NO_FLASH | |
334 | #define CONFIG_ENV_SIZE (16 << 10) | |
89b765c7 SR |
335 | #undef CONFIG_CMD_ENV |
336 | #endif | |
337 | ||
ecc98ec1 | 338 | /* SD/MMC configuration */ |
4a5edda2 | 339 | #ifndef CONFIG_USE_NOR |
ecc98ec1 LP |
340 | #define CONFIG_MMC |
341 | #define CONFIG_DAVINCI_MMC_SD1 | |
342 | #define CONFIG_GENERIC_MMC | |
343 | #define CONFIG_DAVINCI_MMC | |
4a5edda2 | 344 | #endif |
ecc98ec1 LP |
345 | |
346 | /* | |
347 | * Enable MMC commands only when | |
348 | * MMC support is present | |
349 | */ | |
350 | #ifdef CONFIG_MMC | |
351 | #define CONFIG_DOS_PARTITION | |
352 | #define CONFIG_CMD_EXT2 | |
353 | #define CONFIG_CMD_FAT | |
354 | #define CONFIG_CMD_MMC | |
355 | #endif | |
356 | ||
63777665 | 357 | #ifndef CONFIG_DIRECT_NOR_BOOT |
3d2c8e6c | 358 | /* defines for SPL */ |
3f7f2414 TR |
359 | #define CONFIG_SPL_FRAMEWORK |
360 | #define CONFIG_SPL_BOARD_INIT | |
361 | #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE - \ | |
362 | CONFIG_SYS_MALLOC_LEN) | |
363 | #define CONFIG_SYS_SPL_MALLOC_SIZE CONFIG_SYS_MALLOC_LEN | |
364 | #define CONFIG_SPL_SPI_SUPPORT | |
365 | #define CONFIG_SPL_SPI_FLASH_SUPPORT | |
366 | #define CONFIG_SPL_SPI_LOAD | |
3d2c8e6c CR |
367 | #define CONFIG_SPL_SERIAL_SUPPORT |
368 | #define CONFIG_SPL_LIBCOMMON_SUPPORT | |
369 | #define CONFIG_SPL_LIBGENERIC_SUPPORT | |
6b873dca | 370 | #define CONFIG_SPL_LDSCRIPT "board/$(BOARDDIR)/u-boot-spl-da850evm.lds" |
3d2c8e6c CR |
371 | #define CONFIG_SPL_STACK 0x8001ff00 |
372 | #define CONFIG_SPL_TEXT_BASE 0x80000000 | |
b7b5f1a1 | 373 | #define CONFIG_SPL_MAX_FOOTPRINT 32768 |
532d5318 | 374 | #define CONFIG_SPL_PAD_TO 32768 |
63777665 | 375 | #endif |
0d986e61 LP |
376 | |
377 | /* Load U-Boot Image From MMC */ | |
378 | #ifdef CONFIG_SPL_MMC_LOAD | |
379 | #define CONFIG_SPL_MMC_SUPPORT | |
0d986e61 | 380 | #define CONFIG_SPL_LIBDISK_SUPPORT |
3f7f2414 TR |
381 | #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x75 |
382 | #undef CONFIG_SPL_SPI_SUPPORT | |
0d986e61 LP |
383 | #undef CONFIG_SPL_SPI_LOAD |
384 | #endif | |
385 | ||
ab86f72c | 386 | /* additions for new relocation code, must added to all boards */ |
ab86f72c | 387 | #define CONFIG_SYS_SDRAM_BASE 0xc0000000 |
63777665 LP |
388 | |
389 | #ifdef CONFIG_DIRECT_NOR_BOOT | |
390 | #define CONFIG_SYS_INIT_SP_ADDR 0x8001ff00 | |
391 | #else | |
ab86f72c | 392 | #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - /* Fix this */ \ |
25ddd1fb | 393 | GENERATED_GBL_DATA_SIZE) |
63777665 | 394 | #endif /* CONFIG_DIRECT_NOR_BOOT */ |
89b765c7 | 395 | #endif /* __CONFIG_H */ |