projects / people / ms / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 0aee53ba | 1 | /* |
| 540b5af2 | 2 | * Copyright (C) 2012 Samsung Electronics |
| 0aee53ba | 3 | * |
| 540b5af2 | 4 | * Configuration settings for the SAMSUNG EXYNOS5250 board. |
| 0aee53ba | 5 | * |
| 1a459660 | 6 | * SPDX-License-Identifier: GPL-2.0+ |
| 0aee53ba CK |
7 | */ |
| 8 | ||
| 9 | #ifndef __CONFIG_H | |
| 10 | #define __CONFIG_H | |
| 11 | ||
| 12 | /* High Level Configuration Options */ | |
| 13 | #define CONFIG_SAMSUNG /* in a SAMSUNG core */ | |
| 14 | #define CONFIG_S5P /* S5P Family */ | |
| 15 | #define CONFIG_EXYNOS5 /* which is in a Exynos5 Family */ | |
| 16 | #define CONFIG_SMDK5250 /* which is in a SMDK5250 */ | |
| 17 | ||
| 18 | #include <asm/arch/cpu.h> /* get chip and board defs */ | |
| 19 | ||
| 068a1e46 | 20 | #define CONFIG_SYS_GENERIC_BOARD |
| 0aee53ba CK |
21 | #define CONFIG_ARCH_CPU_INIT |
| 22 | #define CONFIG_DISPLAY_CPUINFO | |
| 23 | #define CONFIG_DISPLAY_BOARDINFO | |
| 24 | ||
| 540b5af2 | 25 | /* Enable fdt support for Exynos5250 */ |
| 540b5af2 HR |
26 | #define CONFIG_OF_CONTROL |
| 27 | #define CONFIG_OF_SEPARATE | |
| 28 | ||
| 5b7dcf31 SG |
29 | /* Allow tracing to be enabled */ |
| 30 | #define CONFIG_TRACE | |
| 31 | #define CONFIG_CMD_TRACE | |
| 32 | #define CONFIG_TRACE_BUFFER_SIZE (16 << 20) | |
| 33 | #define CONFIG_TRACE_EARLY_SIZE (8 << 20) | |
| 34 | #define CONFIG_TRACE_EARLY | |
| 35 | #define CONFIG_TRACE_EARLY_ADDR 0x50000000 | |
| 36 | ||
| 0aee53ba CK |
37 | /* Keep L2 Cache Disabled */ |
| 38 | #define CONFIG_SYS_DCACHE_OFF | |
| 39 | ||
| 8e6ee293 AS |
40 | /* Enable ACE acceleration for SHA1 and SHA256 */ |
| 41 | #define CONFIG_EXYNOS_ACE_SHA | |
| 2c6346c1 | 42 | #define CONFIG_SHA_HW_ACCEL |
| 8e6ee293 | 43 | |
| 0aee53ba CK |
44 | #define CONFIG_SYS_SDRAM_BASE 0x40000000 |
| 45 | #define CONFIG_SYS_TEXT_BASE 0x43E00000 | |
| 46 | ||
| 47 | /* input clock of PLL: SMDK5250 has 24MHz input clock */ | |
| 48 | #define CONFIG_SYS_CLK_FREQ 24000000 | |
| 49 | ||
| 50 | #define CONFIG_SETUP_MEMORY_TAGS | |
| 51 | #define CONFIG_CMDLINE_TAG | |
| 52 | #define CONFIG_INITRD_TAG | |
| 53 | #define CONFIG_CMDLINE_EDITING | |
| 54 | ||
| 55 | /* MACH_TYPE_SMDK5250 macro will be removed once added to mach-types */ | |
| 56 | #define MACH_TYPE_SMDK5250 3774 | |
| 57 | #define CONFIG_MACH_TYPE MACH_TYPE_SMDK5250 | |
| 58 | ||
| 59 | /* Power Down Modes */ | |
| 60 | #define S5P_CHECK_SLEEP 0x00000BAD | |
| 61 | #define S5P_CHECK_DIDLE 0xBAD00000 | |
| 62 | #define S5P_CHECK_LPA 0xABAD0000 | |
| 63 | ||
| 64 | /* Offset for inform registers */ | |
| 65 | #define INFORM0_OFFSET 0x800 | |
| 66 | #define INFORM1_OFFSET 0x804 | |
| 67 | ||
| 68 | /* Size of malloc() pool */ | |
| 211e8438 | 69 | #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (4 << 20)) |
| 0aee53ba CK |
70 | |
| 71 | /* select serial console configuration */ | |
| 0aee53ba CK |
72 | #define CONFIG_BAUDRATE 115200 |
| 73 | #define EXYNOS5_DEFAULT_UART_OFFSET 0x010000 | |
| c5171d1c | 74 | #define CONFIG_SILENT_CONSOLE |
| 0aee53ba | 75 | |
| eb28fdac HT |
76 | /* Enable keyboard */ |
| 77 | #define CONFIG_CROS_EC /* CROS_EC protocol */ | |
| 78 | #define CONFIG_CROS_EC_SPI /* Support CROS_EC over SPI */ | |
| 79 | #define CONFIG_CROS_EC_I2C /* Support CROS_EC over I2C */ | |
| 80 | #define CONFIG_CROS_EC_KEYB /* CROS_EC keyboard input */ | |
| 81 | #define CONFIG_CMD_CROS_EC | |
| 82 | #define CONFIG_KEYBOARD | |
| 83 | ||
| a2468ded AK |
84 | /* Console configuration */ |
| 85 | #define CONFIG_CONSOLE_MUX | |
| 86 | #define CONFIG_SYS_CONSOLE_IS_IN_ENV | |
| 87 | #define EXYNOS_DEVICE_SETTINGS \ | |
| eb28fdac | 88 | "stdin=serial,cros-ec-keyb\0" \ |
| a2468ded AK |
89 | "stdout=serial,lcd\0" \ |
| 90 | "stderr=serial,lcd\0" | |
| 91 | ||
| 92 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
| 93 | EXYNOS_DEVICE_SETTINGS | |
| 94 | ||
| 0aee53ba CK |
95 | /* SD/MMC configuration */ |
| 96 | #define CONFIG_GENERIC_MMC | |
| 97 | #define CONFIG_MMC | |
| 7d2d58b4 JC |
98 | #define CONFIG_SDHCI |
| 99 | #define CONFIG_S5P_SDHCI | |
| 752f4c4a A |
100 | #define CONFIG_DWMMC |
| 101 | #define CONFIG_EXYNOS_DWMMC | |
| 102 | #define CONFIG_SUPPORT_EMMC_BOOT | |
| 103 | ||
| 0aee53ba CK |
104 | |
| 105 | #define CONFIG_BOARD_EARLY_INIT_F | |
| 643be9c0 | 106 | #define CONFIG_SKIP_LOWLEVEL_INIT |
| 0aee53ba CK |
107 | |
| 108 | /* PWM */ | |
| 109 | #define CONFIG_PWM | |
| 110 | ||
| 111 | /* allow to overwrite serial and ethaddr */ | |
| 112 | #define CONFIG_ENV_OVERWRITE | |
| 113 | ||
| 114 | /* Command definition*/ | |
| 115 | #include <config_cmd_default.h> | |
| 116 | ||
| 117 | #define CONFIG_CMD_PING | |
| 118 | #define CONFIG_CMD_ELF | |
| 119 | #define CONFIG_CMD_MMC | |
| 120 | #define CONFIG_CMD_EXT2 | |
| 121 | #define CONFIG_CMD_FAT | |
| bf936210 | 122 | #define CONFIG_CMD_NET |
| 2c6346c1 | 123 | #define CONFIG_CMD_HASH |
| 0aee53ba CK |
124 | |
| 125 | #define CONFIG_BOOTDELAY 3 | |
| 126 | #define CONFIG_ZERO_BOOTDELAY_CHECK | |
| 127 | ||
| f7f85f7d AS |
128 | /* Thermal Management Unit */ |
| 129 | #define CONFIG_EXYNOS_TMU | |
| 8afcfc21 AS |
130 | #define CONFIG_CMD_DTT |
| 131 | #define CONFIG_TMU_CMD_DTT | |
| f7f85f7d | 132 | |
| a4dae631 RS |
133 | /* USB */ |
| 134 | #define CONFIG_CMD_USB | |
| 135 | #define CONFIG_USB_EHCI | |
| 136 | #define CONFIG_USB_EHCI_EXYNOS | |
| 137 | #define CONFIG_USB_STORAGE | |
| 138 | ||
| 70656c79 | 139 | /* USB boot mode */ |
| 643be9c0 | 140 | #define CONFIG_USB_BOOTING |
| 70656c79 VG |
141 | #define EXYNOS_COPY_USB_FNPTR_ADDR 0x02020070 |
| 142 | #define EXYNOS_USB_SECONDARY_BOOT 0xfeed0002 | |
| 143 | #define EXYNOS_IRAM_SECONDARY_BASE 0x02020018 | |
| 144 | ||
| c1af608f SG |
145 | /* TPM */ |
| 146 | #define CONFIG_TPM | |
| 147 | #define CONFIG_CMD_TPM | |
| 1b393db5 TWHT |
148 | #define CONFIG_TPM_TIS_I2C |
| 149 | #define CONFIG_TPM_TIS_I2C_BUS_NUMBER 3 | |
| 150 | #define CONFIG_TPM_TIS_I2C_SLAVE_ADDR 0x20 | |
| c1af608f | 151 | |
| 81e35203 CK |
152 | /* MMC SPL */ |
| 153 | #define CONFIG_SPL | |
| 154 | #define COPY_BL2_FNPTR_ADDR 0x02020030 | |
| 155 | ||
| 643be9c0 RS |
156 | #define CONFIG_SPL_LIBCOMMON_SUPPORT |
| 157 | ||
| 78fbcc95 | 158 | /* specific .lds file */ |
| 6e50e5ca | 159 | #define CONFIG_SPL_LDSCRIPT "board/samsung/common/exynos-uboot-spl.lds" |
| 78fbcc95 | 160 | #define CONFIG_SPL_TEXT_BASE 0x02023400 |
| eac579d0 | 161 | #define CONFIG_SPL_MAX_FOOTPRINT (14 * 1024) |
| 78fbcc95 | 162 | |
| 0aee53ba CK |
163 | #define CONFIG_BOOTCOMMAND "mmc read 40007000 451 2000; bootm 40007000" |
| 164 | ||
| 165 | /* Miscellaneous configurable options */ | |
| 166 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ | |
| 167 | #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ | |
| 0aee53ba CK |
168 | #define CONFIG_SYS_PROMPT "SMDK5250 # " |
| 169 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ | |
| 170 | #define CONFIG_SYS_PBSIZE 384 /* Print Buffer Size */ | |
| 171 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
| 172 | #define CONFIG_DEFAULT_CONSOLE "console=ttySAC1,115200n8\0" | |
| 173 | /* Boot Argument Buffer Size */ | |
| 174 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE | |
| 175 | /* memtest works on */ | |
| 176 | #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE | |
| 177 | #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x5E00000) | |
| 178 | #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000) | |
| 179 | ||
| 180 | #define CONFIG_SYS_HZ 1000 | |
| 181 | ||
| 0aee53ba CK |
182 | #define CONFIG_RD_LVL |
| 183 | ||
| 0aee53ba CK |
184 | #define CONFIG_NR_DRAM_BANKS 8 |
| 185 | #define SDRAM_BANK_SIZE (256UL << 20UL) /* 256 MB */ | |
| 186 | #define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE | |
| 187 | #define PHYS_SDRAM_1_SIZE SDRAM_BANK_SIZE | |
| 188 | #define PHYS_SDRAM_2 (CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE) | |
| 189 | #define PHYS_SDRAM_2_SIZE SDRAM_BANK_SIZE | |
| 190 | #define PHYS_SDRAM_3 (CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE)) | |
| 191 | #define PHYS_SDRAM_3_SIZE SDRAM_BANK_SIZE | |
| 192 | #define PHYS_SDRAM_4 (CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE)) | |
| 193 | #define PHYS_SDRAM_4_SIZE SDRAM_BANK_SIZE | |
| 194 | #define PHYS_SDRAM_5 (CONFIG_SYS_SDRAM_BASE + (4 * SDRAM_BANK_SIZE)) | |
| 195 | #define PHYS_SDRAM_5_SIZE SDRAM_BANK_SIZE | |
| 196 | #define PHYS_SDRAM_6 (CONFIG_SYS_SDRAM_BASE + (5 * SDRAM_BANK_SIZE)) | |
| 197 | #define PHYS_SDRAM_6_SIZE SDRAM_BANK_SIZE | |
| 198 | #define PHYS_SDRAM_7 (CONFIG_SYS_SDRAM_BASE + (6 * SDRAM_BANK_SIZE)) | |
| 199 | #define PHYS_SDRAM_7_SIZE SDRAM_BANK_SIZE | |
| 200 | #define PHYS_SDRAM_8 (CONFIG_SYS_SDRAM_BASE + (7 * SDRAM_BANK_SIZE)) | |
| 201 | #define PHYS_SDRAM_8_SIZE SDRAM_BANK_SIZE | |
| 202 | ||
| 203 | #define CONFIG_SYS_MONITOR_BASE 0x00000000 | |
| 204 | ||
| 205 | /* FLASH and environment organization */ | |
| 206 | #define CONFIG_SYS_NO_FLASH | |
| 207 | #undef CONFIG_CMD_IMLS | |
| 208 | #define CONFIG_IDENT_STRING " for SMDK5250" | |
| 209 | ||
| 0aee53ba CK |
210 | #define CONFIG_SYS_MMC_ENV_DEV 0 |
| 211 | ||
| 212 | #define CONFIG_SECURE_BL1_ONLY | |
| 213 | ||
| 214 | /* Secure FW size configuration */ | |
| 215 | #ifdef CONFIG_SECURE_BL1_ONLY | |
| 216 | #define CONFIG_SEC_FW_SIZE (8 << 10) /* 8KB */ | |
| 217 | #else | |
| 218 | #define CONFIG_SEC_FW_SIZE 0 | |
| 219 | #endif | |
| 220 | ||
| 221 | /* Configuration of BL1, BL2, ENV Blocks on mmc */ | |
| 222 | #define CONFIG_RES_BLOCK_SIZE (512) | |
| 223 | #define CONFIG_BL1_SIZE (16 << 10) /*16 K reserved for BL1*/ | |
| 224 | #define CONFIG_BL2_SIZE (512UL << 10UL) /* 512 KB */ | |
| 225 | #define CONFIG_ENV_SIZE (16 << 10) /* 16 KB */ | |
| 226 | ||
| 227 | #define CONFIG_BL1_OFFSET (CONFIG_RES_BLOCK_SIZE + CONFIG_SEC_FW_SIZE) | |
| 228 | #define CONFIG_BL2_OFFSET (CONFIG_BL1_OFFSET + CONFIG_BL1_SIZE) | |
| 229 | #define CONFIG_ENV_OFFSET (CONFIG_BL2_OFFSET + CONFIG_BL2_SIZE) | |
| 230 | ||
| 81e35203 CK |
231 | /* U-boot copy size from boot Media to DRAM.*/ |
| 232 | #define BL2_START_OFFSET (CONFIG_BL2_OFFSET/512) | |
| 233 | #define BL2_SIZE_BLOC_COUNT (CONFIG_BL2_SIZE/512) | |
| 7a533773 | 234 | |
| 643be9c0 | 235 | #define CONFIG_SPI_BOOTING |
| 7a533773 RS |
236 | #define EXYNOS_COPY_SPI_FNPTR_ADDR 0x02020058 |
| 237 | #define SPI_FLASH_UBOOT_POS (CONFIG_SEC_FW_SIZE + CONFIG_BL1_SIZE) | |
| 238 | ||
| 0aee53ba | 239 | #define CONFIG_DOS_PARTITION |
| 752f4c4a A |
240 | #define CONFIG_EFI_PARTITION |
| 241 | #define CONFIG_CMD_PART | |
| 242 | #define CONFIG_PARTITION_UUIDS | |
| 243 | ||
| 0aee53ba CK |
244 | |
| 245 | #define CONFIG_IRAM_STACK 0x02050000 | |
| 246 | ||
| 643be9c0 | 247 | #define CONFIG_SYS_INIT_SP_ADDR CONFIG_IRAM_STACK |
| 0aee53ba | 248 | |
| c82b050e RS |
249 | /* I2C */ |
| 250 | #define CONFIG_SYS_I2C_INIT_BOARD | |
| 251 | #define CONFIG_HARD_I2C | |
| 252 | #define CONFIG_CMD_I2C | |
| 253 | #define CONFIG_SYS_I2C_SPEED 100000 /* 100 Kbps */ | |
| 254 | #define CONFIG_DRIVER_S3C24X0_I2C | |
| 255 | #define CONFIG_I2C_MULTI_BUS | |
| 256 | #define CONFIG_MAX_I2C_NUM 8 | |
| 257 | #define CONFIG_SYS_I2C_SLAVE 0x0 | |
| 23b479b2 | 258 | #define CONFIG_I2C_EDID |
| c82b050e | 259 | |
| 0d146a56 RS |
260 | /* PMIC */ |
| 261 | #define CONFIG_PMIC | |
| 262 | #define CONFIG_PMIC_I2C | |
| 263 | #define CONFIG_PMIC_MAX77686 | |
| 264 | ||
| 3a8a7001 HR |
265 | /* SPI */ |
| 266 | #define CONFIG_ENV_IS_IN_SPI_FLASH | |
| 267 | #define CONFIG_SPI_FLASH | |
| 268 | ||
| 269 | #ifdef CONFIG_SPI_FLASH | |
| 270 | #define CONFIG_EXYNOS_SPI | |
| 271 | #define CONFIG_CMD_SF | |
| 272 | #define CONFIG_CMD_SPI | |
| 273 | #define CONFIG_SPI_FLASH_WINBOND | |
| c7c4fe07 | 274 | #define CONFIG_SPI_FLASH_GIGADEVICE |
| 3a8a7001 HR |
275 | #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 |
| 276 | #define CONFIG_SF_DEFAULT_SPEED 50000000 | |
| 277 | #define EXYNOS5_SPI_NUM_CONTROLLERS 5 | |
| 278 | #endif | |
| 279 | ||
| 280 | #ifdef CONFIG_ENV_IS_IN_SPI_FLASH | |
| 281 | #define CONFIG_ENV_SPI_MODE SPI_MODE_0 | |
| 282 | #define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE | |
| 283 | #define CONFIG_ENV_SPI_BUS 1 | |
| 284 | #define CONFIG_ENV_SPI_MAX_HZ 50000000 | |
| 285 | #endif | |
| 286 | ||
| 0d146a56 | 287 | /* PMIC */ |
| 211e8438 RS |
288 | #define CONFIG_POWER |
| 289 | #define CONFIG_POWER_I2C | |
| 290 | #define CONFIG_POWER_MAX77686 | |
| 0d146a56 | 291 | |
| 3a8a7001 HR |
292 | /* SPI */ |
| 293 | #define CONFIG_ENV_IS_IN_SPI_FLASH | |
| 294 | #define CONFIG_SPI_FLASH | |
| 295 | ||
| 296 | #ifdef CONFIG_SPI_FLASH | |
| 297 | #define CONFIG_EXYNOS_SPI | |
| 298 | #define CONFIG_CMD_SF | |
| 299 | #define CONFIG_CMD_SPI | |
| 300 | #define CONFIG_SPI_FLASH_WINBOND | |
| 301 | #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 | |
| 302 | #define CONFIG_SF_DEFAULT_SPEED 50000000 | |
| 303 | #define EXYNOS5_SPI_NUM_CONTROLLERS 5 | |
| 304 | #endif | |
| 305 | ||
| 306 | #ifdef CONFIG_ENV_IS_IN_SPI_FLASH | |
| 307 | #define CONFIG_ENV_SPI_MODE SPI_MODE_0 | |
| 308 | #define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE | |
| 309 | #define CONFIG_ENV_SPI_BUS 1 | |
| 310 | #define CONFIG_ENV_SPI_MAX_HZ 50000000 | |
| 311 | #endif | |
| 312 | ||
| bf936210 CK |
313 | /* Ethernet Controllor Driver */ |
| 314 | #ifdef CONFIG_CMD_NET | |
| 315 | #define CONFIG_SMC911X | |
| 316 | #define CONFIG_SMC911X_BASE 0x5000000 | |
| 317 | #define CONFIG_SMC911X_16_BIT | |
| 318 | #define CONFIG_ENV_SROM_BANK 1 | |
| 319 | #endif /*CONFIG_CMD_NET*/ | |
| 320 | ||
| 061562c4 CK |
321 | /* Enable PXE Support */ |
| 322 | #ifdef CONFIG_CMD_NET | |
| 323 | #define CONFIG_CMD_PXE | |
| 324 | #define CONFIG_MENU | |
| 325 | #endif | |
| 326 | ||
| 36364714 RS |
327 | /* Sound */ |
| 328 | #define CONFIG_CMD_SOUND | |
| 329 | #ifdef CONFIG_CMD_SOUND | |
| 330 | #define CONFIG_SOUND | |
| 331 | #define CONFIG_I2S | |
| cfa6df19 | 332 | #define CONFIG_SOUND_MAX98095 |
| 36364714 RS |
333 | #define CONFIG_SOUND_WM8994 |
| 334 | #endif | |
| 335 | ||
| 0aee53ba CK |
336 | /* Enable devicetree support */ |
| 337 | #define CONFIG_OF_LIBFDT | |
| 338 | ||
| 23b479b2 SG |
339 | /* SHA hashing */ |
| 340 | #define CONFIG_CMD_HASH | |
| 341 | #define CONFIG_HASH_VERIFY | |
| 342 | #define CONFIG_SHA1 | |
| 343 | #define CONFIG_SHA256 | |
| 344 | ||
| 9b572852 AK |
345 | /* Display */ |
| 346 | #define CONFIG_LCD | |
| 99e51629 | 347 | #ifdef CONFIG_LCD |
| 9b572852 AK |
348 | #define CONFIG_EXYNOS_FB |
| 349 | #define CONFIG_EXYNOS_DP | |
| 350 | #define LCD_XRES 2560 | |
| 351 | #define LCD_YRES 1600 | |
| 352 | #define LCD_BPP LCD_COLOR16 | |
| 99e51629 | 353 | #endif |
| 9b572852 | 354 | |
| 4f3bfa97 AS |
355 | /* Enable Time Command */ |
| 356 | #define CONFIG_CMD_TIME | |
| 357 | ||
| 0aee53ba | 358 | #endif /* __CONFIG_H */ |