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Commit | Line | Data |
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c8a7d9da WH |
1 | /* |
2 | * Copyright 2014 Freescale Semiconductor, Inc. | |
3 | * | |
4 | * SPDX-License-Identifier: GPL-2.0+ | |
5 | */ | |
6 | ||
7 | #ifndef __CONFIG_H | |
8 | #define __CONFIG_H | |
9 | ||
aeb901f2 | 10 | #define CONFIG_ARMV7_PSCI_1_0 |
340848b1 | 11 | |
3288628a HZ |
12 | #define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR |
13 | ||
18fb0e3c | 14 | #define CONFIG_SYS_FSL_CLK |
c8a7d9da | 15 | |
c8a7d9da | 16 | #define CONFIG_SKIP_LOWLEVEL_INIT |
99e1bd42 | 17 | #define CONFIG_DEEP_SLEEP |
c8a7d9da WH |
18 | |
19 | /* | |
20 | * Size of malloc() pool | |
21 | */ | |
22 | #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024 * 1024) | |
23 | ||
24 | #define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR | |
25 | #define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE | |
26 | ||
c8a7d9da WH |
27 | #define CONFIG_SYS_CLK_FREQ 100000000 |
28 | #define CONFIG_DDR_CLK_FREQ 100000000 | |
29 | ||
a88cc3bd YS |
30 | #define DDR_SDRAM_CFG 0x470c0008 |
31 | #define DDR_CS0_BNDS 0x008000bf | |
32 | #define DDR_CS0_CONFIG 0x80014302 | |
33 | #define DDR_TIMING_CFG_0 0x50550004 | |
34 | #define DDR_TIMING_CFG_1 0xbcb38c56 | |
35 | #define DDR_TIMING_CFG_2 0x0040d120 | |
36 | #define DDR_TIMING_CFG_3 0x010e1000 | |
37 | #define DDR_TIMING_CFG_4 0x00000001 | |
38 | #define DDR_TIMING_CFG_5 0x03401400 | |
39 | #define DDR_SDRAM_CFG_2 0x00401010 | |
40 | #define DDR_SDRAM_MODE 0x00061c60 | |
41 | #define DDR_SDRAM_MODE_2 0x00180000 | |
42 | #define DDR_SDRAM_INTERVAL 0x18600618 | |
43 | #define DDR_DDR_WRLVL_CNTL 0x8655f605 | |
44 | #define DDR_DDR_WRLVL_CNTL_2 0x05060607 | |
45 | #define DDR_DDR_WRLVL_CNTL_3 0x05050505 | |
46 | #define DDR_DDR_CDR1 0x80040000 | |
47 | #define DDR_DDR_CDR2 0x00000001 | |
48 | #define DDR_SDRAM_CLK_CNTL 0x02000000 | |
49 | #define DDR_DDR_ZQ_CNTL 0x89080600 | |
50 | #define DDR_CS0_CONFIG_2 0 | |
51 | #define DDR_SDRAM_CFG_MEM_EN 0x80000000 | |
99e1bd42 TY |
52 | #define SDRAM_CFG2_D_INIT 0x00000010 |
53 | #define DDR_CDR2_VREF_TRAIN_EN 0x00000080 | |
54 | #define SDRAM_CFG2_FRC_SR 0x80000000 | |
55 | #define SDRAM_CFG_BI 0x00000001 | |
a88cc3bd | 56 | |
8415bb68 AW |
57 | #ifdef CONFIG_RAMBOOT_PBL |
58 | #define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1021atwr/ls102xa_pbi.cfg | |
59 | #endif | |
60 | ||
61 | #ifdef CONFIG_SD_BOOT | |
947cee11 AW |
62 | #ifdef CONFIG_SD_BOOT_QSPI |
63 | #define CONFIG_SYS_FSL_PBL_RCW \ | |
64 | board/freescale/ls1021atwr/ls102xa_rcw_sd_qspi.cfg | |
65 | #else | |
66 | #define CONFIG_SYS_FSL_PBL_RCW \ | |
67 | board/freescale/ls1021atwr/ls102xa_rcw_sd_ifc.cfg | |
68 | #endif | |
e7e720c2 SG |
69 | |
70 | #ifdef CONFIG_SECURE_BOOT | |
e7e720c2 SG |
71 | /* |
72 | * HDR would be appended at end of image and copied to DDR along | |
73 | * with U-Boot image. | |
74 | */ | |
693d4c9f | 75 | #define CONFIG_U_BOOT_HDR_SIZE (16 << 10) |
e7e720c2 | 76 | #endif /* ifdef CONFIG_SECURE_BOOT */ |
8415bb68 AW |
77 | |
78 | #define CONFIG_SPL_TEXT_BASE 0x10000000 | |
79 | #define CONFIG_SPL_MAX_SIZE 0x1a000 | |
80 | #define CONFIG_SPL_STACK 0x1001d000 | |
81 | #define CONFIG_SPL_PAD_TO 0x1c000 | |
8415bb68 | 82 | |
99e1bd42 TY |
83 | #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE + \ |
84 | CONFIG_SYS_MONITOR_LEN) | |
8415bb68 AW |
85 | #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 |
86 | #define CONFIG_SPL_BSS_START_ADDR 0x80100000 | |
87 | #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 | |
e7e720c2 SG |
88 | |
89 | #ifdef CONFIG_U_BOOT_HDR_SIZE | |
90 | /* | |
91 | * HDR would be appended at end of image and copied to DDR along | |
92 | * with U-Boot image. Here u-boot max. size is 512K. So if binary | |
93 | * size increases then increase this size in case of secure boot as | |
94 | * it uses raw u-boot image instead of fit image. | |
95 | */ | |
9b6639fa | 96 | #define CONFIG_SYS_MONITOR_LEN (0x100000 + CONFIG_U_BOOT_HDR_SIZE) |
e7e720c2 | 97 | #else |
9b6639fa | 98 | #define CONFIG_SYS_MONITOR_LEN 0x100000 |
e7e720c2 | 99 | #endif /* ifdef CONFIG_U_BOOT_HDR_SIZE */ |
8415bb68 AW |
100 | #endif |
101 | ||
c8a7d9da WH |
102 | #define CONFIG_NR_DRAM_BANKS 1 |
103 | #define PHYS_SDRAM 0x80000000 | |
104 | #define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024) | |
105 | ||
106 | #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL | |
107 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE | |
108 | ||
4c59ab9c AW |
109 | #if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \ |
110 | !defined(CONFIG_QSPI_BOOT) | |
eaa859e7 | 111 | #define CONFIG_U_QE |
5aa03ddd | 112 | #define CONFIG_SYS_QE_FMAN_FW_IN_NOR |
eaa859e7 ZQ |
113 | #endif |
114 | ||
c8a7d9da WH |
115 | /* |
116 | * IFC Definitions | |
117 | */ | |
947cee11 | 118 | #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) |
c8a7d9da WH |
119 | #define CONFIG_FSL_IFC |
120 | #define CONFIG_SYS_FLASH_BASE 0x60000000 | |
121 | #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE | |
122 | ||
123 | #define CONFIG_SYS_NOR0_CSPR_EXT (0x0) | |
124 | #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ | |
125 | CSPR_PORT_SIZE_16 | \ | |
126 | CSPR_MSEL_NOR | \ | |
127 | CSPR_V) | |
128 | #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024) | |
129 | ||
130 | /* NOR Flash Timing Params */ | |
131 | #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ | |
132 | CSOR_NOR_TRHZ_80) | |
133 | #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ | |
134 | FTIM0_NOR_TEADC(0x5) | \ | |
135 | FTIM0_NOR_TAVDS(0x0) | \ | |
136 | FTIM0_NOR_TEAHC(0x5)) | |
137 | #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ | |
138 | FTIM1_NOR_TRAD_NOR(0x1A) | \ | |
139 | FTIM1_NOR_TSEQRAD_NOR(0x13)) | |
140 | #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ | |
141 | FTIM2_NOR_TCH(0x4) | \ | |
142 | FTIM2_NOR_TWP(0x1c) | \ | |
143 | FTIM2_NOR_TWPH(0x0e)) | |
144 | #define CONFIG_SYS_NOR_FTIM3 0 | |
145 | ||
146 | #define CONFIG_FLASH_CFI_DRIVER | |
147 | #define CONFIG_SYS_FLASH_CFI | |
148 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE | |
149 | #define CONFIG_SYS_FLASH_QUIET_TEST | |
150 | #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ | |
151 | ||
152 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ | |
153 | #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ | |
154 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ | |
155 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ | |
156 | ||
157 | #define CONFIG_SYS_FLASH_EMPTY_INFO | |
158 | #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS } | |
159 | ||
160 | #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS | |
272c5265 | 161 | #define CONFIG_SYS_WRITE_SWAPPED_DATA |
d612f0ab | 162 | #endif |
c8a7d9da WH |
163 | |
164 | /* CPLD */ | |
165 | ||
166 | #define CONFIG_SYS_CPLD_BASE 0x7fb00000 | |
167 | #define CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE | |
168 | ||
169 | #define CONFIG_SYS_FPGA_CSPR_EXT (0x0) | |
170 | #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \ | |
171 | CSPR_PORT_SIZE_8 | \ | |
172 | CSPR_MSEL_GPCM | \ | |
173 | CSPR_V) | |
174 | #define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024) | |
175 | #define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ | |
176 | CSOR_NOR_NOR_MODE_AVD_NOR | \ | |
177 | CSOR_NOR_TRHZ_80) | |
178 | ||
179 | /* CPLD Timing parameters for IFC GPCM */ | |
180 | #define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xf) | \ | |
181 | FTIM0_GPCM_TEADC(0xf) | \ | |
182 | FTIM0_GPCM_TEAHC(0xf)) | |
183 | #define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ | |
184 | FTIM1_GPCM_TRAD(0x3f)) | |
185 | #define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0xf) | \ | |
186 | FTIM2_GPCM_TCH(0xf) | \ | |
187 | FTIM2_GPCM_TWP(0xff)) | |
188 | #define CONFIG_SYS_FPGA_FTIM3 0x0 | |
189 | #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT | |
190 | #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR | |
191 | #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK | |
192 | #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR | |
193 | #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 | |
194 | #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 | |
195 | #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 | |
196 | #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 | |
197 | #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_FPGA_CSPR_EXT | |
198 | #define CONFIG_SYS_CSPR1 CONFIG_SYS_FPGA_CSPR | |
199 | #define CONFIG_SYS_AMASK1 CONFIG_SYS_FPGA_AMASK | |
200 | #define CONFIG_SYS_CSOR1 CONFIG_SYS_FPGA_CSOR | |
201 | #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_FPGA_FTIM0 | |
202 | #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_FPGA_FTIM1 | |
203 | #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_FPGA_FTIM2 | |
204 | #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_FPGA_FTIM3 | |
205 | ||
206 | /* | |
207 | * Serial Port | |
208 | */ | |
55d53ab4 | 209 | #ifdef CONFIG_LPUART |
55d53ab4 AW |
210 | #define CONFIG_LPUART_32B_REG |
211 | #else | |
c8a7d9da | 212 | #define CONFIG_CONS_INDEX 1 |
c8a7d9da | 213 | #define CONFIG_SYS_NS16550_SERIAL |
f833cd62 | 214 | #ifndef CONFIG_DM_SERIAL |
c8a7d9da | 215 | #define CONFIG_SYS_NS16550_REG_SIZE 1 |
f833cd62 | 216 | #endif |
c8a7d9da | 217 | #define CONFIG_SYS_NS16550_CLK get_serial_clock() |
55d53ab4 | 218 | #endif |
c8a7d9da | 219 | |
c8a7d9da WH |
220 | /* |
221 | * I2C | |
222 | */ | |
c8a7d9da WH |
223 | #define CONFIG_SYS_I2C |
224 | #define CONFIG_SYS_I2C_MXC | |
03544c66 AA |
225 | #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ |
226 | #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ | |
f8cb101e | 227 | #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ |
c8a7d9da | 228 | |
5175a288 | 229 | /* EEPROM */ |
5175a288 AW |
230 | #define CONFIG_ID_EEPROM |
231 | #define CONFIG_SYS_I2C_EEPROM_NXID | |
232 | #define CONFIG_SYS_EEPROM_BUS_NUM 1 | |
233 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x53 | |
234 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 | |
235 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 | |
236 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 | |
5175a288 | 237 | |
c8a7d9da WH |
238 | /* |
239 | * MMC | |
240 | */ | |
c8a7d9da | 241 | #define CONFIG_FSL_ESDHC |
c8a7d9da | 242 | |
9dd3d3c0 | 243 | /* SPI */ |
947cee11 | 244 | #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) |
9dd3d3c0 | 245 | /* QSPI */ |
d612f0ab AW |
246 | #define QSPI0_AMBA_BASE 0x40000000 |
247 | #define FSL_QSPI_FLASH_SIZE (1 << 24) | |
248 | #define FSL_QSPI_FLASH_NUM 2 | |
249 | ||
03d1d568 | 250 | /* DSPI */ |
03d1d568 YY |
251 | #endif |
252 | ||
9dd3d3c0 HW |
253 | /* DM SPI */ |
254 | #if defined(CONFIG_FSL_DSPI) || defined(CONFIG_FSL_QSPI) | |
9dd3d3c0 HW |
255 | #define CONFIG_DM_SPI_FLASH |
256 | #endif | |
d612f0ab | 257 | |
b4ecc8c6 WH |
258 | /* |
259 | * Video | |
260 | */ | |
b215fb3f | 261 | #ifdef CONFIG_VIDEO_FSL_DCU_FB |
b4ecc8c6 WH |
262 | #define CONFIG_VIDEO_LOGO |
263 | #define CONFIG_VIDEO_BMP_LOGO | |
264 | ||
265 | #define CONFIG_FSL_DCU_SII9022A | |
266 | #define CONFIG_SYS_I2C_DVI_BUS_NUM 1 | |
267 | #define CONFIG_SYS_I2C_DVI_ADDR 0x39 | |
268 | #endif | |
269 | ||
c8a7d9da WH |
270 | /* |
271 | * eTSEC | |
272 | */ | |
273 | #define CONFIG_TSEC_ENET | |
274 | ||
275 | #ifdef CONFIG_TSEC_ENET | |
276 | #define CONFIG_MII | |
277 | #define CONFIG_MII_DEFAULT_TSEC 1 | |
278 | #define CONFIG_TSEC1 1 | |
279 | #define CONFIG_TSEC1_NAME "eTSEC1" | |
280 | #define CONFIG_TSEC2 1 | |
281 | #define CONFIG_TSEC2_NAME "eTSEC2" | |
282 | #define CONFIG_TSEC3 1 | |
283 | #define CONFIG_TSEC3_NAME "eTSEC3" | |
284 | ||
285 | #define TSEC1_PHY_ADDR 2 | |
286 | #define TSEC2_PHY_ADDR 0 | |
287 | #define TSEC3_PHY_ADDR 1 | |
288 | ||
289 | #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
290 | #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
291 | #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
292 | ||
293 | #define TSEC1_PHYIDX 0 | |
294 | #define TSEC2_PHYIDX 0 | |
295 | #define TSEC3_PHYIDX 0 | |
296 | ||
297 | #define CONFIG_ETHPRIME "eTSEC1" | |
298 | ||
c8a7d9da WH |
299 | #define CONFIG_PHY_ATHEROS |
300 | ||
301 | #define CONFIG_HAS_ETH0 | |
302 | #define CONFIG_HAS_ETH1 | |
303 | #define CONFIG_HAS_ETH2 | |
304 | #endif | |
305 | ||
da419027 | 306 | /* PCIe */ |
b38eaec5 RD |
307 | #define CONFIG_PCIE1 /* PCIE controller 1 */ |
308 | #define CONFIG_PCIE2 /* PCIE controller 2 */ | |
da419027 | 309 | |
180b8688 | 310 | #ifdef CONFIG_PCI |
180b8688 | 311 | #define CONFIG_PCI_SCAN_SHOW |
180b8688 ML |
312 | #endif |
313 | ||
c8a7d9da | 314 | #define CONFIG_CMDLINE_TAG |
8415bb68 | 315 | |
1a2826f6 | 316 | #define CONFIG_PEN_ADDR_BIG_ENDIAN |
435acd83 | 317 | #define CONFIG_LAYERSCAPE_NS_ACCESS |
1a2826f6 | 318 | #define CONFIG_SMP_PEN_ADDR 0x01ee0200 |
e4916e85 | 319 | #define COUNTER_FREQUENCY 12500000 |
1a2826f6 | 320 | |
c8a7d9da | 321 | #define CONFIG_HWCONFIG |
03c22449 ZZ |
322 | #define HWCONFIG_BUFFER_SIZE 256 |
323 | ||
324 | #define CONFIG_FSL_DEVICE_DISABLE | |
c8a7d9da | 325 | |
a65d7408 AW |
326 | #define BOOT_TARGET_DEVICES(func) \ |
327 | func(MMC, mmc, 0) \ | |
328 | func(USB, usb, 0) | |
329 | #include <config_distro_bootcmd.h> | |
c8a7d9da | 330 | |
55d53ab4 AW |
331 | #ifdef CONFIG_LPUART |
332 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
333 | "bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0" \ | |
7ff7166c | 334 | "initrd_high=0xffffffff\0" \ |
a65d7408 AW |
335 | "fdt_high=0xffffffff\0" \ |
336 | "fdt_addr=0x64f00000\0" \ | |
337 | "kernel_addr=0x65000000\0" \ | |
338 | "scriptaddr=0x80000000\0" \ | |
b8ae6798 | 339 | "scripthdraddr=0x80080000\0" \ |
a65d7408 AW |
340 | "fdtheader_addr_r=0x80100000\0" \ |
341 | "kernelheader_addr_r=0x80200000\0" \ | |
342 | "kernel_addr_r=0x81000000\0" \ | |
343 | "fdt_addr_r=0x90000000\0" \ | |
344 | "ramdisk_addr_r=0xa0000000\0" \ | |
345 | "load_addr=0xa0000000\0" \ | |
346 | "kernel_size=0x2800000\0" \ | |
397a173e SL |
347 | "kernel_addr_sd=0x8000\0" \ |
348 | "kernel_size_sd=0x14000\0" \ | |
a65d7408 AW |
349 | BOOTENV \ |
350 | "boot_scripts=ls1021atwr_boot.scr\0" \ | |
b8ae6798 | 351 | "boot_script_hdr=hdr_ls1021atwr_bs.out\0" \ |
a65d7408 AW |
352 | "scan_dev_for_boot_part=" \ |
353 | "part list ${devtype} ${devnum} devplist; " \ | |
354 | "env exists devplist || setenv devplist 1; " \ | |
355 | "for distro_bootpart in ${devplist}; do " \ | |
356 | "if fstype ${devtype} " \ | |
357 | "${devnum}:${distro_bootpart} " \ | |
358 | "bootfstype; then " \ | |
359 | "run scan_dev_for_boot; " \ | |
360 | "fi; " \ | |
361 | "done\0" \ | |
b8ae6798 SG |
362 | "scan_dev_for_boot=" \ |
363 | "echo Scanning ${devtype} " \ | |
364 | "${devnum}:${distro_bootpart}...; " \ | |
365 | "for prefix in ${boot_prefixes}; do " \ | |
366 | "run scan_dev_for_scripts; " \ | |
367 | "done;" \ | |
368 | "\0" \ | |
369 | "boot_a_script=" \ | |
370 | "load ${devtype} ${devnum}:${distro_bootpart} " \ | |
371 | "${scriptaddr} ${prefix}${script}; " \ | |
372 | "env exists secureboot && load ${devtype} " \ | |
373 | "${devnum}:${distro_bootpart} " \ | |
374 | "${scripthdraddr} ${prefix}${boot_script_hdr} " \ | |
375 | "&& esbc_validate ${scripthdraddr};" \ | |
376 | "source ${scriptaddr}\0" \ | |
a65d7408 AW |
377 | "installer=load mmc 0:2 $load_addr " \ |
378 | "/flex_installer_arm32.itb; " \ | |
379 | "bootm $load_addr#ls1021atwr\0" \ | |
380 | "qspi_bootcmd=echo Trying load from qspi..;" \ | |
381 | "sf probe && sf read $load_addr " \ | |
382 | "$kernel_addr $kernel_size && bootm $load_addr#$board\0" \ | |
383 | "nor_bootcmd=echo Trying load from nor..;" \ | |
384 | "cp.b $kernel_addr $load_addr " \ | |
385 | "$kernel_size && bootm $load_addr#$board\0" | |
55d53ab4 | 386 | #else |
c8a7d9da WH |
387 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
388 | "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \ | |
7ff7166c | 389 | "initrd_high=0xffffffff\0" \ |
a65d7408 AW |
390 | "fdt_high=0xffffffff\0" \ |
391 | "fdt_addr=0x64f00000\0" \ | |
9b457cc6 VPB |
392 | "kernel_addr=0x61000000\0" \ |
393 | "kernelheader_addr=0x60800000\0" \ | |
a65d7408 | 394 | "scriptaddr=0x80000000\0" \ |
b8ae6798 | 395 | "scripthdraddr=0x80080000\0" \ |
a65d7408 AW |
396 | "fdtheader_addr_r=0x80100000\0" \ |
397 | "kernelheader_addr_r=0x80200000\0" \ | |
398 | "kernel_addr_r=0x81000000\0" \ | |
9b457cc6 | 399 | "kernelheader_size=0x40000\0" \ |
a65d7408 AW |
400 | "fdt_addr_r=0x90000000\0" \ |
401 | "ramdisk_addr_r=0xa0000000\0" \ | |
402 | "load_addr=0xa0000000\0" \ | |
403 | "kernel_size=0x2800000\0" \ | |
9b457cc6 VPB |
404 | "kernel_addr_sd=0x8000\0" \ |
405 | "kernel_size_sd=0x14000\0" \ | |
406 | "kernelhdr_addr_sd=0x4000\0" \ | |
407 | "kernelhdr_size_sd=0x10\0" \ | |
a65d7408 AW |
408 | BOOTENV \ |
409 | "boot_scripts=ls1021atwr_boot.scr\0" \ | |
b8ae6798 | 410 | "boot_script_hdr=hdr_ls1021atwr_bs.out\0" \ |
a65d7408 AW |
411 | "scan_dev_for_boot_part=" \ |
412 | "part list ${devtype} ${devnum} devplist; " \ | |
413 | "env exists devplist || setenv devplist 1; " \ | |
414 | "for distro_bootpart in ${devplist}; do " \ | |
415 | "if fstype ${devtype} " \ | |
416 | "${devnum}:${distro_bootpart} " \ | |
417 | "bootfstype; then " \ | |
418 | "run scan_dev_for_boot; " \ | |
419 | "fi; " \ | |
420 | "done\0" \ | |
b8ae6798 SG |
421 | "scan_dev_for_boot=" \ |
422 | "echo Scanning ${devtype} " \ | |
423 | "${devnum}:${distro_bootpart}...; " \ | |
424 | "for prefix in ${boot_prefixes}; do " \ | |
425 | "run scan_dev_for_scripts; " \ | |
426 | "done;" \ | |
427 | "\0" \ | |
428 | "boot_a_script=" \ | |
429 | "load ${devtype} ${devnum}:${distro_bootpart} " \ | |
430 | "${scriptaddr} ${prefix}${script}; " \ | |
431 | "env exists secureboot && load ${devtype} " \ | |
432 | "${devnum}:${distro_bootpart} " \ | |
433 | "${scripthdraddr} ${prefix}${boot_script_hdr} " \ | |
434 | "&& esbc_validate ${scripthdraddr};" \ | |
435 | "source ${scriptaddr}\0" \ | |
a65d7408 AW |
436 | "qspi_bootcmd=echo Trying load from qspi..;" \ |
437 | "sf probe && sf read $load_addr " \ | |
9b457cc6 VPB |
438 | "$kernel_addr $kernel_size; env exists secureboot " \ |
439 | "&& sf read $kernelheader_addr_r $kernelheader_addr " \ | |
440 | "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \ | |
441 | "bootm $load_addr#$board\0" \ | |
a65d7408 AW |
442 | "nor_bootcmd=echo Trying load from nor..;" \ |
443 | "cp.b $kernel_addr $load_addr " \ | |
9b457cc6 VPB |
444 | "$kernel_size; env exists secureboot " \ |
445 | "&& cp.b $kernelheader_addr $kernelheader_addr_r " \ | |
446 | "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \ | |
447 | "bootm $load_addr#$board\0" \ | |
397a173e SL |
448 | "sd_bootcmd=echo Trying load from SD ..;" \ |
449 | "mmcinfo && mmc read $load_addr " \ | |
450 | "$kernel_addr_sd $kernel_size_sd && " \ | |
9b457cc6 VPB |
451 | "env exists secureboot && mmc read $kernelheader_addr_r " \ |
452 | "$kernelhdr_addr_sd $kernelhdr_size_sd " \ | |
453 | " && esbc_validate ${kernelheader_addr_r};" \ | |
397a173e | 454 | "bootm $load_addr#$board\0" |
55d53ab4 | 455 | #endif |
c8a7d9da | 456 | |
a65d7408 AW |
457 | #undef CONFIG_BOOTCOMMAND |
458 | #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) | |
9b457cc6 VPB |
459 | #define CONFIG_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd" \ |
460 | "env exists secureboot && esbc_halt" | |
397a173e | 461 | #elif defined(CONFIG_SD_BOOT) |
9b457cc6 VPB |
462 | #define CONFIG_BOOTCOMMAND "run distro_bootcmd; run sd_bootcmd; " \ |
463 | "env exists secureboot && esbc_halt;" | |
a65d7408 | 464 | #else |
9b457cc6 VPB |
465 | #define CONFIG_BOOTCOMMAND "run distro_bootcmd; run nor_bootcmd;" \ |
466 | "env exists secureboot && esbc_halt;" | |
a65d7408 AW |
467 | #endif |
468 | ||
c8a7d9da WH |
469 | /* |
470 | * Miscellaneous configurable options | |
471 | */ | |
c8a7d9da | 472 | |
c8a7d9da WH |
473 | #define CONFIG_SYS_MEMTEST_START 0x80000000 |
474 | #define CONFIG_SYS_MEMTEST_END 0x9fffffff | |
475 | ||
476 | #define CONFIG_SYS_LOAD_ADDR 0x82000000 | |
c8a7d9da | 477 | |
660673af XL |
478 | #define CONFIG_LS102XA_STREAM_ID |
479 | ||
c8a7d9da WH |
480 | #define CONFIG_SYS_INIT_SP_OFFSET \ |
481 | (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) | |
482 | #define CONFIG_SYS_INIT_SP_ADDR \ | |
483 | (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) | |
484 | ||
8415bb68 AW |
485 | #ifdef CONFIG_SPL_BUILD |
486 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE | |
487 | #else | |
c8a7d9da | 488 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ |
8415bb68 | 489 | #endif |
c8a7d9da | 490 | |
615bfce5 | 491 | #define CONFIG_SYS_QE_FW_ADDR 0x60940000 |
eaa859e7 | 492 | |
c8a7d9da WH |
493 | /* |
494 | * Environment | |
495 | */ | |
496 | #define CONFIG_ENV_OVERWRITE | |
497 | ||
8415bb68 | 498 | #if defined(CONFIG_SD_BOOT) |
615bfce5 | 499 | #define CONFIG_ENV_OFFSET 0x300000 |
8415bb68 AW |
500 | #define CONFIG_SYS_MMC_ENV_DEV 0 |
501 | #define CONFIG_ENV_SIZE 0x20000 | |
d612f0ab | 502 | #elif defined(CONFIG_QSPI_BOOT) |
d612f0ab | 503 | #define CONFIG_ENV_SIZE 0x2000 |
615bfce5 | 504 | #define CONFIG_ENV_OFFSET 0x300000 |
d612f0ab | 505 | #define CONFIG_ENV_SECT_SIZE 0x10000 |
8415bb68 | 506 | #else |
615bfce5 | 507 | #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x300000) |
c8a7d9da WH |
508 | #define CONFIG_ENV_SIZE 0x20000 |
509 | #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ | |
8415bb68 | 510 | #endif |
c8a7d9da | 511 | |
4ba4a095 RG |
512 | #define CONFIG_MISC_INIT_R |
513 | ||
ef6c55a2 | 514 | #include <asm/fsl_secure_boot.h> |
cc7b8b9a | 515 | #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ |
4ba4a095 | 516 | |
c8a7d9da | 517 | #endif |