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Commit | Line | Data |
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c8a7d9da WH |
1 | /* |
2 | * Copyright 2014 Freescale Semiconductor, Inc. | |
3 | * | |
4 | * SPDX-License-Identifier: GPL-2.0+ | |
5 | */ | |
6 | ||
7 | #ifndef __CONFIG_H | |
8 | #define __CONFIG_H | |
9 | ||
c8a7d9da WH |
10 | #define CONFIG_LS102XA |
11 | ||
aeb901f2 | 12 | #define CONFIG_ARMV7_PSCI_1_0 |
340848b1 | 13 | |
3288628a HZ |
14 | #define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR |
15 | ||
18fb0e3c | 16 | #define CONFIG_SYS_FSL_CLK |
c8a7d9da | 17 | |
c8a7d9da WH |
18 | #define CONFIG_SKIP_LOWLEVEL_INIT |
19 | #define CONFIG_BOARD_EARLY_INIT_F | |
99e1bd42 | 20 | #define CONFIG_DEEP_SLEEP |
c8a7d9da WH |
21 | |
22 | /* | |
23 | * Size of malloc() pool | |
24 | */ | |
25 | #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024 * 1024) | |
26 | ||
27 | #define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR | |
28 | #define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE | |
29 | ||
10a28644 RM |
30 | /* |
31 | * USB | |
32 | */ | |
33 | ||
34 | /* | |
35 | * EHCI Support - disbaled by default as | |
36 | * there is no signal coming out of soc on | |
37 | * this board for this controller. However, | |
38 | * the silicon still has this controller, | |
39 | * and anyone can use this controller by | |
40 | * taking signals out on their board. | |
41 | */ | |
42 | ||
43 | /*#define CONFIG_HAS_FSL_DR_USB*/ | |
44 | ||
45 | #ifdef CONFIG_HAS_FSL_DR_USB | |
46 | #define CONFIG_USB_EHCI | |
47 | #define CONFIG_USB_EHCI_FSL | |
48 | #define CONFIG_EHCI_HCD_INIT_AFTER_RESET | |
49 | #endif | |
50 | ||
51 | /* XHCI Support - enabled by default */ | |
52 | #define CONFIG_HAS_FSL_XHCI_USB | |
53 | ||
54 | #ifdef CONFIG_HAS_FSL_XHCI_USB | |
55 | #define CONFIG_USB_XHCI_FSL | |
10a28644 RM |
56 | #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 |
57 | #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 | |
58 | #endif | |
59 | ||
c8a7d9da WH |
60 | /* |
61 | * Generic Timer Definitions | |
62 | */ | |
63 | #define GENERIC_TIMER_CLK 12500000 | |
64 | ||
65 | #define CONFIG_SYS_CLK_FREQ 100000000 | |
66 | #define CONFIG_DDR_CLK_FREQ 100000000 | |
67 | ||
a88cc3bd YS |
68 | #define DDR_SDRAM_CFG 0x470c0008 |
69 | #define DDR_CS0_BNDS 0x008000bf | |
70 | #define DDR_CS0_CONFIG 0x80014302 | |
71 | #define DDR_TIMING_CFG_0 0x50550004 | |
72 | #define DDR_TIMING_CFG_1 0xbcb38c56 | |
73 | #define DDR_TIMING_CFG_2 0x0040d120 | |
74 | #define DDR_TIMING_CFG_3 0x010e1000 | |
75 | #define DDR_TIMING_CFG_4 0x00000001 | |
76 | #define DDR_TIMING_CFG_5 0x03401400 | |
77 | #define DDR_SDRAM_CFG_2 0x00401010 | |
78 | #define DDR_SDRAM_MODE 0x00061c60 | |
79 | #define DDR_SDRAM_MODE_2 0x00180000 | |
80 | #define DDR_SDRAM_INTERVAL 0x18600618 | |
81 | #define DDR_DDR_WRLVL_CNTL 0x8655f605 | |
82 | #define DDR_DDR_WRLVL_CNTL_2 0x05060607 | |
83 | #define DDR_DDR_WRLVL_CNTL_3 0x05050505 | |
84 | #define DDR_DDR_CDR1 0x80040000 | |
85 | #define DDR_DDR_CDR2 0x00000001 | |
86 | #define DDR_SDRAM_CLK_CNTL 0x02000000 | |
87 | #define DDR_DDR_ZQ_CNTL 0x89080600 | |
88 | #define DDR_CS0_CONFIG_2 0 | |
89 | #define DDR_SDRAM_CFG_MEM_EN 0x80000000 | |
99e1bd42 TY |
90 | #define SDRAM_CFG2_D_INIT 0x00000010 |
91 | #define DDR_CDR2_VREF_TRAIN_EN 0x00000080 | |
92 | #define SDRAM_CFG2_FRC_SR 0x80000000 | |
93 | #define SDRAM_CFG_BI 0x00000001 | |
a88cc3bd | 94 | |
8415bb68 AW |
95 | #ifdef CONFIG_RAMBOOT_PBL |
96 | #define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1021atwr/ls102xa_pbi.cfg | |
97 | #endif | |
98 | ||
99 | #ifdef CONFIG_SD_BOOT | |
947cee11 AW |
100 | #ifdef CONFIG_SD_BOOT_QSPI |
101 | #define CONFIG_SYS_FSL_PBL_RCW \ | |
102 | board/freescale/ls1021atwr/ls102xa_rcw_sd_qspi.cfg | |
103 | #else | |
104 | #define CONFIG_SYS_FSL_PBL_RCW \ | |
105 | board/freescale/ls1021atwr/ls102xa_rcw_sd_ifc.cfg | |
106 | #endif | |
8415bb68 AW |
107 | #define CONFIG_SPL_FRAMEWORK |
108 | #define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds" | |
e7e720c2 SG |
109 | |
110 | #ifdef CONFIG_SECURE_BOOT | |
e7e720c2 SG |
111 | /* |
112 | * HDR would be appended at end of image and copied to DDR along | |
113 | * with U-Boot image. | |
114 | */ | |
693d4c9f | 115 | #define CONFIG_U_BOOT_HDR_SIZE (16 << 10) |
e7e720c2 | 116 | #endif /* ifdef CONFIG_SECURE_BOOT */ |
8415bb68 AW |
117 | |
118 | #define CONFIG_SPL_TEXT_BASE 0x10000000 | |
119 | #define CONFIG_SPL_MAX_SIZE 0x1a000 | |
120 | #define CONFIG_SPL_STACK 0x1001d000 | |
121 | #define CONFIG_SPL_PAD_TO 0x1c000 | |
122 | #define CONFIG_SYS_TEXT_BASE 0x82000000 | |
123 | ||
99e1bd42 TY |
124 | #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE + \ |
125 | CONFIG_SYS_MONITOR_LEN) | |
8415bb68 AW |
126 | #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 |
127 | #define CONFIG_SPL_BSS_START_ADDR 0x80100000 | |
128 | #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 | |
e7e720c2 SG |
129 | |
130 | #ifdef CONFIG_U_BOOT_HDR_SIZE | |
131 | /* | |
132 | * HDR would be appended at end of image and copied to DDR along | |
133 | * with U-Boot image. Here u-boot max. size is 512K. So if binary | |
134 | * size increases then increase this size in case of secure boot as | |
135 | * it uses raw u-boot image instead of fit image. | |
136 | */ | |
137 | #define CONFIG_SYS_MONITOR_LEN (0x80000 + CONFIG_U_BOOT_HDR_SIZE) | |
138 | #else | |
8415bb68 | 139 | #define CONFIG_SYS_MONITOR_LEN 0x80000 |
e7e720c2 | 140 | #endif /* ifdef CONFIG_U_BOOT_HDR_SIZE */ |
8415bb68 AW |
141 | #endif |
142 | ||
d612f0ab AW |
143 | #ifdef CONFIG_QSPI_BOOT |
144 | #define CONFIG_SYS_TEXT_BASE 0x40010000 | |
947cee11 AW |
145 | #endif |
146 | ||
147 | #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) | |
d612f0ab AW |
148 | #define CONFIG_SYS_NO_FLASH |
149 | #endif | |
150 | ||
c8a7d9da | 151 | #ifndef CONFIG_SYS_TEXT_BASE |
1c69a51c | 152 | #define CONFIG_SYS_TEXT_BASE 0x60100000 |
c8a7d9da WH |
153 | #endif |
154 | ||
155 | #define CONFIG_NR_DRAM_BANKS 1 | |
156 | #define PHYS_SDRAM 0x80000000 | |
157 | #define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024) | |
158 | ||
159 | #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL | |
160 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE | |
161 | ||
4ba4a095 RG |
162 | #define CONFIG_FSL_CAAM /* Enable CAAM */ |
163 | ||
4c59ab9c AW |
164 | #if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \ |
165 | !defined(CONFIG_QSPI_BOOT) | |
eaa859e7 ZQ |
166 | #define CONFIG_U_QE |
167 | #endif | |
168 | ||
c8a7d9da WH |
169 | /* |
170 | * IFC Definitions | |
171 | */ | |
947cee11 | 172 | #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) |
c8a7d9da WH |
173 | #define CONFIG_FSL_IFC |
174 | #define CONFIG_SYS_FLASH_BASE 0x60000000 | |
175 | #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE | |
176 | ||
177 | #define CONFIG_SYS_NOR0_CSPR_EXT (0x0) | |
178 | #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ | |
179 | CSPR_PORT_SIZE_16 | \ | |
180 | CSPR_MSEL_NOR | \ | |
181 | CSPR_V) | |
182 | #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024) | |
183 | ||
184 | /* NOR Flash Timing Params */ | |
185 | #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ | |
186 | CSOR_NOR_TRHZ_80) | |
187 | #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ | |
188 | FTIM0_NOR_TEADC(0x5) | \ | |
189 | FTIM0_NOR_TAVDS(0x0) | \ | |
190 | FTIM0_NOR_TEAHC(0x5)) | |
191 | #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ | |
192 | FTIM1_NOR_TRAD_NOR(0x1A) | \ | |
193 | FTIM1_NOR_TSEQRAD_NOR(0x13)) | |
194 | #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ | |
195 | FTIM2_NOR_TCH(0x4) | \ | |
196 | FTIM2_NOR_TWP(0x1c) | \ | |
197 | FTIM2_NOR_TWPH(0x0e)) | |
198 | #define CONFIG_SYS_NOR_FTIM3 0 | |
199 | ||
200 | #define CONFIG_FLASH_CFI_DRIVER | |
201 | #define CONFIG_SYS_FLASH_CFI | |
202 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE | |
203 | #define CONFIG_SYS_FLASH_QUIET_TEST | |
204 | #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ | |
205 | ||
206 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ | |
207 | #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ | |
208 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ | |
209 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ | |
210 | ||
211 | #define CONFIG_SYS_FLASH_EMPTY_INFO | |
212 | #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS } | |
213 | ||
214 | #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS | |
272c5265 | 215 | #define CONFIG_SYS_WRITE_SWAPPED_DATA |
d612f0ab | 216 | #endif |
c8a7d9da WH |
217 | |
218 | /* CPLD */ | |
219 | ||
220 | #define CONFIG_SYS_CPLD_BASE 0x7fb00000 | |
221 | #define CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE | |
222 | ||
223 | #define CONFIG_SYS_FPGA_CSPR_EXT (0x0) | |
224 | #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \ | |
225 | CSPR_PORT_SIZE_8 | \ | |
226 | CSPR_MSEL_GPCM | \ | |
227 | CSPR_V) | |
228 | #define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024) | |
229 | #define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ | |
230 | CSOR_NOR_NOR_MODE_AVD_NOR | \ | |
231 | CSOR_NOR_TRHZ_80) | |
232 | ||
233 | /* CPLD Timing parameters for IFC GPCM */ | |
234 | #define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xf) | \ | |
235 | FTIM0_GPCM_TEADC(0xf) | \ | |
236 | FTIM0_GPCM_TEAHC(0xf)) | |
237 | #define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ | |
238 | FTIM1_GPCM_TRAD(0x3f)) | |
239 | #define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0xf) | \ | |
240 | FTIM2_GPCM_TCH(0xf) | \ | |
241 | FTIM2_GPCM_TWP(0xff)) | |
242 | #define CONFIG_SYS_FPGA_FTIM3 0x0 | |
243 | #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT | |
244 | #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR | |
245 | #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK | |
246 | #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR | |
247 | #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 | |
248 | #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 | |
249 | #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 | |
250 | #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 | |
251 | #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_FPGA_CSPR_EXT | |
252 | #define CONFIG_SYS_CSPR1 CONFIG_SYS_FPGA_CSPR | |
253 | #define CONFIG_SYS_AMASK1 CONFIG_SYS_FPGA_AMASK | |
254 | #define CONFIG_SYS_CSOR1 CONFIG_SYS_FPGA_CSOR | |
255 | #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_FPGA_FTIM0 | |
256 | #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_FPGA_FTIM1 | |
257 | #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_FPGA_FTIM2 | |
258 | #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_FPGA_FTIM3 | |
259 | ||
260 | /* | |
261 | * Serial Port | |
262 | */ | |
55d53ab4 | 263 | #ifdef CONFIG_LPUART |
55d53ab4 AW |
264 | #define CONFIG_LPUART_32B_REG |
265 | #else | |
c8a7d9da | 266 | #define CONFIG_CONS_INDEX 1 |
c8a7d9da | 267 | #define CONFIG_SYS_NS16550_SERIAL |
f833cd62 | 268 | #ifndef CONFIG_DM_SERIAL |
c8a7d9da | 269 | #define CONFIG_SYS_NS16550_REG_SIZE 1 |
f833cd62 | 270 | #endif |
c8a7d9da | 271 | #define CONFIG_SYS_NS16550_CLK get_serial_clock() |
55d53ab4 | 272 | #endif |
c8a7d9da WH |
273 | |
274 | #define CONFIG_BAUDRATE 115200 | |
275 | ||
276 | /* | |
277 | * I2C | |
278 | */ | |
c8a7d9da WH |
279 | #define CONFIG_SYS_I2C |
280 | #define CONFIG_SYS_I2C_MXC | |
03544c66 AA |
281 | #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ |
282 | #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ | |
f8cb101e | 283 | #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ |
c8a7d9da | 284 | |
5175a288 | 285 | /* EEPROM */ |
5175a288 AW |
286 | #define CONFIG_ID_EEPROM |
287 | #define CONFIG_SYS_I2C_EEPROM_NXID | |
288 | #define CONFIG_SYS_EEPROM_BUS_NUM 1 | |
289 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x53 | |
290 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 | |
291 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 | |
292 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 | |
5175a288 | 293 | |
c8a7d9da WH |
294 | /* |
295 | * MMC | |
296 | */ | |
c8a7d9da WH |
297 | #define CONFIG_FSL_ESDHC |
298 | #define CONFIG_GENERIC_MMC | |
299 | ||
8251ed23 AW |
300 | #define CONFIG_DOS_PARTITION |
301 | ||
9dd3d3c0 | 302 | /* SPI */ |
947cee11 | 303 | #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) |
9dd3d3c0 | 304 | /* QSPI */ |
d612f0ab AW |
305 | #define QSPI0_AMBA_BASE 0x40000000 |
306 | #define FSL_QSPI_FLASH_SIZE (1 << 24) | |
307 | #define FSL_QSPI_FLASH_NUM 2 | |
308 | ||
03d1d568 | 309 | /* DSPI */ |
03d1d568 YY |
310 | #endif |
311 | ||
9dd3d3c0 HW |
312 | /* DM SPI */ |
313 | #if defined(CONFIG_FSL_DSPI) || defined(CONFIG_FSL_QSPI) | |
9dd3d3c0 HW |
314 | #define CONFIG_DM_SPI_FLASH |
315 | #endif | |
d612f0ab | 316 | |
b4ecc8c6 WH |
317 | /* |
318 | * Video | |
319 | */ | |
320 | #define CONFIG_FSL_DCU_FB | |
321 | ||
322 | #ifdef CONFIG_FSL_DCU_FB | |
b4ecc8c6 | 323 | #define CONFIG_CMD_BMP |
b4ecc8c6 WH |
324 | #define CONFIG_VIDEO_LOGO |
325 | #define CONFIG_VIDEO_BMP_LOGO | |
326 | ||
327 | #define CONFIG_FSL_DCU_SII9022A | |
328 | #define CONFIG_SYS_I2C_DVI_BUS_NUM 1 | |
329 | #define CONFIG_SYS_I2C_DVI_ADDR 0x39 | |
330 | #endif | |
331 | ||
c8a7d9da WH |
332 | /* |
333 | * eTSEC | |
334 | */ | |
335 | #define CONFIG_TSEC_ENET | |
336 | ||
337 | #ifdef CONFIG_TSEC_ENET | |
338 | #define CONFIG_MII | |
339 | #define CONFIG_MII_DEFAULT_TSEC 1 | |
340 | #define CONFIG_TSEC1 1 | |
341 | #define CONFIG_TSEC1_NAME "eTSEC1" | |
342 | #define CONFIG_TSEC2 1 | |
343 | #define CONFIG_TSEC2_NAME "eTSEC2" | |
344 | #define CONFIG_TSEC3 1 | |
345 | #define CONFIG_TSEC3_NAME "eTSEC3" | |
346 | ||
347 | #define TSEC1_PHY_ADDR 2 | |
348 | #define TSEC2_PHY_ADDR 0 | |
349 | #define TSEC3_PHY_ADDR 1 | |
350 | ||
351 | #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
352 | #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
353 | #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
354 | ||
355 | #define TSEC1_PHYIDX 0 | |
356 | #define TSEC2_PHYIDX 0 | |
357 | #define TSEC3_PHYIDX 0 | |
358 | ||
359 | #define CONFIG_ETHPRIME "eTSEC1" | |
360 | ||
361 | #define CONFIG_PHY_GIGE | |
362 | #define CONFIG_PHYLIB | |
363 | #define CONFIG_PHY_ATHEROS | |
364 | ||
365 | #define CONFIG_HAS_ETH0 | |
366 | #define CONFIG_HAS_ETH1 | |
367 | #define CONFIG_HAS_ETH2 | |
368 | #endif | |
369 | ||
da419027 | 370 | /* PCIe */ |
b38eaec5 RD |
371 | #define CONFIG_PCIE1 /* PCIE controller 1 */ |
372 | #define CONFIG_PCIE2 /* PCIE controller 2 */ | |
da419027 | 373 | |
180b8688 | 374 | #ifdef CONFIG_PCI |
180b8688 ML |
375 | #define CONFIG_PCI_SCAN_SHOW |
376 | #define CONFIG_CMD_PCI | |
180b8688 ML |
377 | #endif |
378 | ||
c8a7d9da WH |
379 | #define CONFIG_CMDLINE_TAG |
380 | #define CONFIG_CMDLINE_EDITING | |
8415bb68 | 381 | |
1a2826f6 | 382 | #define CONFIG_PEN_ADDR_BIG_ENDIAN |
435acd83 | 383 | #define CONFIG_LAYERSCAPE_NS_ACCESS |
1a2826f6 XL |
384 | #define CONFIG_SMP_PEN_ADDR 0x01ee0200 |
385 | #define CONFIG_TIMER_CLK_FREQ 12500000 | |
1a2826f6 | 386 | |
c8a7d9da | 387 | #define CONFIG_HWCONFIG |
03c22449 ZZ |
388 | #define HWCONFIG_BUFFER_SIZE 256 |
389 | ||
390 | #define CONFIG_FSL_DEVICE_DISABLE | |
c8a7d9da | 391 | |
c8a7d9da | 392 | |
55d53ab4 AW |
393 | #ifdef CONFIG_LPUART |
394 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
395 | "bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0" \ | |
7ff7166c AW |
396 | "initrd_high=0xffffffff\0" \ |
397 | "fdt_high=0xffffffff\0" | |
55d53ab4 | 398 | #else |
c8a7d9da WH |
399 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
400 | "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \ | |
7ff7166c AW |
401 | "initrd_high=0xffffffff\0" \ |
402 | "fdt_high=0xffffffff\0" | |
55d53ab4 | 403 | #endif |
c8a7d9da WH |
404 | |
405 | /* | |
406 | * Miscellaneous configurable options | |
407 | */ | |
408 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ | |
c8a7d9da WH |
409 | #define CONFIG_AUTO_COMPLETE |
410 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ | |
411 | #define CONFIG_SYS_PBSIZE \ | |
412 | (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) | |
413 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
414 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE | |
415 | ||
c8a7d9da WH |
416 | #define CONFIG_SYS_MEMTEST_START 0x80000000 |
417 | #define CONFIG_SYS_MEMTEST_END 0x9fffffff | |
418 | ||
419 | #define CONFIG_SYS_LOAD_ADDR 0x82000000 | |
c8a7d9da | 420 | |
660673af XL |
421 | #define CONFIG_LS102XA_STREAM_ID |
422 | ||
c8a7d9da WH |
423 | /* |
424 | * Stack sizes | |
425 | * The stack sizes are set up in start.S using the settings below | |
426 | */ | |
427 | #define CONFIG_STACKSIZE (30 * 1024) | |
428 | ||
429 | #define CONFIG_SYS_INIT_SP_OFFSET \ | |
430 | (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) | |
431 | #define CONFIG_SYS_INIT_SP_ADDR \ | |
432 | (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) | |
433 | ||
8415bb68 AW |
434 | #ifdef CONFIG_SPL_BUILD |
435 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE | |
436 | #else | |
c8a7d9da | 437 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ |
8415bb68 | 438 | #endif |
c8a7d9da | 439 | |
713bf94f | 440 | #define CONFIG_SYS_QE_FW_ADDR 0x600c0000 |
eaa859e7 | 441 | |
c8a7d9da WH |
442 | /* |
443 | * Environment | |
444 | */ | |
445 | #define CONFIG_ENV_OVERWRITE | |
446 | ||
8415bb68 AW |
447 | #if defined(CONFIG_SD_BOOT) |
448 | #define CONFIG_ENV_OFFSET 0x100000 | |
449 | #define CONFIG_ENV_IS_IN_MMC | |
450 | #define CONFIG_SYS_MMC_ENV_DEV 0 | |
451 | #define CONFIG_ENV_SIZE 0x20000 | |
d612f0ab AW |
452 | #elif defined(CONFIG_QSPI_BOOT) |
453 | #define CONFIG_ENV_IS_IN_SPI_FLASH | |
454 | #define CONFIG_ENV_SIZE 0x2000 | |
455 | #define CONFIG_ENV_OFFSET 0x100000 | |
456 | #define CONFIG_ENV_SECT_SIZE 0x10000 | |
8415bb68 | 457 | #else |
c8a7d9da WH |
458 | #define CONFIG_ENV_IS_IN_FLASH |
459 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) | |
460 | #define CONFIG_ENV_SIZE 0x20000 | |
461 | #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ | |
8415bb68 | 462 | #endif |
c8a7d9da | 463 | |
4ba4a095 RG |
464 | #define CONFIG_MISC_INIT_R |
465 | ||
466 | /* Hash command with SHA acceleration supported in hardware */ | |
ef6c55a2 | 467 | #ifdef CONFIG_FSL_CAAM |
4ba4a095 RG |
468 | #define CONFIG_CMD_HASH |
469 | #define CONFIG_SHA_HW_ACCEL | |
ef6c55a2 AB |
470 | #endif |
471 | ||
472 | #include <asm/fsl_secure_boot.h> | |
cc7b8b9a | 473 | #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ |
4ba4a095 | 474 | |
c8a7d9da | 475 | #endif |