[people/ms/u-boot.git] / include / configs / ls1021atwr.h

/*
 * Copyright 2014 Freescale Semiconductor, Inc.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __CONFIG_H
#define __CONFIG_H

#define CONFIG_ARMV7_PSCI_1_0

#define CONFIG_ARMV7_SECURE_BASE	OCRAM_BASE_S_ADDR

#define CONFIG_SYS_FSL_CLK

#define CONFIG_SKIP_LOWLEVEL_INIT
#define CONFIG_DEEP_SLEEP

/*
 * Size of malloc() pool
 */
#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 16 * 1024 * 1024)

#define CONFIG_SYS_INIT_RAM_ADDR	OCRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE	OCRAM_SIZE

/*
 * USB
 */

/*
 * EHCI Support - disbaled by default as
 * there is no signal coming out of soc on
 * this board for this controller. However,
 * the silicon still has this controller,
 * and anyone can use this controller by
 * taking signals out on their board.
 */

/*#define CONFIG_HAS_FSL_DR_USB*/

#ifdef CONFIG_HAS_FSL_DR_USB
#define CONFIG_USB_EHCI_FSL
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
#endif

/* XHCI Support - enabled by default */
#define CONFIG_USB_MAX_CONTROLLER_COUNT        1

#define CONFIG_SYS_CLK_FREQ		100000000
#define CONFIG_DDR_CLK_FREQ		100000000

#define DDR_SDRAM_CFG			0x470c0008
#define DDR_CS0_BNDS			0x008000bf
#define DDR_CS0_CONFIG			0x80014302
#define DDR_TIMING_CFG_0		0x50550004
#define DDR_TIMING_CFG_1		0xbcb38c56
#define DDR_TIMING_CFG_2		0x0040d120
#define DDR_TIMING_CFG_3		0x010e1000
#define DDR_TIMING_CFG_4		0x00000001
#define DDR_TIMING_CFG_5		0x03401400
#define DDR_SDRAM_CFG_2			0x00401010
#define DDR_SDRAM_MODE			0x00061c60
#define DDR_SDRAM_MODE_2		0x00180000
#define DDR_SDRAM_INTERVAL		0x18600618
#define DDR_DDR_WRLVL_CNTL		0x8655f605
#define DDR_DDR_WRLVL_CNTL_2		0x05060607
#define DDR_DDR_WRLVL_CNTL_3		0x05050505
#define DDR_DDR_CDR1			0x80040000
#define DDR_DDR_CDR2			0x00000001
#define DDR_SDRAM_CLK_CNTL		0x02000000
#define DDR_DDR_ZQ_CNTL			0x89080600
#define DDR_CS0_CONFIG_2		0
#define DDR_SDRAM_CFG_MEM_EN		0x80000000
#define SDRAM_CFG2_D_INIT		0x00000010
#define DDR_CDR2_VREF_TRAIN_EN		0x00000080
#define SDRAM_CFG2_FRC_SR		0x80000000
#define SDRAM_CFG_BI			0x00000001

#ifdef CONFIG_RAMBOOT_PBL
#define CONFIG_SYS_FSL_PBL_PBI	board/freescale/ls1021atwr/ls102xa_pbi.cfg
#endif

#ifdef CONFIG_SD_BOOT
#ifdef CONFIG_SD_BOOT_QSPI
#define CONFIG_SYS_FSL_PBL_RCW	\
	board/freescale/ls1021atwr/ls102xa_rcw_sd_qspi.cfg
#else
#define CONFIG_SYS_FSL_PBL_RCW	\
	board/freescale/ls1021atwr/ls102xa_rcw_sd_ifc.cfg
#endif
#define CONFIG_SPL_FRAMEWORK

#ifdef CONFIG_SECURE_BOOT
/*
 * HDR would be appended at end of image and copied to DDR along
 * with U-Boot image.
 */
#define CONFIG_U_BOOT_HDR_SIZE				(16 << 10)
#endif /* ifdef CONFIG_SECURE_BOOT */

#define CONFIG_SPL_TEXT_BASE		0x10000000
#define CONFIG_SPL_MAX_SIZE		0x1a000
#define CONFIG_SPL_STACK		0x1001d000
#define CONFIG_SPL_PAD_TO		0x1c000
#define CONFIG_SYS_TEXT_BASE		0x82000000

#define CONFIG_SYS_SPL_MALLOC_START	(CONFIG_SYS_TEXT_BASE + \
		CONFIG_SYS_MONITOR_LEN)
#define CONFIG_SYS_SPL_MALLOC_SIZE	0x100000
#define CONFIG_SPL_BSS_START_ADDR	0x80100000
#define CONFIG_SPL_BSS_MAX_SIZE		0x80000

#ifdef CONFIG_U_BOOT_HDR_SIZE
/*
 * HDR would be appended at end of image and copied to DDR along
 * with U-Boot image. Here u-boot max. size is 512K. So if binary
 * size increases then increase this size in case of secure boot as
 * it uses raw u-boot image instead of fit image.
 */
#define CONFIG_SYS_MONITOR_LEN		(0x100000 + CONFIG_U_BOOT_HDR_SIZE)
#else
#define CONFIG_SYS_MONITOR_LEN		0x100000
#endif /* ifdef CONFIG_U_BOOT_HDR_SIZE */
#endif

#ifdef CONFIG_QSPI_BOOT
#define CONFIG_SYS_TEXT_BASE		0x40100000
#endif

#ifndef CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_TEXT_BASE		0x60100000
#endif

#define CONFIG_NR_DRAM_BANKS		1
#define PHYS_SDRAM			0x80000000
#define PHYS_SDRAM_SIZE			(1u * 1024 * 1024 * 1024)

#define CONFIG_SYS_DDR_SDRAM_BASE      0x80000000UL
#define CONFIG_SYS_SDRAM_BASE          CONFIG_SYS_DDR_SDRAM_BASE

#if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \
	!defined(CONFIG_QSPI_BOOT)
#define CONFIG_U_QE
#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
#endif

/*
 * IFC Definitions
 */
#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
#define CONFIG_FSL_IFC
#define CONFIG_SYS_FLASH_BASE		0x60000000
#define CONFIG_SYS_FLASH_BASE_PHYS	CONFIG_SYS_FLASH_BASE

#define CONFIG_SYS_NOR0_CSPR_EXT	(0x0)
#define CONFIG_SYS_NOR0_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
				CSPR_PORT_SIZE_16 | \
				CSPR_MSEL_NOR | \
				CSPR_V)
#define CONFIG_SYS_NOR_AMASK		IFC_AMASK(128 * 1024 * 1024)

/* NOR Flash Timing Params */
#define CONFIG_SYS_NOR_CSOR		(CSOR_NOR_ADM_SHIFT(4) | \
					CSOR_NOR_TRHZ_80)
#define CONFIG_SYS_NOR_FTIM0		(FTIM0_NOR_TACSE(0x4) | \
					FTIM0_NOR_TEADC(0x5) | \
					FTIM0_NOR_TAVDS(0x0) | \
					FTIM0_NOR_TEAHC(0x5))
#define CONFIG_SYS_NOR_FTIM1		(FTIM1_NOR_TACO(0x35) | \
					FTIM1_NOR_TRAD_NOR(0x1A) | \
					FTIM1_NOR_TSEQRAD_NOR(0x13))
#define CONFIG_SYS_NOR_FTIM2		(FTIM2_NOR_TCS(0x4) | \
					FTIM2_NOR_TCH(0x4) | \
					FTIM2_NOR_TWP(0x1c) | \
					FTIM2_NOR_TWPH(0x0e))
#define CONFIG_SYS_NOR_FTIM3		0

#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
#define CONFIG_SYS_FLASH_QUIET_TEST
#define CONFIG_FLASH_SHOW_PROGRESS	45	/* count down from 45/5: 9..1 */

#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* number of banks */
#define CONFIG_SYS_MAX_FLASH_SECT	1024	/* sectors per device */
#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */

#define CONFIG_SYS_FLASH_EMPTY_INFO
#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE_PHYS }

#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
#define CONFIG_SYS_WRITE_SWAPPED_DATA
#endif

/* CPLD */

#define CONFIG_SYS_CPLD_BASE	0x7fb00000
#define CPLD_BASE_PHYS		CONFIG_SYS_CPLD_BASE

#define CONFIG_SYS_FPGA_CSPR_EXT        (0x0)
#define CONFIG_SYS_FPGA_CSPR		(CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \
					CSPR_PORT_SIZE_8 | \
					CSPR_MSEL_GPCM | \
					CSPR_V)
#define CONFIG_SYS_FPGA_AMASK		IFC_AMASK(64 * 1024)
#define CONFIG_SYS_FPGA_CSOR		(CSOR_NOR_ADM_SHIFT(4) | \
					CSOR_NOR_NOR_MODE_AVD_NOR | \
					CSOR_NOR_TRHZ_80)

/* CPLD Timing parameters for IFC GPCM */
#define CONFIG_SYS_FPGA_FTIM0		(FTIM0_GPCM_TACSE(0xf) | \
					FTIM0_GPCM_TEADC(0xf) | \
					FTIM0_GPCM_TEAHC(0xf))
#define CONFIG_SYS_FPGA_FTIM1		(FTIM1_GPCM_TACO(0xff) | \
					FTIM1_GPCM_TRAD(0x3f))
#define CONFIG_SYS_FPGA_FTIM2		(FTIM2_GPCM_TCS(0xf) | \
					FTIM2_GPCM_TCH(0xf) | \
					FTIM2_GPCM_TWP(0xff))
#define CONFIG_SYS_FPGA_FTIM3           0x0
#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NOR0_CSPR_EXT
#define CONFIG_SYS_CSPR0		CONFIG_SYS_NOR0_CSPR
#define CONFIG_SYS_AMASK0		CONFIG_SYS_NOR_AMASK
#define CONFIG_SYS_CSOR0		CONFIG_SYS_NOR_CSOR
#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NOR_FTIM0
#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NOR_FTIM1
#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NOR_FTIM2
#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NOR_FTIM3
#define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_FPGA_CSPR_EXT
#define CONFIG_SYS_CSPR1		CONFIG_SYS_FPGA_CSPR
#define CONFIG_SYS_AMASK1		CONFIG_SYS_FPGA_AMASK
#define CONFIG_SYS_CSOR1		CONFIG_SYS_FPGA_CSOR
#define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_FPGA_FTIM0
#define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_FPGA_FTIM1
#define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_FPGA_FTIM2
#define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_FPGA_FTIM3

/*
 * Serial Port
 */
#ifdef CONFIG_LPUART
#define CONFIG_LPUART_32B_REG
#else
#define CONFIG_CONS_INDEX		1
#define CONFIG_SYS_NS16550_SERIAL
#ifndef CONFIG_DM_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	1
#endif
#define CONFIG_SYS_NS16550_CLK		get_serial_clock()
#endif

/*
 * I2C
 */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_MXC
#define CONFIG_SYS_I2C_MXC_I2C1		/* enable I2C bus 1 */
#define CONFIG_SYS_I2C_MXC_I2C2		/* enable I2C bus 2 */
#define CONFIG_SYS_I2C_MXC_I2C3		/* enable I2C bus 3 */

/* EEPROM */
#define CONFIG_ID_EEPROM
#define CONFIG_SYS_I2C_EEPROM_NXID
#define CONFIG_SYS_EEPROM_BUS_NUM		1
#define CONFIG_SYS_I2C_EEPROM_ADDR		0x53
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	3
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	5

/*
 * MMC
 */
#define CONFIG_FSL_ESDHC

/* SPI */
#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
/* QSPI */
#define QSPI0_AMBA_BASE			0x40000000
#define FSL_QSPI_FLASH_SIZE		(1 << 24)
#define FSL_QSPI_FLASH_NUM		2

/* DSPI */
#endif

/* DM SPI */
#if defined(CONFIG_FSL_DSPI) || defined(CONFIG_FSL_QSPI)
#define CONFIG_DM_SPI_FLASH
#endif

/*
 * Video
 */
#ifdef CONFIG_VIDEO_FSL_DCU_FB
#define CONFIG_VIDEO_LOGO
#define CONFIG_VIDEO_BMP_LOGO

#define CONFIG_FSL_DCU_SII9022A
#define CONFIG_SYS_I2C_DVI_BUS_NUM	1
#define CONFIG_SYS_I2C_DVI_ADDR		0x39
#endif

/*
 * eTSEC
 */
#define CONFIG_TSEC_ENET

#ifdef CONFIG_TSEC_ENET
#define CONFIG_MII
#define CONFIG_MII_DEFAULT_TSEC		1
#define CONFIG_TSEC1			1
#define CONFIG_TSEC1_NAME		"eTSEC1"
#define CONFIG_TSEC2			1
#define CONFIG_TSEC2_NAME		"eTSEC2"
#define CONFIG_TSEC3			1
#define CONFIG_TSEC3_NAME		"eTSEC3"

#define TSEC1_PHY_ADDR			2
#define TSEC2_PHY_ADDR			0
#define TSEC3_PHY_ADDR			1

#define TSEC1_FLAGS			(TSEC_GIGABIT | TSEC_REDUCED)
#define TSEC2_FLAGS			(TSEC_GIGABIT | TSEC_REDUCED)
#define TSEC3_FLAGS			(TSEC_GIGABIT | TSEC_REDUCED)

#define TSEC1_PHYIDX			0
#define TSEC2_PHYIDX			0
#define TSEC3_PHYIDX			0

#define CONFIG_ETHPRIME			"eTSEC1"

#define CONFIG_PHY_ATHEROS

#define CONFIG_HAS_ETH0
#define CONFIG_HAS_ETH1
#define CONFIG_HAS_ETH2
#endif

/* PCIe */
#define CONFIG_PCIE1		/* PCIE controller 1 */
#define CONFIG_PCIE2		/* PCIE controller 2 */

#ifdef CONFIG_PCI
#define CONFIG_PCI_SCAN_SHOW
#endif

#define CONFIG_CMDLINE_TAG

#define CONFIG_PEN_ADDR_BIG_ENDIAN
#define CONFIG_LAYERSCAPE_NS_ACCESS
#define CONFIG_SMP_PEN_ADDR		0x01ee0200
#define COUNTER_FREQUENCY		12500000

#define CONFIG_HWCONFIG
#define HWCONFIG_BUFFER_SIZE		256

#define CONFIG_FSL_DEVICE_DISABLE

#include <config_distro_defaults.h>
#define BOOT_TARGET_DEVICES(func) \
	func(MMC, mmc, 0) \
	func(USB, usb, 0)
#include <config_distro_bootcmd.h>

#ifdef CONFIG_LPUART
#define CONFIG_EXTRA_ENV_SETTINGS       \
	"bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0" \
	"initrd_high=0xffffffff\0"      \
	"fdt_high=0xffffffff\0"		\
	"fdt_addr=0x64f00000\0"		\
	"kernel_addr=0x65000000\0"	\
	"scriptaddr=0x80000000\0"	\
	"scripthdraddr=0x80080000\0"	\
	"fdtheader_addr_r=0x80100000\0"	\
	"kernelheader_addr_r=0x80200000\0"	\
	"kernel_addr_r=0x81000000\0"	\
	"fdt_addr_r=0x90000000\0"	\
	"ramdisk_addr_r=0xa0000000\0"	\
	"load_addr=0xa0000000\0"	\
	"kernel_size=0x2800000\0"	\
	BOOTENV				\
	"boot_scripts=ls1021atwr_boot.scr\0"	\
	"boot_script_hdr=hdr_ls1021atwr_bs.out\0"	\
		"scan_dev_for_boot_part="	\
			"part list ${devtype} ${devnum} devplist; "	\
			"env exists devplist || setenv devplist 1; "	\
			"for distro_bootpart in ${devplist}; do "	\
			"if fstype ${devtype} "				\
				"${devnum}:${distro_bootpart} "		\
				"bootfstype; then "			\
				"run scan_dev_for_boot; "		\
			"fi; "			\
		"done\0"			\
	"scan_dev_for_boot="				  \
		"echo Scanning ${devtype} "		  \
				"${devnum}:${distro_bootpart}...; "  \
		"for prefix in ${boot_prefixes}; do "	  \
			"run scan_dev_for_scripts; "	  \
		"done;"					  \
		"\0"					  \
	"boot_a_script="				  \
		"load ${devtype} ${devnum}:${distro_bootpart} "  \
			"${scriptaddr} ${prefix}${script}; "    \
		"env exists secureboot && load ${devtype} "     \
			"${devnum}:${distro_bootpart} "		\
			"${scripthdraddr} ${prefix}${boot_script_hdr} " \
			"&& esbc_validate ${scripthdraddr};"    \
		"source ${scriptaddr}\0"	  \
	"installer=load mmc 0:2 $load_addr "	\
		"/flex_installer_arm32.itb; "		\
		"bootm $load_addr#ls1021atwr\0"	\
	"qspi_bootcmd=echo Trying load from qspi..;"	\
		"sf probe && sf read $load_addr "	\
		"$kernel_addr $kernel_size && bootm $load_addr#$board\0"	\
	"nor_bootcmd=echo Trying load from nor..;"	\
		"cp.b $kernel_addr $load_addr "		\
		"$kernel_size && bootm $load_addr#$board\0"
#else
#define CONFIG_EXTRA_ENV_SETTINGS	\
	"bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \
	"initrd_high=0xffffffff\0"      \
	"fdt_high=0xffffffff\0"		\
	"fdt_addr=0x64f00000\0"		\
	"kernel_addr=0x65000000\0"	\
	"scriptaddr=0x80000000\0"	\
	"scripthdraddr=0x80080000\0"	\
	"fdtheader_addr_r=0x80100000\0"	\
	"kernelheader_addr_r=0x80200000\0"	\
	"kernel_addr_r=0x81000000\0"	\
	"fdt_addr_r=0x90000000\0"	\
	"ramdisk_addr_r=0xa0000000\0"	\
	"load_addr=0xa0000000\0"	\
	"kernel_size=0x2800000\0"	\
	BOOTENV				\
	"boot_scripts=ls1021atwr_boot.scr\0"	\
	"boot_script_hdr=hdr_ls1021atwr_bs.out\0"	\
		"scan_dev_for_boot_part="	\
			"part list ${devtype} ${devnum} devplist; "	\
			"env exists devplist || setenv devplist 1; "	\
			"for distro_bootpart in ${devplist}; do "	\
			"if fstype ${devtype} "				\
				"${devnum}:${distro_bootpart} "		\
				"bootfstype; then "			\
				"run scan_dev_for_boot; "		\
			"fi; "			\
		"done\0"			\
	"scan_dev_for_boot="				  \
		"echo Scanning ${devtype} "		  \
				"${devnum}:${distro_bootpart}...; "  \
		"for prefix in ${boot_prefixes}; do "	  \
			"run scan_dev_for_scripts; "	  \
		"done;"					  \
		"\0"					  \
	"boot_a_script="				  \
		"load ${devtype} ${devnum}:${distro_bootpart} "  \
			"${scriptaddr} ${prefix}${script}; "    \
		"env exists secureboot && load ${devtype} "     \
			"${devnum}:${distro_bootpart} "		\
			"${scripthdraddr} ${prefix}${boot_script_hdr} " \
			"&& esbc_validate ${scripthdraddr};"    \
		"source ${scriptaddr}\0"	  \
	"installer=load mmc 0:2 $load_addr "	\
		"/flex_installer_arm32.itb; "		\
		"bootm $load_addr#ls1021atwr\0"	\
	"qspi_bootcmd=echo Trying load from qspi..;"	\
		"sf probe && sf read $load_addr "	\
		"$kernel_addr $kernel_size && bootm $load_addr#$board\0"	\
	"nor_bootcmd=echo Trying load from nor..;"	\
		"cp.b $kernel_addr $load_addr "		\
		"$kernel_size && bootm $load_addr#$board\0"
#endif

#undef CONFIG_BOOTCOMMAND
#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
#define CONFIG_BOOTCOMMAND "run distro_bootcmd; env exists secureboot"	\
			   "&& esbc_halt; run qspi_bootcmd;"
#else
#define CONFIG_BOOTCOMMAND "run distro_bootcmd; env exists secureboot"	\
			   "&& esbc_halt; run nor_bootcmd;"
#endif

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP		/* undef to save memory */
#define CONFIG_AUTO_COMPLETE

#define CONFIG_SYS_MEMTEST_START	0x80000000
#define CONFIG_SYS_MEMTEST_END		0x9fffffff

#define CONFIG_SYS_LOAD_ADDR		0x82000000

#define CONFIG_LS102XA_STREAM_ID

#define CONFIG_SYS_INIT_SP_OFFSET \
	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_ADDR \
	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)

#ifdef CONFIG_SPL_BUILD
#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
#else
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
#endif

#define CONFIG_SYS_QE_FW_ADDR     0x60940000

/*
 * Environment
 */
#define CONFIG_ENV_OVERWRITE

#if defined(CONFIG_SD_BOOT)
#define CONFIG_ENV_OFFSET		0x300000
#define CONFIG_SYS_MMC_ENV_DEV		0
#define CONFIG_ENV_SIZE			0x20000
#elif defined(CONFIG_QSPI_BOOT)
#define CONFIG_ENV_SIZE			0x2000
#define CONFIG_ENV_OFFSET		0x300000
#define CONFIG_ENV_SECT_SIZE		0x10000
#else
#define CONFIG_ENV_ADDR			(CONFIG_SYS_FLASH_BASE + 0x300000)
#define CONFIG_ENV_SIZE			0x20000
#define CONFIG_ENV_SECT_SIZE		0x20000 /* 128K (one sector) */
#endif

#define CONFIG_MISC_INIT_R

#include <asm/fsl_secure_boot.h>
#define CONFIG_SYS_BOOTM_LEN	(64 << 20) /* Increase max gunzip size */

#endif
Commit	Line	Data
c8a7d9da WH	1	/*
	2	* Copyright 2014 Freescale Semiconductor, Inc.
	3	*
	4	* SPDX-License-Identifier: GPL-2.0+
	5	*/
	6
	7	#ifndef __CONFIG_H
	8	#define __CONFIG_H
	9
aeb901f2	10	#define CONFIG_ARMV7_PSCI_1_0
340848b1	11
3288628a HZ	12	#define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR
3288628a HZ	13
18fb0e3c	14	#define CONFIG_SYS_FSL_CLK
c8a7d9da	15
c8a7d9da	16	#define CONFIG_SKIP_LOWLEVEL_INIT
99e1bd42	17	#define CONFIG_DEEP_SLEEP
c8a7d9da WH	18
	19	/*
	20	* Size of malloc() pool
	21	*/
	22	#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024 * 1024)
	23
	24	#define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR
	25	#define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE
	26
10a28644 RM	27	/*
	28	* USB
	29	*/
	30
	31	/*
	32	* EHCI Support - disbaled by default as
	33	* there is no signal coming out of soc on
	34	* this board for this controller. However,
	35	* the silicon still has this controller,
	36	* and anyone can use this controller by
	37	* taking signals out on their board.
	38	*/
	39
	40	/#define CONFIG_HAS_FSL_DR_USB/
	41
	42	#ifdef CONFIG_HAS_FSL_DR_USB
10a28644 RM	43	#define CONFIG_USB_EHCI_FSL
	44	#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
	45	#endif
	46
	47	/* XHCI Support - enabled by default */
10a28644	48	#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
10a28644	49
c8a7d9da WH	50	#define CONFIG_SYS_CLK_FREQ 100000000
	51	#define CONFIG_DDR_CLK_FREQ 100000000
	52
a88cc3bd YS	53	#define DDR_SDRAM_CFG 0x470c0008
	54	#define DDR_CS0_BNDS 0x008000bf
	55	#define DDR_CS0_CONFIG 0x80014302
	56	#define DDR_TIMING_CFG_0 0x50550004
	57	#define DDR_TIMING_CFG_1 0xbcb38c56
	58	#define DDR_TIMING_CFG_2 0x0040d120
	59	#define DDR_TIMING_CFG_3 0x010e1000
	60	#define DDR_TIMING_CFG_4 0x00000001
	61	#define DDR_TIMING_CFG_5 0x03401400
	62	#define DDR_SDRAM_CFG_2 0x00401010
	63	#define DDR_SDRAM_MODE 0x00061c60
	64	#define DDR_SDRAM_MODE_2 0x00180000
	65	#define DDR_SDRAM_INTERVAL 0x18600618
	66	#define DDR_DDR_WRLVL_CNTL 0x8655f605
	67	#define DDR_DDR_WRLVL_CNTL_2 0x05060607
	68	#define DDR_DDR_WRLVL_CNTL_3 0x05050505
	69	#define DDR_DDR_CDR1 0x80040000
	70	#define DDR_DDR_CDR2 0x00000001
	71	#define DDR_SDRAM_CLK_CNTL 0x02000000
	72	#define DDR_DDR_ZQ_CNTL 0x89080600
	73	#define DDR_CS0_CONFIG_2 0
	74	#define DDR_SDRAM_CFG_MEM_EN 0x80000000
99e1bd42 TY	75	#define SDRAM_CFG2_D_INIT 0x00000010
	76	#define DDR_CDR2_VREF_TRAIN_EN 0x00000080
	77	#define SDRAM_CFG2_FRC_SR 0x80000000
	78	#define SDRAM_CFG_BI 0x00000001
a88cc3bd	79
8415bb68 AW	80	#ifdef CONFIG_RAMBOOT_PBL
	81	#define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1021atwr/ls102xa_pbi.cfg
	82	#endif
	83
	84	#ifdef CONFIG_SD_BOOT
947cee11 AW	85	#ifdef CONFIG_SD_BOOT_QSPI
	86	#define CONFIG_SYS_FSL_PBL_RCW \
	87	board/freescale/ls1021atwr/ls102xa_rcw_sd_qspi.cfg
	88	#else
	89	#define CONFIG_SYS_FSL_PBL_RCW \
	90	board/freescale/ls1021atwr/ls102xa_rcw_sd_ifc.cfg
	91	#endif
8415bb68	92	#define CONFIG_SPL_FRAMEWORK
e7e720c2 SG	93
e7e720c2 SG	94	#ifdef CONFIG_SECURE_BOOT
e7e720c2 SG	95	/*
	96	* HDR would be appended at end of image and copied to DDR along
	97	* with U-Boot image.
	98	*/
693d4c9f	99	#define CONFIG_U_BOOT_HDR_SIZE (16 << 10)
e7e720c2	100	#endif /* ifdef CONFIG_SECURE_BOOT */
8415bb68 AW	101
	102	#define CONFIG_SPL_TEXT_BASE 0x10000000
	103	#define CONFIG_SPL_MAX_SIZE 0x1a000
	104	#define CONFIG_SPL_STACK 0x1001d000
	105	#define CONFIG_SPL_PAD_TO 0x1c000
	106	#define CONFIG_SYS_TEXT_BASE 0x82000000
	107
99e1bd42 TY	108	#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE + \
99e1bd42 TY	109	CONFIG_SYS_MONITOR_LEN)
8415bb68 AW	110	#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
	111	#define CONFIG_SPL_BSS_START_ADDR 0x80100000
	112	#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
e7e720c2 SG	113
	114	#ifdef CONFIG_U_BOOT_HDR_SIZE
	115	/*
	116	* HDR would be appended at end of image and copied to DDR along
	117	* with U-Boot image. Here u-boot max. size is 512K. So if binary
	118	* size increases then increase this size in case of secure boot as
	119	* it uses raw u-boot image instead of fit image.
	120	*/
9b6639fa	121	#define CONFIG_SYS_MONITOR_LEN (0x100000 + CONFIG_U_BOOT_HDR_SIZE)
e7e720c2	122	#else
9b6639fa	123	#define CONFIG_SYS_MONITOR_LEN 0x100000
e7e720c2	124	#endif /* ifdef CONFIG_U_BOOT_HDR_SIZE */
8415bb68 AW	125	#endif
8415bb68 AW	126
d612f0ab	127	#ifdef CONFIG_QSPI_BOOT
615bfce5	128	#define CONFIG_SYS_TEXT_BASE 0x40100000
947cee11 AW	129	#endif
947cee11 AW	130
c8a7d9da	131	#ifndef CONFIG_SYS_TEXT_BASE
1c69a51c	132	#define CONFIG_SYS_TEXT_BASE 0x60100000
c8a7d9da WH	133	#endif
	134
	135	#define CONFIG_NR_DRAM_BANKS 1
	136	#define PHYS_SDRAM 0x80000000
	137	#define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024)
	138
	139	#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
	140	#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
	141
4c59ab9c AW	142	#if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \
4c59ab9c AW	143	!defined(CONFIG_QSPI_BOOT)
eaa859e7	144	#define CONFIG_U_QE
5aa03ddd	145	#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
eaa859e7 ZQ	146	#endif
eaa859e7 ZQ	147
c8a7d9da WH	148	/*
	149	* IFC Definitions
	150	*/
947cee11	151	#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
c8a7d9da WH	152	#define CONFIG_FSL_IFC
	153	#define CONFIG_SYS_FLASH_BASE 0x60000000
	154	#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
	155
	156	#define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
	157	#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \| \
	158	CSPR_PORT_SIZE_16 \| \
	159	CSPR_MSEL_NOR \| \
	160	CSPR_V)
	161	#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024)
	162
	163	/* NOR Flash Timing Params */
	164	#define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) \| \
	165	CSOR_NOR_TRHZ_80)
	166	#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) \| \
	167	FTIM0_NOR_TEADC(0x5) \| \
	168	FTIM0_NOR_TAVDS(0x0) \| \
	169	FTIM0_NOR_TEAHC(0x5))
	170	#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) \| \
	171	FTIM1_NOR_TRAD_NOR(0x1A) \| \
	172	FTIM1_NOR_TSEQRAD_NOR(0x13))
	173	#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) \| \
	174	FTIM2_NOR_TCH(0x4) \| \
	175	FTIM2_NOR_TWP(0x1c) \| \
	176	FTIM2_NOR_TWPH(0x0e))
	177	#define CONFIG_SYS_NOR_FTIM3 0
	178
	179	#define CONFIG_FLASH_CFI_DRIVER
	180	#define CONFIG_SYS_FLASH_CFI
	181	#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
	182	#define CONFIG_SYS_FLASH_QUIET_TEST
	183	#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
	184
	185	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
	186	#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
	187	#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
	188	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
	189
	190	#define CONFIG_SYS_FLASH_EMPTY_INFO
	191	#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS }
	192
	193	#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
272c5265	194	#define CONFIG_SYS_WRITE_SWAPPED_DATA
d612f0ab	195	#endif
c8a7d9da WH	196
	197	/* CPLD */
	198
	199	#define CONFIG_SYS_CPLD_BASE 0x7fb00000
	200	#define CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE
	201
	202	#define CONFIG_SYS_FPGA_CSPR_EXT (0x0)
	203	#define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) \| \
	204	CSPR_PORT_SIZE_8 \| \
	205	CSPR_MSEL_GPCM \| \
	206	CSPR_V)
	207	#define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024)
	208	#define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) \| \
	209	CSOR_NOR_NOR_MODE_AVD_NOR \| \
	210	CSOR_NOR_TRHZ_80)
	211
	212	/* CPLD Timing parameters for IFC GPCM */
	213	#define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xf) \| \
	214	FTIM0_GPCM_TEADC(0xf) \| \
	215	FTIM0_GPCM_TEAHC(0xf))
	216	#define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0xff) \| \
	217	FTIM1_GPCM_TRAD(0x3f))
	218	#define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0xf) \| \
	219	FTIM2_GPCM_TCH(0xf) \| \
	220	FTIM2_GPCM_TWP(0xff))
	221	#define CONFIG_SYS_FPGA_FTIM3 0x0
	222	#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
	223	#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
	224	#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
	225	#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
	226	#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
	227	#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
	228	#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
	229	#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
	230	#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_FPGA_CSPR_EXT
	231	#define CONFIG_SYS_CSPR1 CONFIG_SYS_FPGA_CSPR
	232	#define CONFIG_SYS_AMASK1 CONFIG_SYS_FPGA_AMASK
	233	#define CONFIG_SYS_CSOR1 CONFIG_SYS_FPGA_CSOR
	234	#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_FPGA_FTIM0
	235	#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_FPGA_FTIM1
	236	#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_FPGA_FTIM2
	237	#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_FPGA_FTIM3
	238
	239	/*
	240	* Serial Port
	241	*/
55d53ab4	242	#ifdef CONFIG_LPUART
55d53ab4 AW	243	#define CONFIG_LPUART_32B_REG
55d53ab4 AW	244	#else
c8a7d9da	245	#define CONFIG_CONS_INDEX 1
c8a7d9da	246	#define CONFIG_SYS_NS16550_SERIAL
f833cd62	247	#ifndef CONFIG_DM_SERIAL
c8a7d9da	248	#define CONFIG_SYS_NS16550_REG_SIZE 1
f833cd62	249	#endif
c8a7d9da	250	#define CONFIG_SYS_NS16550_CLK get_serial_clock()
55d53ab4	251	#endif
c8a7d9da	252
c8a7d9da WH	253	/*
	254	* I2C
	255	*/
c8a7d9da WH	256	#define CONFIG_SYS_I2C
c8a7d9da WH	257	#define CONFIG_SYS_I2C_MXC
03544c66 AA	258	#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
03544c66 AA	259	#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
f8cb101e	260	#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
c8a7d9da	261
5175a288	262	/* EEPROM */
5175a288 AW	263	#define CONFIG_ID_EEPROM
	264	#define CONFIG_SYS_I2C_EEPROM_NXID
	265	#define CONFIG_SYS_EEPROM_BUS_NUM 1
	266	#define CONFIG_SYS_I2C_EEPROM_ADDR 0x53
	267	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
	268	#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
	269	#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
5175a288	270
c8a7d9da WH	271	/*
	272	* MMC
	273	*/
c8a7d9da	274	#define CONFIG_FSL_ESDHC
c8a7d9da	275
9dd3d3c0	276	/* SPI */
947cee11	277	#if defined(CONFIG_QSPI_BOOT) \|\| defined(CONFIG_SD_BOOT_QSPI)
9dd3d3c0	278	/* QSPI */
d612f0ab AW	279	#define QSPI0_AMBA_BASE 0x40000000
	280	#define FSL_QSPI_FLASH_SIZE (1 << 24)
	281	#define FSL_QSPI_FLASH_NUM 2
	282
03d1d568	283	/* DSPI */
03d1d568 YY	284	#endif
03d1d568 YY	285
9dd3d3c0 HW	286	/* DM SPI */
9dd3d3c0 HW	287	#if defined(CONFIG_FSL_DSPI) \|\| defined(CONFIG_FSL_QSPI)
9dd3d3c0 HW	288	#define CONFIG_DM_SPI_FLASH
9dd3d3c0 HW	289	#endif
d612f0ab	290
b4ecc8c6 WH	291	/*
	292	* Video
	293	*/
b215fb3f	294	#ifdef CONFIG_VIDEO_FSL_DCU_FB
b4ecc8c6 WH	295	#define CONFIG_VIDEO_LOGO
	296	#define CONFIG_VIDEO_BMP_LOGO
	297
	298	#define CONFIG_FSL_DCU_SII9022A
	299	#define CONFIG_SYS_I2C_DVI_BUS_NUM 1
	300	#define CONFIG_SYS_I2C_DVI_ADDR 0x39
	301	#endif
	302
c8a7d9da WH	303	/*
	304	* eTSEC
	305	*/
	306	#define CONFIG_TSEC_ENET
	307
	308	#ifdef CONFIG_TSEC_ENET
	309	#define CONFIG_MII
	310	#define CONFIG_MII_DEFAULT_TSEC 1
	311	#define CONFIG_TSEC1 1
	312	#define CONFIG_TSEC1_NAME "eTSEC1"
	313	#define CONFIG_TSEC2 1
	314	#define CONFIG_TSEC2_NAME "eTSEC2"
	315	#define CONFIG_TSEC3 1
	316	#define CONFIG_TSEC3_NAME "eTSEC3"
	317
	318	#define TSEC1_PHY_ADDR 2
	319	#define TSEC2_PHY_ADDR 0
	320	#define TSEC3_PHY_ADDR 1
	321
	322	#define TSEC1_FLAGS (TSEC_GIGABIT \| TSEC_REDUCED)
	323	#define TSEC2_FLAGS (TSEC_GIGABIT \| TSEC_REDUCED)
	324	#define TSEC3_FLAGS (TSEC_GIGABIT \| TSEC_REDUCED)
	325
	326	#define TSEC1_PHYIDX 0
	327	#define TSEC2_PHYIDX 0
	328	#define TSEC3_PHYIDX 0
	329
	330	#define CONFIG_ETHPRIME "eTSEC1"
	331
c8a7d9da WH	332	#define CONFIG_PHY_ATHEROS
	333
	334	#define CONFIG_HAS_ETH0
	335	#define CONFIG_HAS_ETH1
	336	#define CONFIG_HAS_ETH2
	337	#endif
	338
da419027	339	/* PCIe */
b38eaec5 RD	340	#define CONFIG_PCIE1 /* PCIE controller 1 */
b38eaec5 RD	341	#define CONFIG_PCIE2 /* PCIE controller 2 */
da419027	342
180b8688	343	#ifdef CONFIG_PCI
180b8688	344	#define CONFIG_PCI_SCAN_SHOW
180b8688 ML	345	#endif
180b8688 ML	346
c8a7d9da	347	#define CONFIG_CMDLINE_TAG
8415bb68	348
1a2826f6	349	#define CONFIG_PEN_ADDR_BIG_ENDIAN
435acd83	350	#define CONFIG_LAYERSCAPE_NS_ACCESS
1a2826f6	351	#define CONFIG_SMP_PEN_ADDR 0x01ee0200
e4916e85	352	#define COUNTER_FREQUENCY 12500000
1a2826f6	353
c8a7d9da	354	#define CONFIG_HWCONFIG
03c22449 ZZ	355	#define HWCONFIG_BUFFER_SIZE 256
	356
	357	#define CONFIG_FSL_DEVICE_DISABLE
c8a7d9da	358
a65d7408 AW	359	#include <config_distro_defaults.h>
	360	#define BOOT_TARGET_DEVICES(func) \
	361	func(MMC, mmc, 0) \
	362	func(USB, usb, 0)
	363	#include <config_distro_bootcmd.h>
c8a7d9da	364
55d53ab4 AW	365	#ifdef CONFIG_LPUART
	366	#define CONFIG_EXTRA_ENV_SETTINGS \
	367	"bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0" \
7ff7166c	368	"initrd_high=0xffffffff\0" \
a65d7408 AW	369	"fdt_high=0xffffffff\0" \
	370	"fdt_addr=0x64f00000\0" \
	371	"kernel_addr=0x65000000\0" \
	372	"scriptaddr=0x80000000\0" \
b8ae6798	373	"scripthdraddr=0x80080000\0" \
a65d7408 AW	374	"fdtheader_addr_r=0x80100000\0" \
	375	"kernelheader_addr_r=0x80200000\0" \
	376	"kernel_addr_r=0x81000000\0" \
	377	"fdt_addr_r=0x90000000\0" \
	378	"ramdisk_addr_r=0xa0000000\0" \
	379	"load_addr=0xa0000000\0" \
	380	"kernel_size=0x2800000\0" \
	381	BOOTENV \
	382	"boot_scripts=ls1021atwr_boot.scr\0" \
b8ae6798	383	"boot_script_hdr=hdr_ls1021atwr_bs.out\0" \
a65d7408 AW	384	"scan_dev_for_boot_part=" \
	385	"part list ${devtype} ${devnum} devplist; " \
	386	"env exists devplist \|\| setenv devplist 1; " \
	387	"for distro_bootpart in ${devplist}; do " \
	388	"if fstype ${devtype} " \
	389	"${devnum}:${distro_bootpart} " \
	390	"bootfstype; then " \
	391	"run scan_dev_for_boot; " \
	392	"fi; " \
	393	"done\0" \
b8ae6798 SG	394	"scan_dev_for_boot=" \
	395	"echo Scanning ${devtype} " \
	396	"${devnum}:${distro_bootpart}...; " \
	397	"for prefix in ${boot_prefixes}; do " \
	398	"run scan_dev_for_scripts; " \
	399	"done;" \
	400	"\0" \
	401	"boot_a_script=" \
	402	"load ${devtype} ${devnum}:${distro_bootpart} " \
	403	"${scriptaddr} ${prefix}${script}; " \
	404	"env exists secureboot && load ${devtype} " \
	405	"${devnum}:${distro_bootpart} " \
	406	"${scripthdraddr} ${prefix}${boot_script_hdr} " \
	407	"&& esbc_validate ${scripthdraddr};" \
	408	"source ${scriptaddr}\0" \
a65d7408 AW	409	"installer=load mmc 0:2 $load_addr " \
	410	"/flex_installer_arm32.itb; " \
	411	"bootm $load_addr#ls1021atwr\0" \
	412	"qspi_bootcmd=echo Trying load from qspi..;" \
	413	"sf probe && sf read $load_addr " \
	414	"$kernel_addr $kernel_size && bootm $load_addr#$board\0" \
	415	"nor_bootcmd=echo Trying load from nor..;" \
	416	"cp.b $kernel_addr $load_addr " \
	417	"$kernel_size && bootm $load_addr#$board\0"
55d53ab4	418	#else
c8a7d9da WH	419	#define CONFIG_EXTRA_ENV_SETTINGS \
c8a7d9da WH	420	"bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \
7ff7166c	421	"initrd_high=0xffffffff\0" \
a65d7408 AW	422	"fdt_high=0xffffffff\0" \
	423	"fdt_addr=0x64f00000\0" \
	424	"kernel_addr=0x65000000\0" \
	425	"scriptaddr=0x80000000\0" \
b8ae6798	426	"scripthdraddr=0x80080000\0" \
a65d7408 AW	427	"fdtheader_addr_r=0x80100000\0" \
	428	"kernelheader_addr_r=0x80200000\0" \
	429	"kernel_addr_r=0x81000000\0" \
	430	"fdt_addr_r=0x90000000\0" \
	431	"ramdisk_addr_r=0xa0000000\0" \
	432	"load_addr=0xa0000000\0" \
	433	"kernel_size=0x2800000\0" \
	434	BOOTENV \
	435	"boot_scripts=ls1021atwr_boot.scr\0" \
b8ae6798	436	"boot_script_hdr=hdr_ls1021atwr_bs.out\0" \
a65d7408 AW	437	"scan_dev_for_boot_part=" \
	438	"part list ${devtype} ${devnum} devplist; " \
	439	"env exists devplist \|\| setenv devplist 1; " \
	440	"for distro_bootpart in ${devplist}; do " \
	441	"if fstype ${devtype} " \
	442	"${devnum}:${distro_bootpart} " \
	443	"bootfstype; then " \
	444	"run scan_dev_for_boot; " \
	445	"fi; " \
	446	"done\0" \
b8ae6798 SG	447	"scan_dev_for_boot=" \
	448	"echo Scanning ${devtype} " \
	449	"${devnum}:${distro_bootpart}...; " \
	450	"for prefix in ${boot_prefixes}; do " \
	451	"run scan_dev_for_scripts; " \
	452	"done;" \
	453	"\0" \
	454	"boot_a_script=" \
	455	"load ${devtype} ${devnum}:${distro_bootpart} " \
	456	"${scriptaddr} ${prefix}${script}; " \
	457	"env exists secureboot && load ${devtype} " \
	458	"${devnum}:${distro_bootpart} " \
	459	"${scripthdraddr} ${prefix}${boot_script_hdr} " \
	460	"&& esbc_validate ${scripthdraddr};" \
	461	"source ${scriptaddr}\0" \
a65d7408 AW	462	"installer=load mmc 0:2 $load_addr " \
	463	"/flex_installer_arm32.itb; " \
	464	"bootm $load_addr#ls1021atwr\0" \
	465	"qspi_bootcmd=echo Trying load from qspi..;" \
	466	"sf probe && sf read $load_addr " \
	467	"$kernel_addr $kernel_size && bootm $load_addr#$board\0" \
	468	"nor_bootcmd=echo Trying load from nor..;" \
	469	"cp.b $kernel_addr $load_addr " \
	470	"$kernel_size && bootm $load_addr#$board\0"
55d53ab4	471	#endif
c8a7d9da	472
a65d7408 AW	473	#undef CONFIG_BOOTCOMMAND
a65d7408 AW	474	#if defined(CONFIG_QSPI_BOOT) \|\| defined(CONFIG_SD_BOOT_QSPI)
b8ae6798 SG	475	#define CONFIG_BOOTCOMMAND "run distro_bootcmd; env exists secureboot" \
b8ae6798 SG	476	"&& esbc_halt; run qspi_bootcmd;"
a65d7408	477	#else
b8ae6798 SG	478	#define CONFIG_BOOTCOMMAND "run distro_bootcmd; env exists secureboot" \
b8ae6798 SG	479	"&& esbc_halt; run nor_bootcmd;"
a65d7408 AW	480	#endif
a65d7408 AW	481
c8a7d9da WH	482	/*
	483	* Miscellaneous configurable options
	484	*/
	485	#define CONFIG_SYS_LONGHELP /* undef to save memory */
c8a7d9da	486	#define CONFIG_AUTO_COMPLETE
c8a7d9da	487
c8a7d9da WH	488	#define CONFIG_SYS_MEMTEST_START 0x80000000
	489	#define CONFIG_SYS_MEMTEST_END 0x9fffffff
	490
	491	#define CONFIG_SYS_LOAD_ADDR 0x82000000
c8a7d9da	492
660673af XL	493	#define CONFIG_LS102XA_STREAM_ID
660673af XL	494
c8a7d9da WH	495	#define CONFIG_SYS_INIT_SP_OFFSET \
	496	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
	497	#define CONFIG_SYS_INIT_SP_ADDR \
	498	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
	499
8415bb68 AW	500	#ifdef CONFIG_SPL_BUILD
	501	#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
	502	#else
c8a7d9da	503	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
8415bb68	504	#endif
c8a7d9da	505
615bfce5	506	#define CONFIG_SYS_QE_FW_ADDR 0x60940000
eaa859e7	507
c8a7d9da WH	508	/*
	509	* Environment
	510	*/
	511	#define CONFIG_ENV_OVERWRITE
	512
8415bb68	513	#if defined(CONFIG_SD_BOOT)
615bfce5	514	#define CONFIG_ENV_OFFSET 0x300000
8415bb68 AW	515	#define CONFIG_SYS_MMC_ENV_DEV 0
8415bb68 AW	516	#define CONFIG_ENV_SIZE 0x20000
d612f0ab	517	#elif defined(CONFIG_QSPI_BOOT)
d612f0ab	518	#define CONFIG_ENV_SIZE 0x2000
615bfce5	519	#define CONFIG_ENV_OFFSET 0x300000
d612f0ab	520	#define CONFIG_ENV_SECT_SIZE 0x10000
8415bb68	521	#else
615bfce5	522	#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x300000)
c8a7d9da WH	523	#define CONFIG_ENV_SIZE 0x20000
c8a7d9da WH	524	#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
8415bb68	525	#endif
c8a7d9da	526
4ba4a095 RG	527	#define CONFIG_MISC_INIT_R
4ba4a095 RG	528
ef6c55a2	529	#include <asm/fsl_secure_boot.h>
cc7b8b9a	530	#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
4ba4a095	531
c8a7d9da	532	#endif