[people/ms/u-boot.git] / include / configs / ls1021atwr.h

/*
 * Copyright 2014 Freescale Semiconductor, Inc.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __CONFIG_H
#define __CONFIG_H

#define CONFIG_ARMV7_PSCI_1_0

#define CONFIG_ARMV7_SECURE_BASE	OCRAM_BASE_S_ADDR

#define CONFIG_SYS_FSL_CLK

#define CONFIG_SKIP_LOWLEVEL_INIT
#define CONFIG_DEEP_SLEEP

/*
 * Size of malloc() pool
 */
#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 16 * 1024 * 1024)

#define CONFIG_SYS_INIT_RAM_ADDR	OCRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE	OCRAM_SIZE

/*
 * USB
 */

/*
 * EHCI Support - disbaled by default as
 * there is no signal coming out of soc on
 * this board for this controller. However,
 * the silicon still has this controller,
 * and anyone can use this controller by
 * taking signals out on their board.
 */

/*#define CONFIG_HAS_FSL_DR_USB*/

#ifdef CONFIG_HAS_FSL_DR_USB
#define CONFIG_USB_EHCI_FSL
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
#endif

#define CONFIG_SYS_CLK_FREQ		100000000
#define CONFIG_DDR_CLK_FREQ		100000000

#define DDR_SDRAM_CFG			0x470c0008
#define DDR_CS0_BNDS			0x008000bf
#define DDR_CS0_CONFIG			0x80014302
#define DDR_TIMING_CFG_0		0x50550004
#define DDR_TIMING_CFG_1		0xbcb38c56
#define DDR_TIMING_CFG_2		0x0040d120
#define DDR_TIMING_CFG_3		0x010e1000
#define DDR_TIMING_CFG_4		0x00000001
#define DDR_TIMING_CFG_5		0x03401400
#define DDR_SDRAM_CFG_2			0x00401010
#define DDR_SDRAM_MODE			0x00061c60
#define DDR_SDRAM_MODE_2		0x00180000
#define DDR_SDRAM_INTERVAL		0x18600618
#define DDR_DDR_WRLVL_CNTL		0x8655f605
#define DDR_DDR_WRLVL_CNTL_2		0x05060607
#define DDR_DDR_WRLVL_CNTL_3		0x05050505
#define DDR_DDR_CDR1			0x80040000
#define DDR_DDR_CDR2			0x00000001
#define DDR_SDRAM_CLK_CNTL		0x02000000
#define DDR_DDR_ZQ_CNTL			0x89080600
#define DDR_CS0_CONFIG_2		0
#define DDR_SDRAM_CFG_MEM_EN		0x80000000
#define SDRAM_CFG2_D_INIT		0x00000010
#define DDR_CDR2_VREF_TRAIN_EN		0x00000080
#define SDRAM_CFG2_FRC_SR		0x80000000
#define SDRAM_CFG_BI			0x00000001

#ifdef CONFIG_RAMBOOT_PBL
#define CONFIG_SYS_FSL_PBL_PBI	board/freescale/ls1021atwr/ls102xa_pbi.cfg
#endif

#ifdef CONFIG_SD_BOOT
#ifdef CONFIG_SD_BOOT_QSPI
#define CONFIG_SYS_FSL_PBL_RCW	\
	board/freescale/ls1021atwr/ls102xa_rcw_sd_qspi.cfg
#else
#define CONFIG_SYS_FSL_PBL_RCW	\
	board/freescale/ls1021atwr/ls102xa_rcw_sd_ifc.cfg
#endif
#define CONFIG_SPL_FRAMEWORK

#ifdef CONFIG_SECURE_BOOT
/*
 * HDR would be appended at end of image and copied to DDR along
 * with U-Boot image.
 */
#define CONFIG_U_BOOT_HDR_SIZE				(16 << 10)
#endif /* ifdef CONFIG_SECURE_BOOT */

#define CONFIG_SPL_TEXT_BASE		0x10000000
#define CONFIG_SPL_MAX_SIZE		0x1a000
#define CONFIG_SPL_STACK		0x1001d000
#define CONFIG_SPL_PAD_TO		0x1c000
#define CONFIG_SYS_TEXT_BASE		0x82000000

#define CONFIG_SYS_SPL_MALLOC_START	(CONFIG_SYS_TEXT_BASE + \
		CONFIG_SYS_MONITOR_LEN)
#define CONFIG_SYS_SPL_MALLOC_SIZE	0x100000
#define CONFIG_SPL_BSS_START_ADDR	0x80100000
#define CONFIG_SPL_BSS_MAX_SIZE		0x80000

#ifdef CONFIG_U_BOOT_HDR_SIZE
/*
 * HDR would be appended at end of image and copied to DDR along
 * with U-Boot image. Here u-boot max. size is 512K. So if binary
 * size increases then increase this size in case of secure boot as
 * it uses raw u-boot image instead of fit image.
 */
#define CONFIG_SYS_MONITOR_LEN		(0x100000 + CONFIG_U_BOOT_HDR_SIZE)
#else
#define CONFIG_SYS_MONITOR_LEN		0x100000
#endif /* ifdef CONFIG_U_BOOT_HDR_SIZE */
#endif

#ifdef CONFIG_QSPI_BOOT
#define CONFIG_SYS_TEXT_BASE		0x40100000
#endif

#ifndef CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_TEXT_BASE		0x60100000
#endif

#define CONFIG_NR_DRAM_BANKS		1
#define PHYS_SDRAM			0x80000000
#define PHYS_SDRAM_SIZE			(1u * 1024 * 1024 * 1024)

#define CONFIG_SYS_DDR_SDRAM_BASE      0x80000000UL
#define CONFIG_SYS_SDRAM_BASE          CONFIG_SYS_DDR_SDRAM_BASE

#if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \
	!defined(CONFIG_QSPI_BOOT)
#define CONFIG_U_QE
#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
#endif

/*
 * IFC Definitions
 */
#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
#define CONFIG_FSL_IFC
#define CONFIG_SYS_FLASH_BASE		0x60000000
#define CONFIG_SYS_FLASH_BASE_PHYS	CONFIG_SYS_FLASH_BASE

#define CONFIG_SYS_NOR0_CSPR_EXT	(0x0)
#define CONFIG_SYS_NOR0_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
				CSPR_PORT_SIZE_16 | \
				CSPR_MSEL_NOR | \
				CSPR_V)
#define CONFIG_SYS_NOR_AMASK		IFC_AMASK(128 * 1024 * 1024)

/* NOR Flash Timing Params */
#define CONFIG_SYS_NOR_CSOR		(CSOR_NOR_ADM_SHIFT(4) | \
					CSOR_NOR_TRHZ_80)
#define CONFIG_SYS_NOR_FTIM0		(FTIM0_NOR_TACSE(0x4) | \
					FTIM0_NOR_TEADC(0x5) | \
					FTIM0_NOR_TAVDS(0x0) | \
					FTIM0_NOR_TEAHC(0x5))
#define CONFIG_SYS_NOR_FTIM1		(FTIM1_NOR_TACO(0x35) | \
					FTIM1_NOR_TRAD_NOR(0x1A) | \
					FTIM1_NOR_TSEQRAD_NOR(0x13))
#define CONFIG_SYS_NOR_FTIM2		(FTIM2_NOR_TCS(0x4) | \
					FTIM2_NOR_TCH(0x4) | \
					FTIM2_NOR_TWP(0x1c) | \
					FTIM2_NOR_TWPH(0x0e))
#define CONFIG_SYS_NOR_FTIM3		0

#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
#define CONFIG_SYS_FLASH_QUIET_TEST
#define CONFIG_FLASH_SHOW_PROGRESS	45	/* count down from 45/5: 9..1 */

#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* number of banks */
#define CONFIG_SYS_MAX_FLASH_SECT	1024	/* sectors per device */
#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */

#define CONFIG_SYS_FLASH_EMPTY_INFO
#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE_PHYS }

#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
#define CONFIG_SYS_WRITE_SWAPPED_DATA
#endif

/* CPLD */

#define CONFIG_SYS_CPLD_BASE	0x7fb00000
#define CPLD_BASE_PHYS		CONFIG_SYS_CPLD_BASE

#define CONFIG_SYS_FPGA_CSPR_EXT        (0x0)
#define CONFIG_SYS_FPGA_CSPR		(CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \
					CSPR_PORT_SIZE_8 | \
					CSPR_MSEL_GPCM | \
					CSPR_V)
#define CONFIG_SYS_FPGA_AMASK		IFC_AMASK(64 * 1024)
#define CONFIG_SYS_FPGA_CSOR		(CSOR_NOR_ADM_SHIFT(4) | \
					CSOR_NOR_NOR_MODE_AVD_NOR | \
					CSOR_NOR_TRHZ_80)

/* CPLD Timing parameters for IFC GPCM */
#define CONFIG_SYS_FPGA_FTIM0		(FTIM0_GPCM_TACSE(0xf) | \
					FTIM0_GPCM_TEADC(0xf) | \
					FTIM0_GPCM_TEAHC(0xf))
#define CONFIG_SYS_FPGA_FTIM1		(FTIM1_GPCM_TACO(0xff) | \
					FTIM1_GPCM_TRAD(0x3f))
#define CONFIG_SYS_FPGA_FTIM2		(FTIM2_GPCM_TCS(0xf) | \
					FTIM2_GPCM_TCH(0xf) | \
					FTIM2_GPCM_TWP(0xff))
#define CONFIG_SYS_FPGA_FTIM3           0x0
#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NOR0_CSPR_EXT
#define CONFIG_SYS_CSPR0		CONFIG_SYS_NOR0_CSPR
#define CONFIG_SYS_AMASK0		CONFIG_SYS_NOR_AMASK
#define CONFIG_SYS_CSOR0		CONFIG_SYS_NOR_CSOR
#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NOR_FTIM0
#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NOR_FTIM1
#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NOR_FTIM2
#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NOR_FTIM3
#define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_FPGA_CSPR_EXT
#define CONFIG_SYS_CSPR1		CONFIG_SYS_FPGA_CSPR
#define CONFIG_SYS_AMASK1		CONFIG_SYS_FPGA_AMASK
#define CONFIG_SYS_CSOR1		CONFIG_SYS_FPGA_CSOR
#define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_FPGA_FTIM0
#define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_FPGA_FTIM1
#define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_FPGA_FTIM2
#define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_FPGA_FTIM3

/*
 * Serial Port
 */
#ifdef CONFIG_LPUART
#define CONFIG_LPUART_32B_REG
#else
#define CONFIG_CONS_INDEX		1
#define CONFIG_SYS_NS16550_SERIAL
#ifndef CONFIG_DM_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	1
#endif
#define CONFIG_SYS_NS16550_CLK		get_serial_clock()
#endif

/*
 * I2C
 */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_MXC
#define CONFIG_SYS_I2C_MXC_I2C1		/* enable I2C bus 1 */
#define CONFIG_SYS_I2C_MXC_I2C2		/* enable I2C bus 2 */
#define CONFIG_SYS_I2C_MXC_I2C3		/* enable I2C bus 3 */

/* EEPROM */
#define CONFIG_ID_EEPROM
#define CONFIG_SYS_I2C_EEPROM_NXID
#define CONFIG_SYS_EEPROM_BUS_NUM		1
#define CONFIG_SYS_I2C_EEPROM_ADDR		0x53
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	3
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	5

/*
 * MMC
 */
#define CONFIG_FSL_ESDHC

/* SPI */
#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
/* QSPI */
#define QSPI0_AMBA_BASE			0x40000000
#define FSL_QSPI_FLASH_SIZE		(1 << 24)
#define FSL_QSPI_FLASH_NUM		2

/* DSPI */
#endif

/* DM SPI */
#if defined(CONFIG_FSL_DSPI) || defined(CONFIG_FSL_QSPI)
#define CONFIG_DM_SPI_FLASH
#endif

/*
 * Video
 */
#ifdef CONFIG_VIDEO_FSL_DCU_FB
#define CONFIG_VIDEO_LOGO
#define CONFIG_VIDEO_BMP_LOGO

#define CONFIG_FSL_DCU_SII9022A
#define CONFIG_SYS_I2C_DVI_BUS_NUM	1
#define CONFIG_SYS_I2C_DVI_ADDR		0x39
#endif

/*
 * eTSEC
 */
#define CONFIG_TSEC_ENET

#ifdef CONFIG_TSEC_ENET
#define CONFIG_MII
#define CONFIG_MII_DEFAULT_TSEC		1
#define CONFIG_TSEC1			1
#define CONFIG_TSEC1_NAME		"eTSEC1"
#define CONFIG_TSEC2			1
#define CONFIG_TSEC2_NAME		"eTSEC2"
#define CONFIG_TSEC3			1
#define CONFIG_TSEC3_NAME		"eTSEC3"

#define TSEC1_PHY_ADDR			2
#define TSEC2_PHY_ADDR			0
#define TSEC3_PHY_ADDR			1

#define TSEC1_FLAGS			(TSEC_GIGABIT | TSEC_REDUCED)
#define TSEC2_FLAGS			(TSEC_GIGABIT | TSEC_REDUCED)
#define TSEC3_FLAGS			(TSEC_GIGABIT | TSEC_REDUCED)

#define TSEC1_PHYIDX			0
#define TSEC2_PHYIDX			0
#define TSEC3_PHYIDX			0

#define CONFIG_ETHPRIME			"eTSEC1"

#define CONFIG_PHY_ATHEROS

#define CONFIG_HAS_ETH0
#define CONFIG_HAS_ETH1
#define CONFIG_HAS_ETH2
#endif

/* PCIe */
#define CONFIG_PCIE1		/* PCIE controller 1 */
#define CONFIG_PCIE2		/* PCIE controller 2 */

#ifdef CONFIG_PCI
#define CONFIG_PCI_SCAN_SHOW
#endif

#define CONFIG_CMDLINE_TAG

#define CONFIG_PEN_ADDR_BIG_ENDIAN
#define CONFIG_LAYERSCAPE_NS_ACCESS
#define CONFIG_SMP_PEN_ADDR		0x01ee0200
#define COUNTER_FREQUENCY		12500000

#define CONFIG_HWCONFIG
#define HWCONFIG_BUFFER_SIZE		256

#define CONFIG_FSL_DEVICE_DISABLE

#include <config_distro_defaults.h>
#define BOOT_TARGET_DEVICES(func) \
	func(MMC, mmc, 0) \
	func(USB, usb, 0)
#include <config_distro_bootcmd.h>

#ifdef CONFIG_LPUART
#define CONFIG_EXTRA_ENV_SETTINGS       \
	"bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0" \
	"initrd_high=0xffffffff\0"      \
	"fdt_high=0xffffffff\0"		\
	"fdt_addr=0x64f00000\0"		\
	"kernel_addr=0x65000000\0"	\
	"scriptaddr=0x80000000\0"	\
	"scripthdraddr=0x80080000\0"	\
	"fdtheader_addr_r=0x80100000\0"	\
	"kernelheader_addr_r=0x80200000\0"	\
	"kernel_addr_r=0x81000000\0"	\
	"fdt_addr_r=0x90000000\0"	\
	"ramdisk_addr_r=0xa0000000\0"	\
	"load_addr=0xa0000000\0"	\
	"kernel_size=0x2800000\0"	\
	"kernel_addr_sd=0x8000\0"	\
	"kernel_size_sd=0x14000\0"	\
	BOOTENV				\
	"boot_scripts=ls1021atwr_boot.scr\0"	\
	"boot_script_hdr=hdr_ls1021atwr_bs.out\0"	\
		"scan_dev_for_boot_part="	\
			"part list ${devtype} ${devnum} devplist; "	\
			"env exists devplist || setenv devplist 1; "	\
			"for distro_bootpart in ${devplist}; do "	\
			"if fstype ${devtype} "				\
				"${devnum}:${distro_bootpart} "		\
				"bootfstype; then "			\
				"run scan_dev_for_boot; "		\
			"fi; "			\
		"done\0"			\
	"scan_dev_for_boot="				  \
		"echo Scanning ${devtype} "		  \
				"${devnum}:${distro_bootpart}...; "  \
		"for prefix in ${boot_prefixes}; do "	  \
			"run scan_dev_for_scripts; "	  \
		"done;"					  \
		"\0"					  \
	"boot_a_script="				  \
		"load ${devtype} ${devnum}:${distro_bootpart} "  \
			"${scriptaddr} ${prefix}${script}; "    \
		"env exists secureboot && load ${devtype} "     \
			"${devnum}:${distro_bootpart} "		\
			"${scripthdraddr} ${prefix}${boot_script_hdr} " \
			"&& esbc_validate ${scripthdraddr};"    \
		"source ${scriptaddr}\0"	  \
	"installer=load mmc 0:2 $load_addr "	\
		"/flex_installer_arm32.itb; "		\
		"bootm $load_addr#ls1021atwr\0"	\
	"qspi_bootcmd=echo Trying load from qspi..;"	\
		"sf probe && sf read $load_addr "	\
		"$kernel_addr $kernel_size && bootm $load_addr#$board\0"	\
	"nor_bootcmd=echo Trying load from nor..;"	\
		"cp.b $kernel_addr $load_addr "		\
		"$kernel_size && bootm $load_addr#$board\0"
#else
#define CONFIG_EXTRA_ENV_SETTINGS	\
	"bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \
	"initrd_high=0xffffffff\0"      \
	"fdt_high=0xffffffff\0"		\
	"fdt_addr=0x64f00000\0"		\
	"kernel_addr=0x61000000\0"	\
	"kernelheader_addr=0x60800000\0"	\
	"scriptaddr=0x80000000\0"	\
	"scripthdraddr=0x80080000\0"	\
	"fdtheader_addr_r=0x80100000\0"	\
	"kernelheader_addr_r=0x80200000\0"	\
	"kernel_addr_r=0x81000000\0"	\
	"kernelheader_size=0x40000\0"	\
	"fdt_addr_r=0x90000000\0"	\
	"ramdisk_addr_r=0xa0000000\0"	\
	"load_addr=0xa0000000\0"	\
	"kernel_size=0x2800000\0"	\
	"kernel_addr_sd=0x8000\0"	\
	"kernel_size_sd=0x14000\0"	\
	"kernelhdr_addr_sd=0x4000\0"		\
	"kernelhdr_size_sd=0x10\0"		\
	BOOTENV				\
	"boot_scripts=ls1021atwr_boot.scr\0"	\
	"boot_script_hdr=hdr_ls1021atwr_bs.out\0"	\
		"scan_dev_for_boot_part="	\
			"part list ${devtype} ${devnum} devplist; "	\
			"env exists devplist || setenv devplist 1; "	\
			"for distro_bootpart in ${devplist}; do "	\
			"if fstype ${devtype} "				\
				"${devnum}:${distro_bootpart} "		\
				"bootfstype; then "			\
				"run scan_dev_for_boot; "		\
			"fi; "			\
		"done\0"			\
	"scan_dev_for_boot="				  \
		"echo Scanning ${devtype} "		  \
				"${devnum}:${distro_bootpart}...; "  \
		"for prefix in ${boot_prefixes}; do "	  \
			"run scan_dev_for_scripts; "	  \
		"done;"					  \
		"\0"					  \
	"boot_a_script="				  \
		"load ${devtype} ${devnum}:${distro_bootpart} "  \
			"${scriptaddr} ${prefix}${script}; "    \
		"env exists secureboot && load ${devtype} "     \
			"${devnum}:${distro_bootpart} "		\
			"${scripthdraddr} ${prefix}${boot_script_hdr} " \
			"&& esbc_validate ${scripthdraddr};"    \
		"source ${scriptaddr}\0"	  \
	"qspi_bootcmd=echo Trying load from qspi..;"	\
		"sf probe && sf read $load_addr "	\
		"$kernel_addr $kernel_size; env exists secureboot "	\
		"&& sf read $kernelheader_addr_r $kernelheader_addr "	\
		"$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
		"bootm $load_addr#$board\0" \
	"nor_bootcmd=echo Trying load from nor..;"	\
		"cp.b $kernel_addr $load_addr "		\
		"$kernel_size; env exists secureboot "	\
		"&& cp.b $kernelheader_addr $kernelheader_addr_r "	\
		"$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
		"bootm $load_addr#$board\0"	\
	"sd_bootcmd=echo Trying load from SD ..;"       \
		"mmcinfo && mmc read $load_addr "	\
		"$kernel_addr_sd $kernel_size_sd && "	\
		"env exists secureboot && mmc read $kernelheader_addr_r "		\
		"$kernelhdr_addr_sd $kernelhdr_size_sd "		\
		" && esbc_validate ${kernelheader_addr_r};"	\
		"bootm $load_addr#$board\0"
#endif

#undef CONFIG_BOOTCOMMAND
#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
#define CONFIG_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd"	\
			   "env exists secureboot && esbc_halt"
#elif defined(CONFIG_SD_BOOT)
#define CONFIG_BOOTCOMMAND "run distro_bootcmd; run sd_bootcmd; "	\
			   "env exists secureboot && esbc_halt;"
#else
#define CONFIG_BOOTCOMMAND "run distro_bootcmd; run nor_bootcmd;"	\
			   "env exists secureboot && esbc_halt;"
#endif

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP		/* undef to save memory */
#define CONFIG_AUTO_COMPLETE

#define CONFIG_SYS_MEMTEST_START	0x80000000
#define CONFIG_SYS_MEMTEST_END		0x9fffffff

#define CONFIG_SYS_LOAD_ADDR		0x82000000

#define CONFIG_LS102XA_STREAM_ID

#define CONFIG_SYS_INIT_SP_OFFSET \
	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_ADDR \
	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)

#ifdef CONFIG_SPL_BUILD
#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
#else
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
#endif

#define CONFIG_SYS_QE_FW_ADDR     0x60940000

/*
 * Environment
 */
#define CONFIG_ENV_OVERWRITE

#if defined(CONFIG_SD_BOOT)
#define CONFIG_ENV_OFFSET		0x300000
#define CONFIG_SYS_MMC_ENV_DEV		0
#define CONFIG_ENV_SIZE			0x20000
#elif defined(CONFIG_QSPI_BOOT)
#define CONFIG_ENV_SIZE			0x2000
#define CONFIG_ENV_OFFSET		0x300000
#define CONFIG_ENV_SECT_SIZE		0x10000
#else
#define CONFIG_ENV_ADDR			(CONFIG_SYS_FLASH_BASE + 0x300000)
#define CONFIG_ENV_SIZE			0x20000
#define CONFIG_ENV_SECT_SIZE		0x20000 /* 128K (one sector) */
#endif

#define CONFIG_MISC_INIT_R

#include <asm/fsl_secure_boot.h>
#define CONFIG_SYS_BOOTM_LEN	(64 << 20) /* Increase max gunzip size */

#endif
Commit	Line	Data
c8a7d9da WH	1	/*
	2	* Copyright 2014 Freescale Semiconductor, Inc.
	3	*
	4	* SPDX-License-Identifier: GPL-2.0+
	5	*/
	6
	7	#ifndef __CONFIG_H
	8	#define __CONFIG_H
	9
aeb901f2	10	#define CONFIG_ARMV7_PSCI_1_0
340848b1	11
3288628a HZ	12	#define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR
3288628a HZ	13
18fb0e3c	14	#define CONFIG_SYS_FSL_CLK
c8a7d9da	15
c8a7d9da	16	#define CONFIG_SKIP_LOWLEVEL_INIT
99e1bd42	17	#define CONFIG_DEEP_SLEEP
c8a7d9da WH	18
	19	/*
	20	* Size of malloc() pool
	21	*/
	22	#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024 * 1024)
	23
	24	#define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR
	25	#define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE
	26
10a28644 RM	27	/*
	28	* USB
	29	*/
	30
	31	/*
	32	* EHCI Support - disbaled by default as
	33	* there is no signal coming out of soc on
	34	* this board for this controller. However,
	35	* the silicon still has this controller,
	36	* and anyone can use this controller by
	37	* taking signals out on their board.
	38	*/
	39
	40	/#define CONFIG_HAS_FSL_DR_USB/
	41
	42	#ifdef CONFIG_HAS_FSL_DR_USB
10a28644 RM	43	#define CONFIG_USB_EHCI_FSL
	44	#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
	45	#endif
	46
c8a7d9da WH	47	#define CONFIG_SYS_CLK_FREQ 100000000
	48	#define CONFIG_DDR_CLK_FREQ 100000000
	49
a88cc3bd YS	50	#define DDR_SDRAM_CFG 0x470c0008
	51	#define DDR_CS0_BNDS 0x008000bf
	52	#define DDR_CS0_CONFIG 0x80014302
	53	#define DDR_TIMING_CFG_0 0x50550004
	54	#define DDR_TIMING_CFG_1 0xbcb38c56
	55	#define DDR_TIMING_CFG_2 0x0040d120
	56	#define DDR_TIMING_CFG_3 0x010e1000
	57	#define DDR_TIMING_CFG_4 0x00000001
	58	#define DDR_TIMING_CFG_5 0x03401400
	59	#define DDR_SDRAM_CFG_2 0x00401010
	60	#define DDR_SDRAM_MODE 0x00061c60
	61	#define DDR_SDRAM_MODE_2 0x00180000
	62	#define DDR_SDRAM_INTERVAL 0x18600618
	63	#define DDR_DDR_WRLVL_CNTL 0x8655f605
	64	#define DDR_DDR_WRLVL_CNTL_2 0x05060607
	65	#define DDR_DDR_WRLVL_CNTL_3 0x05050505
	66	#define DDR_DDR_CDR1 0x80040000
	67	#define DDR_DDR_CDR2 0x00000001
	68	#define DDR_SDRAM_CLK_CNTL 0x02000000
	69	#define DDR_DDR_ZQ_CNTL 0x89080600
	70	#define DDR_CS0_CONFIG_2 0
	71	#define DDR_SDRAM_CFG_MEM_EN 0x80000000
99e1bd42 TY	72	#define SDRAM_CFG2_D_INIT 0x00000010
	73	#define DDR_CDR2_VREF_TRAIN_EN 0x00000080
	74	#define SDRAM_CFG2_FRC_SR 0x80000000
	75	#define SDRAM_CFG_BI 0x00000001
a88cc3bd	76
8415bb68 AW	77	#ifdef CONFIG_RAMBOOT_PBL
	78	#define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1021atwr/ls102xa_pbi.cfg
	79	#endif
	80
	81	#ifdef CONFIG_SD_BOOT
947cee11 AW	82	#ifdef CONFIG_SD_BOOT_QSPI
	83	#define CONFIG_SYS_FSL_PBL_RCW \
	84	board/freescale/ls1021atwr/ls102xa_rcw_sd_qspi.cfg
	85	#else
	86	#define CONFIG_SYS_FSL_PBL_RCW \
	87	board/freescale/ls1021atwr/ls102xa_rcw_sd_ifc.cfg
	88	#endif
8415bb68	89	#define CONFIG_SPL_FRAMEWORK
e7e720c2 SG	90
e7e720c2 SG	91	#ifdef CONFIG_SECURE_BOOT
e7e720c2 SG	92	/*
	93	* HDR would be appended at end of image and copied to DDR along
	94	* with U-Boot image.
	95	*/
693d4c9f	96	#define CONFIG_U_BOOT_HDR_SIZE (16 << 10)
e7e720c2	97	#endif /* ifdef CONFIG_SECURE_BOOT */
8415bb68 AW	98
	99	#define CONFIG_SPL_TEXT_BASE 0x10000000
	100	#define CONFIG_SPL_MAX_SIZE 0x1a000
	101	#define CONFIG_SPL_STACK 0x1001d000
	102	#define CONFIG_SPL_PAD_TO 0x1c000
	103	#define CONFIG_SYS_TEXT_BASE 0x82000000
	104
99e1bd42 TY	105	#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE + \
99e1bd42 TY	106	CONFIG_SYS_MONITOR_LEN)
8415bb68 AW	107	#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
	108	#define CONFIG_SPL_BSS_START_ADDR 0x80100000
	109	#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
e7e720c2 SG	110
	111	#ifdef CONFIG_U_BOOT_HDR_SIZE
	112	/*
	113	* HDR would be appended at end of image and copied to DDR along
	114	* with U-Boot image. Here u-boot max. size is 512K. So if binary
	115	* size increases then increase this size in case of secure boot as
	116	* it uses raw u-boot image instead of fit image.
	117	*/
9b6639fa	118	#define CONFIG_SYS_MONITOR_LEN (0x100000 + CONFIG_U_BOOT_HDR_SIZE)
e7e720c2	119	#else
9b6639fa	120	#define CONFIG_SYS_MONITOR_LEN 0x100000
e7e720c2	121	#endif /* ifdef CONFIG_U_BOOT_HDR_SIZE */
8415bb68 AW	122	#endif
8415bb68 AW	123
d612f0ab	124	#ifdef CONFIG_QSPI_BOOT
615bfce5	125	#define CONFIG_SYS_TEXT_BASE 0x40100000
947cee11 AW	126	#endif
947cee11 AW	127
c8a7d9da	128	#ifndef CONFIG_SYS_TEXT_BASE
1c69a51c	129	#define CONFIG_SYS_TEXT_BASE 0x60100000
c8a7d9da WH	130	#endif
	131
	132	#define CONFIG_NR_DRAM_BANKS 1
	133	#define PHYS_SDRAM 0x80000000
	134	#define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024)
	135
	136	#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
	137	#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
	138
4c59ab9c AW	139	#if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \
4c59ab9c AW	140	!defined(CONFIG_QSPI_BOOT)
eaa859e7	141	#define CONFIG_U_QE
5aa03ddd	142	#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
eaa859e7 ZQ	143	#endif
eaa859e7 ZQ	144
c8a7d9da WH	145	/*
	146	* IFC Definitions
	147	*/
947cee11	148	#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
c8a7d9da WH	149	#define CONFIG_FSL_IFC
	150	#define CONFIG_SYS_FLASH_BASE 0x60000000
	151	#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
	152
	153	#define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
	154	#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \| \
	155	CSPR_PORT_SIZE_16 \| \
	156	CSPR_MSEL_NOR \| \
	157	CSPR_V)
	158	#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024)
	159
	160	/* NOR Flash Timing Params */
	161	#define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) \| \
	162	CSOR_NOR_TRHZ_80)
	163	#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) \| \
	164	FTIM0_NOR_TEADC(0x5) \| \
	165	FTIM0_NOR_TAVDS(0x0) \| \
	166	FTIM0_NOR_TEAHC(0x5))
	167	#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) \| \
	168	FTIM1_NOR_TRAD_NOR(0x1A) \| \
	169	FTIM1_NOR_TSEQRAD_NOR(0x13))
	170	#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) \| \
	171	FTIM2_NOR_TCH(0x4) \| \
	172	FTIM2_NOR_TWP(0x1c) \| \
	173	FTIM2_NOR_TWPH(0x0e))
	174	#define CONFIG_SYS_NOR_FTIM3 0
	175
	176	#define CONFIG_FLASH_CFI_DRIVER
	177	#define CONFIG_SYS_FLASH_CFI
	178	#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
	179	#define CONFIG_SYS_FLASH_QUIET_TEST
	180	#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
	181
	182	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
	183	#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
	184	#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
	185	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
	186
	187	#define CONFIG_SYS_FLASH_EMPTY_INFO
	188	#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS }
	189
	190	#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
272c5265	191	#define CONFIG_SYS_WRITE_SWAPPED_DATA
d612f0ab	192	#endif
c8a7d9da WH	193
	194	/* CPLD */
	195
	196	#define CONFIG_SYS_CPLD_BASE 0x7fb00000
	197	#define CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE
	198
	199	#define CONFIG_SYS_FPGA_CSPR_EXT (0x0)
	200	#define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) \| \
	201	CSPR_PORT_SIZE_8 \| \
	202	CSPR_MSEL_GPCM \| \
	203	CSPR_V)
	204	#define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024)
	205	#define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) \| \
	206	CSOR_NOR_NOR_MODE_AVD_NOR \| \
	207	CSOR_NOR_TRHZ_80)
	208
	209	/* CPLD Timing parameters for IFC GPCM */
	210	#define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xf) \| \
	211	FTIM0_GPCM_TEADC(0xf) \| \
	212	FTIM0_GPCM_TEAHC(0xf))
	213	#define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0xff) \| \
	214	FTIM1_GPCM_TRAD(0x3f))
	215	#define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0xf) \| \
	216	FTIM2_GPCM_TCH(0xf) \| \
	217	FTIM2_GPCM_TWP(0xff))
	218	#define CONFIG_SYS_FPGA_FTIM3 0x0
	219	#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
	220	#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
	221	#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
	222	#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
	223	#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
	224	#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
	225	#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
	226	#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
	227	#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_FPGA_CSPR_EXT
	228	#define CONFIG_SYS_CSPR1 CONFIG_SYS_FPGA_CSPR
	229	#define CONFIG_SYS_AMASK1 CONFIG_SYS_FPGA_AMASK
	230	#define CONFIG_SYS_CSOR1 CONFIG_SYS_FPGA_CSOR
	231	#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_FPGA_FTIM0
	232	#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_FPGA_FTIM1
	233	#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_FPGA_FTIM2
	234	#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_FPGA_FTIM3
	235
	236	/*
	237	* Serial Port
	238	*/
55d53ab4	239	#ifdef CONFIG_LPUART
55d53ab4 AW	240	#define CONFIG_LPUART_32B_REG
55d53ab4 AW	241	#else
c8a7d9da	242	#define CONFIG_CONS_INDEX 1
c8a7d9da	243	#define CONFIG_SYS_NS16550_SERIAL
f833cd62	244	#ifndef CONFIG_DM_SERIAL
c8a7d9da	245	#define CONFIG_SYS_NS16550_REG_SIZE 1
f833cd62	246	#endif
c8a7d9da	247	#define CONFIG_SYS_NS16550_CLK get_serial_clock()
55d53ab4	248	#endif
c8a7d9da	249
c8a7d9da WH	250	/*
	251	* I2C
	252	*/
c8a7d9da WH	253	#define CONFIG_SYS_I2C
c8a7d9da WH	254	#define CONFIG_SYS_I2C_MXC
03544c66 AA	255	#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
03544c66 AA	256	#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
f8cb101e	257	#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
c8a7d9da	258
5175a288	259	/* EEPROM */
5175a288 AW	260	#define CONFIG_ID_EEPROM
	261	#define CONFIG_SYS_I2C_EEPROM_NXID
	262	#define CONFIG_SYS_EEPROM_BUS_NUM 1
	263	#define CONFIG_SYS_I2C_EEPROM_ADDR 0x53
	264	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
	265	#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
	266	#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
5175a288	267
c8a7d9da WH	268	/*
	269	* MMC
	270	*/
c8a7d9da	271	#define CONFIG_FSL_ESDHC
c8a7d9da	272
9dd3d3c0	273	/* SPI */
947cee11	274	#if defined(CONFIG_QSPI_BOOT) \|\| defined(CONFIG_SD_BOOT_QSPI)
9dd3d3c0	275	/* QSPI */
d612f0ab AW	276	#define QSPI0_AMBA_BASE 0x40000000
	277	#define FSL_QSPI_FLASH_SIZE (1 << 24)
	278	#define FSL_QSPI_FLASH_NUM 2
	279
03d1d568	280	/* DSPI */
03d1d568 YY	281	#endif
03d1d568 YY	282
9dd3d3c0 HW	283	/* DM SPI */
9dd3d3c0 HW	284	#if defined(CONFIG_FSL_DSPI) \|\| defined(CONFIG_FSL_QSPI)
9dd3d3c0 HW	285	#define CONFIG_DM_SPI_FLASH
9dd3d3c0 HW	286	#endif
d612f0ab	287
b4ecc8c6 WH	288	/*
	289	* Video
	290	*/
b215fb3f	291	#ifdef CONFIG_VIDEO_FSL_DCU_FB
b4ecc8c6 WH	292	#define CONFIG_VIDEO_LOGO
	293	#define CONFIG_VIDEO_BMP_LOGO
	294
	295	#define CONFIG_FSL_DCU_SII9022A
	296	#define CONFIG_SYS_I2C_DVI_BUS_NUM 1
	297	#define CONFIG_SYS_I2C_DVI_ADDR 0x39
	298	#endif
	299
c8a7d9da WH	300	/*
	301	* eTSEC
	302	*/
	303	#define CONFIG_TSEC_ENET
	304
	305	#ifdef CONFIG_TSEC_ENET
	306	#define CONFIG_MII
	307	#define CONFIG_MII_DEFAULT_TSEC 1
	308	#define CONFIG_TSEC1 1
	309	#define CONFIG_TSEC1_NAME "eTSEC1"
	310	#define CONFIG_TSEC2 1
	311	#define CONFIG_TSEC2_NAME "eTSEC2"
	312	#define CONFIG_TSEC3 1
	313	#define CONFIG_TSEC3_NAME "eTSEC3"
	314
	315	#define TSEC1_PHY_ADDR 2
	316	#define TSEC2_PHY_ADDR 0
	317	#define TSEC3_PHY_ADDR 1
	318
	319	#define TSEC1_FLAGS (TSEC_GIGABIT \| TSEC_REDUCED)
	320	#define TSEC2_FLAGS (TSEC_GIGABIT \| TSEC_REDUCED)
	321	#define TSEC3_FLAGS (TSEC_GIGABIT \| TSEC_REDUCED)
	322
	323	#define TSEC1_PHYIDX 0
	324	#define TSEC2_PHYIDX 0
	325	#define TSEC3_PHYIDX 0
	326
	327	#define CONFIG_ETHPRIME "eTSEC1"
	328
c8a7d9da WH	329	#define CONFIG_PHY_ATHEROS
	330
	331	#define CONFIG_HAS_ETH0
	332	#define CONFIG_HAS_ETH1
	333	#define CONFIG_HAS_ETH2
	334	#endif
	335
da419027	336	/* PCIe */
b38eaec5 RD	337	#define CONFIG_PCIE1 /* PCIE controller 1 */
b38eaec5 RD	338	#define CONFIG_PCIE2 /* PCIE controller 2 */
da419027	339
180b8688	340	#ifdef CONFIG_PCI
180b8688	341	#define CONFIG_PCI_SCAN_SHOW
180b8688 ML	342	#endif
180b8688 ML	343
c8a7d9da	344	#define CONFIG_CMDLINE_TAG
8415bb68	345
1a2826f6	346	#define CONFIG_PEN_ADDR_BIG_ENDIAN
435acd83	347	#define CONFIG_LAYERSCAPE_NS_ACCESS
1a2826f6	348	#define CONFIG_SMP_PEN_ADDR 0x01ee0200
e4916e85	349	#define COUNTER_FREQUENCY 12500000
1a2826f6	350
c8a7d9da	351	#define CONFIG_HWCONFIG
03c22449 ZZ	352	#define HWCONFIG_BUFFER_SIZE 256
	353
	354	#define CONFIG_FSL_DEVICE_DISABLE
c8a7d9da	355
a65d7408 AW	356	#include <config_distro_defaults.h>
	357	#define BOOT_TARGET_DEVICES(func) \
	358	func(MMC, mmc, 0) \
	359	func(USB, usb, 0)
	360	#include <config_distro_bootcmd.h>
c8a7d9da	361
55d53ab4 AW	362	#ifdef CONFIG_LPUART
	363	#define CONFIG_EXTRA_ENV_SETTINGS \
	364	"bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0" \
7ff7166c	365	"initrd_high=0xffffffff\0" \
a65d7408 AW	366	"fdt_high=0xffffffff\0" \
	367	"fdt_addr=0x64f00000\0" \
	368	"kernel_addr=0x65000000\0" \
	369	"scriptaddr=0x80000000\0" \
b8ae6798	370	"scripthdraddr=0x80080000\0" \
a65d7408 AW	371	"fdtheader_addr_r=0x80100000\0" \
	372	"kernelheader_addr_r=0x80200000\0" \
	373	"kernel_addr_r=0x81000000\0" \
	374	"fdt_addr_r=0x90000000\0" \
	375	"ramdisk_addr_r=0xa0000000\0" \
	376	"load_addr=0xa0000000\0" \
	377	"kernel_size=0x2800000\0" \
397a173e SL	378	"kernel_addr_sd=0x8000\0" \
397a173e SL	379	"kernel_size_sd=0x14000\0" \
a65d7408 AW	380	BOOTENV \
a65d7408 AW	381	"boot_scripts=ls1021atwr_boot.scr\0" \
b8ae6798	382	"boot_script_hdr=hdr_ls1021atwr_bs.out\0" \
a65d7408 AW	383	"scan_dev_for_boot_part=" \
	384	"part list ${devtype} ${devnum} devplist; " \
	385	"env exists devplist \|\| setenv devplist 1; " \
	386	"for distro_bootpart in ${devplist}; do " \
	387	"if fstype ${devtype} " \
	388	"${devnum}:${distro_bootpart} " \
	389	"bootfstype; then " \
	390	"run scan_dev_for_boot; " \
	391	"fi; " \
	392	"done\0" \
b8ae6798 SG	393	"scan_dev_for_boot=" \
	394	"echo Scanning ${devtype} " \
	395	"${devnum}:${distro_bootpart}...; " \
	396	"for prefix in ${boot_prefixes}; do " \
	397	"run scan_dev_for_scripts; " \
	398	"done;" \
	399	"\0" \
	400	"boot_a_script=" \
	401	"load ${devtype} ${devnum}:${distro_bootpart} " \
	402	"${scriptaddr} ${prefix}${script}; " \
	403	"env exists secureboot && load ${devtype} " \
	404	"${devnum}:${distro_bootpart} " \
	405	"${scripthdraddr} ${prefix}${boot_script_hdr} " \
	406	"&& esbc_validate ${scripthdraddr};" \
	407	"source ${scriptaddr}\0" \
a65d7408 AW	408	"installer=load mmc 0:2 $load_addr " \
	409	"/flex_installer_arm32.itb; " \
	410	"bootm $load_addr#ls1021atwr\0" \
	411	"qspi_bootcmd=echo Trying load from qspi..;" \
	412	"sf probe && sf read $load_addr " \
	413	"$kernel_addr $kernel_size && bootm $load_addr#$board\0" \
	414	"nor_bootcmd=echo Trying load from nor..;" \
	415	"cp.b $kernel_addr $load_addr " \
	416	"$kernel_size && bootm $load_addr#$board\0"
55d53ab4	417	#else
c8a7d9da WH	418	#define CONFIG_EXTRA_ENV_SETTINGS \
c8a7d9da WH	419	"bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \
7ff7166c	420	"initrd_high=0xffffffff\0" \
a65d7408 AW	421	"fdt_high=0xffffffff\0" \
a65d7408 AW	422	"fdt_addr=0x64f00000\0" \
9b457cc6 VPB	423	"kernel_addr=0x61000000\0" \
9b457cc6 VPB	424	"kernelheader_addr=0x60800000\0" \
a65d7408	425	"scriptaddr=0x80000000\0" \
b8ae6798	426	"scripthdraddr=0x80080000\0" \
a65d7408 AW	427	"fdtheader_addr_r=0x80100000\0" \
	428	"kernelheader_addr_r=0x80200000\0" \
	429	"kernel_addr_r=0x81000000\0" \
9b457cc6	430	"kernelheader_size=0x40000\0" \
a65d7408 AW	431	"fdt_addr_r=0x90000000\0" \
	432	"ramdisk_addr_r=0xa0000000\0" \
	433	"load_addr=0xa0000000\0" \
	434	"kernel_size=0x2800000\0" \
9b457cc6 VPB	435	"kernel_addr_sd=0x8000\0" \
	436	"kernel_size_sd=0x14000\0" \
	437	"kernelhdr_addr_sd=0x4000\0" \
	438	"kernelhdr_size_sd=0x10\0" \
a65d7408 AW	439	BOOTENV \
a65d7408 AW	440	"boot_scripts=ls1021atwr_boot.scr\0" \
b8ae6798	441	"boot_script_hdr=hdr_ls1021atwr_bs.out\0" \
a65d7408 AW	442	"scan_dev_for_boot_part=" \
	443	"part list ${devtype} ${devnum} devplist; " \
	444	"env exists devplist \|\| setenv devplist 1; " \
	445	"for distro_bootpart in ${devplist}; do " \
	446	"if fstype ${devtype} " \
	447	"${devnum}:${distro_bootpart} " \
	448	"bootfstype; then " \
	449	"run scan_dev_for_boot; " \
	450	"fi; " \
	451	"done\0" \
b8ae6798 SG	452	"scan_dev_for_boot=" \
	453	"echo Scanning ${devtype} " \
	454	"${devnum}:${distro_bootpart}...; " \
	455	"for prefix in ${boot_prefixes}; do " \
	456	"run scan_dev_for_scripts; " \
	457	"done;" \
	458	"\0" \
	459	"boot_a_script=" \
	460	"load ${devtype} ${devnum}:${distro_bootpart} " \
	461	"${scriptaddr} ${prefix}${script}; " \
	462	"env exists secureboot && load ${devtype} " \
	463	"${devnum}:${distro_bootpart} " \
	464	"${scripthdraddr} ${prefix}${boot_script_hdr} " \
	465	"&& esbc_validate ${scripthdraddr};" \
	466	"source ${scriptaddr}\0" \
a65d7408 AW	467	"qspi_bootcmd=echo Trying load from qspi..;" \
a65d7408 AW	468	"sf probe && sf read $load_addr " \
9b457cc6 VPB	469	"$kernel_addr $kernel_size; env exists secureboot " \
	470	"&& sf read $kernelheader_addr_r $kernelheader_addr " \
	471	"$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
	472	"bootm $load_addr#$board\0" \
a65d7408 AW	473	"nor_bootcmd=echo Trying load from nor..;" \
a65d7408 AW	474	"cp.b $kernel_addr $load_addr " \
9b457cc6 VPB	475	"$kernel_size; env exists secureboot " \
	476	"&& cp.b $kernelheader_addr $kernelheader_addr_r " \
	477	"$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
	478	"bootm $load_addr#$board\0" \
397a173e SL	479	"sd_bootcmd=echo Trying load from SD ..;" \
	480	"mmcinfo && mmc read $load_addr " \
	481	"$kernel_addr_sd $kernel_size_sd && " \
9b457cc6 VPB	482	"env exists secureboot && mmc read $kernelheader_addr_r " \
	483	"$kernelhdr_addr_sd $kernelhdr_size_sd " \
	484	" && esbc_validate ${kernelheader_addr_r};" \
397a173e	485	"bootm $load_addr#$board\0"
55d53ab4	486	#endif
c8a7d9da	487
a65d7408 AW	488	#undef CONFIG_BOOTCOMMAND
a65d7408 AW	489	#if defined(CONFIG_QSPI_BOOT) \|\| defined(CONFIG_SD_BOOT_QSPI)
9b457cc6 VPB	490	#define CONFIG_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd" \
9b457cc6 VPB	491	"env exists secureboot && esbc_halt"
397a173e	492	#elif defined(CONFIG_SD_BOOT)
9b457cc6 VPB	493	#define CONFIG_BOOTCOMMAND "run distro_bootcmd; run sd_bootcmd; " \
9b457cc6 VPB	494	"env exists secureboot && esbc_halt;"
a65d7408	495	#else
9b457cc6 VPB	496	#define CONFIG_BOOTCOMMAND "run distro_bootcmd; run nor_bootcmd;" \
9b457cc6 VPB	497	"env exists secureboot && esbc_halt;"
a65d7408 AW	498	#endif
a65d7408 AW	499
c8a7d9da WH	500	/*
	501	* Miscellaneous configurable options
	502	*/
	503	#define CONFIG_SYS_LONGHELP /* undef to save memory */
c8a7d9da	504	#define CONFIG_AUTO_COMPLETE
c8a7d9da	505
c8a7d9da WH	506	#define CONFIG_SYS_MEMTEST_START 0x80000000
	507	#define CONFIG_SYS_MEMTEST_END 0x9fffffff
	508
	509	#define CONFIG_SYS_LOAD_ADDR 0x82000000
c8a7d9da	510
660673af XL	511	#define CONFIG_LS102XA_STREAM_ID
660673af XL	512
c8a7d9da WH	513	#define CONFIG_SYS_INIT_SP_OFFSET \
	514	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
	515	#define CONFIG_SYS_INIT_SP_ADDR \
	516	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
	517
8415bb68 AW	518	#ifdef CONFIG_SPL_BUILD
	519	#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
	520	#else
c8a7d9da	521	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
8415bb68	522	#endif
c8a7d9da	523
615bfce5	524	#define CONFIG_SYS_QE_FW_ADDR 0x60940000
eaa859e7	525
c8a7d9da WH	526	/*
	527	* Environment
	528	*/
	529	#define CONFIG_ENV_OVERWRITE
	530
8415bb68	531	#if defined(CONFIG_SD_BOOT)
615bfce5	532	#define CONFIG_ENV_OFFSET 0x300000
8415bb68 AW	533	#define CONFIG_SYS_MMC_ENV_DEV 0
8415bb68 AW	534	#define CONFIG_ENV_SIZE 0x20000
d612f0ab	535	#elif defined(CONFIG_QSPI_BOOT)
d612f0ab	536	#define CONFIG_ENV_SIZE 0x2000
615bfce5	537	#define CONFIG_ENV_OFFSET 0x300000
d612f0ab	538	#define CONFIG_ENV_SECT_SIZE 0x10000
8415bb68	539	#else
615bfce5	540	#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x300000)
c8a7d9da WH	541	#define CONFIG_ENV_SIZE 0x20000
c8a7d9da WH	542	#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
8415bb68	543	#endif
c8a7d9da	544
4ba4a095 RG	545	#define CONFIG_MISC_INIT_R
4ba4a095 RG	546
ef6c55a2	547	#include <asm/fsl_secure_boot.h>
cc7b8b9a	548	#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
4ba4a095	549
c8a7d9da	550	#endif