[people/ms/u-boot.git] / include / configs / ls1021atwr.h

/*
 * Copyright 2014 Freescale Semiconductor, Inc.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __CONFIG_H
#define __CONFIG_H

#define CONFIG_LS102XA

#define CONFIG_ARMV7_PSCI_1_0

#define CONFIG_ARMV7_SECURE_BASE	OCRAM_BASE_S_ADDR

#define CONFIG_SYS_FSL_CLK

#define CONFIG_SKIP_LOWLEVEL_INIT
#define CONFIG_DEEP_SLEEP

/*
 * Size of malloc() pool
 */
#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 16 * 1024 * 1024)

#define CONFIG_SYS_INIT_RAM_ADDR	OCRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE	OCRAM_SIZE

/*
 * USB
 */

/*
 * EHCI Support - disbaled by default as
 * there is no signal coming out of soc on
 * this board for this controller. However,
 * the silicon still has this controller,
 * and anyone can use this controller by
 * taking signals out on their board.
 */

/*#define CONFIG_HAS_FSL_DR_USB*/

#ifdef CONFIG_HAS_FSL_DR_USB
#define CONFIG_USB_EHCI
#define CONFIG_USB_EHCI_FSL
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
#endif

/* XHCI Support - enabled by default */
#define CONFIG_HAS_FSL_XHCI_USB

#ifdef CONFIG_HAS_FSL_XHCI_USB
#define CONFIG_USB_XHCI_FSL
#define CONFIG_USB_MAX_CONTROLLER_COUNT        1
#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS     2
#endif

#define CONFIG_SYS_CLK_FREQ		100000000
#define CONFIG_DDR_CLK_FREQ		100000000

#define DDR_SDRAM_CFG			0x470c0008
#define DDR_CS0_BNDS			0x008000bf
#define DDR_CS0_CONFIG			0x80014302
#define DDR_TIMING_CFG_0		0x50550004
#define DDR_TIMING_CFG_1		0xbcb38c56
#define DDR_TIMING_CFG_2		0x0040d120
#define DDR_TIMING_CFG_3		0x010e1000
#define DDR_TIMING_CFG_4		0x00000001
#define DDR_TIMING_CFG_5		0x03401400
#define DDR_SDRAM_CFG_2			0x00401010
#define DDR_SDRAM_MODE			0x00061c60
#define DDR_SDRAM_MODE_2		0x00180000
#define DDR_SDRAM_INTERVAL		0x18600618
#define DDR_DDR_WRLVL_CNTL		0x8655f605
#define DDR_DDR_WRLVL_CNTL_2		0x05060607
#define DDR_DDR_WRLVL_CNTL_3		0x05050505
#define DDR_DDR_CDR1			0x80040000
#define DDR_DDR_CDR2			0x00000001
#define DDR_SDRAM_CLK_CNTL		0x02000000
#define DDR_DDR_ZQ_CNTL			0x89080600
#define DDR_CS0_CONFIG_2		0
#define DDR_SDRAM_CFG_MEM_EN		0x80000000
#define SDRAM_CFG2_D_INIT		0x00000010
#define DDR_CDR2_VREF_TRAIN_EN		0x00000080
#define SDRAM_CFG2_FRC_SR		0x80000000
#define SDRAM_CFG_BI			0x00000001

#ifdef CONFIG_RAMBOOT_PBL
#define CONFIG_SYS_FSL_PBL_PBI	board/freescale/ls1021atwr/ls102xa_pbi.cfg
#endif

#ifdef CONFIG_SD_BOOT
#ifdef CONFIG_SD_BOOT_QSPI
#define CONFIG_SYS_FSL_PBL_RCW	\
	board/freescale/ls1021atwr/ls102xa_rcw_sd_qspi.cfg
#else
#define CONFIG_SYS_FSL_PBL_RCW	\
	board/freescale/ls1021atwr/ls102xa_rcw_sd_ifc.cfg
#endif
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_LDSCRIPT	"arch/$(ARCH)/cpu/u-boot-spl.lds"

#ifdef CONFIG_SECURE_BOOT
/*
 * HDR would be appended at end of image and copied to DDR along
 * with U-Boot image.
 */
#define CONFIG_U_BOOT_HDR_SIZE				(16 << 10)
#endif /* ifdef CONFIG_SECURE_BOOT */

#define CONFIG_SPL_TEXT_BASE		0x10000000
#define CONFIG_SPL_MAX_SIZE		0x1a000
#define CONFIG_SPL_STACK		0x1001d000
#define CONFIG_SPL_PAD_TO		0x1c000
#define CONFIG_SYS_TEXT_BASE		0x82000000

#define CONFIG_SYS_SPL_MALLOC_START	(CONFIG_SYS_TEXT_BASE + \
		CONFIG_SYS_MONITOR_LEN)
#define CONFIG_SYS_SPL_MALLOC_SIZE	0x100000
#define CONFIG_SPL_BSS_START_ADDR	0x80100000
#define CONFIG_SPL_BSS_MAX_SIZE		0x80000

#ifdef CONFIG_U_BOOT_HDR_SIZE
/*
 * HDR would be appended at end of image and copied to DDR along
 * with U-Boot image. Here u-boot max. size is 512K. So if binary
 * size increases then increase this size in case of secure boot as
 * it uses raw u-boot image instead of fit image.
 */
#define CONFIG_SYS_MONITOR_LEN		(0x100000 + CONFIG_U_BOOT_HDR_SIZE)
#else
#define CONFIG_SYS_MONITOR_LEN		0x100000
#endif /* ifdef CONFIG_U_BOOT_HDR_SIZE */
#endif

#ifdef CONFIG_QSPI_BOOT
#define CONFIG_SYS_TEXT_BASE		0x40010000
#endif

#ifndef CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_TEXT_BASE		0x60100000
#endif

#define CONFIG_NR_DRAM_BANKS		1
#define PHYS_SDRAM			0x80000000
#define PHYS_SDRAM_SIZE			(1u * 1024 * 1024 * 1024)

#define CONFIG_SYS_DDR_SDRAM_BASE      0x80000000UL
#define CONFIG_SYS_SDRAM_BASE          CONFIG_SYS_DDR_SDRAM_BASE

#if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \
	!defined(CONFIG_QSPI_BOOT)
#define CONFIG_U_QE
#endif

/*
 * IFC Definitions
 */
#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
#define CONFIG_FSL_IFC
#define CONFIG_SYS_FLASH_BASE		0x60000000
#define CONFIG_SYS_FLASH_BASE_PHYS	CONFIG_SYS_FLASH_BASE

#define CONFIG_SYS_NOR0_CSPR_EXT	(0x0)
#define CONFIG_SYS_NOR0_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
				CSPR_PORT_SIZE_16 | \
				CSPR_MSEL_NOR | \
				CSPR_V)
#define CONFIG_SYS_NOR_AMASK		IFC_AMASK(128 * 1024 * 1024)

/* NOR Flash Timing Params */
#define CONFIG_SYS_NOR_CSOR		(CSOR_NOR_ADM_SHIFT(4) | \
					CSOR_NOR_TRHZ_80)
#define CONFIG_SYS_NOR_FTIM0		(FTIM0_NOR_TACSE(0x4) | \
					FTIM0_NOR_TEADC(0x5) | \
					FTIM0_NOR_TAVDS(0x0) | \
					FTIM0_NOR_TEAHC(0x5))
#define CONFIG_SYS_NOR_FTIM1		(FTIM1_NOR_TACO(0x35) | \
					FTIM1_NOR_TRAD_NOR(0x1A) | \
					FTIM1_NOR_TSEQRAD_NOR(0x13))
#define CONFIG_SYS_NOR_FTIM2		(FTIM2_NOR_TCS(0x4) | \
					FTIM2_NOR_TCH(0x4) | \
					FTIM2_NOR_TWP(0x1c) | \
					FTIM2_NOR_TWPH(0x0e))
#define CONFIG_SYS_NOR_FTIM3		0

#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
#define CONFIG_SYS_FLASH_QUIET_TEST
#define CONFIG_FLASH_SHOW_PROGRESS	45	/* count down from 45/5: 9..1 */

#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* number of banks */
#define CONFIG_SYS_MAX_FLASH_SECT	1024	/* sectors per device */
#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */

#define CONFIG_SYS_FLASH_EMPTY_INFO
#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE_PHYS }

#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
#define CONFIG_SYS_WRITE_SWAPPED_DATA
#endif

/* CPLD */

#define CONFIG_SYS_CPLD_BASE	0x7fb00000
#define CPLD_BASE_PHYS		CONFIG_SYS_CPLD_BASE

#define CONFIG_SYS_FPGA_CSPR_EXT        (0x0)
#define CONFIG_SYS_FPGA_CSPR		(CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \
					CSPR_PORT_SIZE_8 | \
					CSPR_MSEL_GPCM | \
					CSPR_V)
#define CONFIG_SYS_FPGA_AMASK		IFC_AMASK(64 * 1024)
#define CONFIG_SYS_FPGA_CSOR		(CSOR_NOR_ADM_SHIFT(4) | \
					CSOR_NOR_NOR_MODE_AVD_NOR | \
					CSOR_NOR_TRHZ_80)

/* CPLD Timing parameters for IFC GPCM */
#define CONFIG_SYS_FPGA_FTIM0		(FTIM0_GPCM_TACSE(0xf) | \
					FTIM0_GPCM_TEADC(0xf) | \
					FTIM0_GPCM_TEAHC(0xf))
#define CONFIG_SYS_FPGA_FTIM1		(FTIM1_GPCM_TACO(0xff) | \
					FTIM1_GPCM_TRAD(0x3f))
#define CONFIG_SYS_FPGA_FTIM2		(FTIM2_GPCM_TCS(0xf) | \
					FTIM2_GPCM_TCH(0xf) | \
					FTIM2_GPCM_TWP(0xff))
#define CONFIG_SYS_FPGA_FTIM3           0x0
#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NOR0_CSPR_EXT
#define CONFIG_SYS_CSPR0		CONFIG_SYS_NOR0_CSPR
#define CONFIG_SYS_AMASK0		CONFIG_SYS_NOR_AMASK
#define CONFIG_SYS_CSOR0		CONFIG_SYS_NOR_CSOR
#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NOR_FTIM0
#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NOR_FTIM1
#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NOR_FTIM2
#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NOR_FTIM3
#define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_FPGA_CSPR_EXT
#define CONFIG_SYS_CSPR1		CONFIG_SYS_FPGA_CSPR
#define CONFIG_SYS_AMASK1		CONFIG_SYS_FPGA_AMASK
#define CONFIG_SYS_CSOR1		CONFIG_SYS_FPGA_CSOR
#define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_FPGA_FTIM0
#define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_FPGA_FTIM1
#define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_FPGA_FTIM2
#define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_FPGA_FTIM3

/*
 * Serial Port
 */
#ifdef CONFIG_LPUART
#define CONFIG_LPUART_32B_REG
#else
#define CONFIG_CONS_INDEX		1
#define CONFIG_SYS_NS16550_SERIAL
#ifndef CONFIG_DM_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	1
#endif
#define CONFIG_SYS_NS16550_CLK		get_serial_clock()
#endif

/*
 * I2C
 */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_MXC
#define CONFIG_SYS_I2C_MXC_I2C1		/* enable I2C bus 1 */
#define CONFIG_SYS_I2C_MXC_I2C2		/* enable I2C bus 2 */
#define CONFIG_SYS_I2C_MXC_I2C3		/* enable I2C bus 3 */

/* EEPROM */
#define CONFIG_ID_EEPROM
#define CONFIG_SYS_I2C_EEPROM_NXID
#define CONFIG_SYS_EEPROM_BUS_NUM		1
#define CONFIG_SYS_I2C_EEPROM_ADDR		0x53
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	3
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	5

/*
 * MMC
 */
#define CONFIG_FSL_ESDHC

/* SPI */
#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
/* QSPI */
#define QSPI0_AMBA_BASE			0x40000000
#define FSL_QSPI_FLASH_SIZE		(1 << 24)
#define FSL_QSPI_FLASH_NUM		2

/* DSPI */
#endif

/* DM SPI */
#if defined(CONFIG_FSL_DSPI) || defined(CONFIG_FSL_QSPI)
#define CONFIG_DM_SPI_FLASH
#endif

/*
 * Video
 */
#ifdef CONFIG_VIDEO_FSL_DCU_FB
#define CONFIG_CMD_BMP
#define CONFIG_VIDEO_LOGO
#define CONFIG_VIDEO_BMP_LOGO

#define CONFIG_FSL_DCU_SII9022A
#define CONFIG_SYS_I2C_DVI_BUS_NUM	1
#define CONFIG_SYS_I2C_DVI_ADDR		0x39
#endif

/*
 * eTSEC
 */
#define CONFIG_TSEC_ENET

#ifdef CONFIG_TSEC_ENET
#define CONFIG_MII
#define CONFIG_MII_DEFAULT_TSEC		1
#define CONFIG_TSEC1			1
#define CONFIG_TSEC1_NAME		"eTSEC1"
#define CONFIG_TSEC2			1
#define CONFIG_TSEC2_NAME		"eTSEC2"
#define CONFIG_TSEC3			1
#define CONFIG_TSEC3_NAME		"eTSEC3"

#define TSEC1_PHY_ADDR			2
#define TSEC2_PHY_ADDR			0
#define TSEC3_PHY_ADDR			1

#define TSEC1_FLAGS			(TSEC_GIGABIT | TSEC_REDUCED)
#define TSEC2_FLAGS			(TSEC_GIGABIT | TSEC_REDUCED)
#define TSEC3_FLAGS			(TSEC_GIGABIT | TSEC_REDUCED)

#define TSEC1_PHYIDX			0
#define TSEC2_PHYIDX			0
#define TSEC3_PHYIDX			0

#define CONFIG_ETHPRIME			"eTSEC1"

#define CONFIG_PHY_GIGE
#define CONFIG_PHYLIB
#define CONFIG_PHY_ATHEROS

#define CONFIG_HAS_ETH0
#define CONFIG_HAS_ETH1
#define CONFIG_HAS_ETH2
#endif

/* PCIe */
#define CONFIG_PCIE1		/* PCIE controller 1 */
#define CONFIG_PCIE2		/* PCIE controller 2 */

#ifdef CONFIG_PCI
#define CONFIG_PCI_SCAN_SHOW
#define CONFIG_CMD_PCI
#endif

#define CONFIG_CMDLINE_TAG
#define CONFIG_CMDLINE_EDITING

#define CONFIG_PEN_ADDR_BIG_ENDIAN
#define CONFIG_LAYERSCAPE_NS_ACCESS
#define CONFIG_SMP_PEN_ADDR		0x01ee0200
#define COUNTER_FREQUENCY		12500000

#define CONFIG_HWCONFIG
#define HWCONFIG_BUFFER_SIZE		256

#define CONFIG_FSL_DEVICE_DISABLE


#ifdef CONFIG_LPUART
#define CONFIG_EXTRA_ENV_SETTINGS       \
	"bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0" \
	"initrd_high=0xffffffff\0"      \
	"fdt_high=0xffffffff\0"
#else
#define CONFIG_EXTRA_ENV_SETTINGS	\
	"bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \
	"initrd_high=0xffffffff\0"      \
	"fdt_high=0xffffffff\0"
#endif

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP		/* undef to save memory */
#define CONFIG_AUTO_COMPLETE
#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size */
#define CONFIG_SYS_PBSIZE		\
		(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_MAXARGS		16	/* max number of command args */
#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE

#define CONFIG_SYS_MEMTEST_START	0x80000000
#define CONFIG_SYS_MEMTEST_END		0x9fffffff

#define CONFIG_SYS_LOAD_ADDR		0x82000000

#define CONFIG_LS102XA_STREAM_ID

#define CONFIG_SYS_INIT_SP_OFFSET \
	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_ADDR \
	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)

#ifdef CONFIG_SPL_BUILD
#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
#else
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
#endif

#define CONFIG_SYS_QE_FW_ADDR     0x600c0000

/*
 * Environment
 */
#define CONFIG_ENV_OVERWRITE

#if defined(CONFIG_SD_BOOT)
#define CONFIG_ENV_OFFSET		0x100000
#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_MMC_ENV_DEV		0
#define CONFIG_ENV_SIZE			0x20000
#elif defined(CONFIG_QSPI_BOOT)
#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_SIZE			0x2000
#define CONFIG_ENV_OFFSET		0x100000
#define CONFIG_ENV_SECT_SIZE		0x10000
#else
#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_SIZE			0x20000
#define CONFIG_ENV_SECT_SIZE		0x20000 /* 128K (one sector) */
#endif

#define CONFIG_MISC_INIT_R

/* Hash command with SHA acceleration supported in hardware */
#ifdef CONFIG_FSL_CAAM
#define CONFIG_CMD_HASH
#define CONFIG_SHA_HW_ACCEL
#endif

#include <asm/fsl_secure_boot.h>
#define CONFIG_SYS_BOOTM_LEN	(64 << 20) /* Increase max gunzip size */

#endif
Commit	Line	Data
c8a7d9da WH	1	/*
	2	* Copyright 2014 Freescale Semiconductor, Inc.
	3	*
	4	* SPDX-License-Identifier: GPL-2.0+
	5	*/
	6
	7	#ifndef __CONFIG_H
	8	#define __CONFIG_H
	9
c8a7d9da WH	10	#define CONFIG_LS102XA
c8a7d9da WH	11
aeb901f2	12	#define CONFIG_ARMV7_PSCI_1_0
340848b1	13
3288628a HZ	14	#define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR
3288628a HZ	15
18fb0e3c	16	#define CONFIG_SYS_FSL_CLK
c8a7d9da	17
c8a7d9da	18	#define CONFIG_SKIP_LOWLEVEL_INIT
99e1bd42	19	#define CONFIG_DEEP_SLEEP
c8a7d9da WH	20
	21	/*
	22	* Size of malloc() pool
	23	*/
	24	#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024 * 1024)
	25
	26	#define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR
	27	#define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE
	28
10a28644 RM	29	/*
	30	* USB
	31	*/
	32
	33	/*
	34	* EHCI Support - disbaled by default as
	35	* there is no signal coming out of soc on
	36	* this board for this controller. However,
	37	* the silicon still has this controller,
	38	* and anyone can use this controller by
	39	* taking signals out on their board.
	40	*/
	41
	42	/#define CONFIG_HAS_FSL_DR_USB/
	43
	44	#ifdef CONFIG_HAS_FSL_DR_USB
	45	#define CONFIG_USB_EHCI
	46	#define CONFIG_USB_EHCI_FSL
	47	#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
	48	#endif
	49
	50	/* XHCI Support - enabled by default */
	51	#define CONFIG_HAS_FSL_XHCI_USB
	52
	53	#ifdef CONFIG_HAS_FSL_XHCI_USB
	54	#define CONFIG_USB_XHCI_FSL
10a28644 RM	55	#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
	56	#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
	57	#endif
	58
c8a7d9da WH	59	#define CONFIG_SYS_CLK_FREQ 100000000
	60	#define CONFIG_DDR_CLK_FREQ 100000000
	61
a88cc3bd YS	62	#define DDR_SDRAM_CFG 0x470c0008
	63	#define DDR_CS0_BNDS 0x008000bf
	64	#define DDR_CS0_CONFIG 0x80014302
	65	#define DDR_TIMING_CFG_0 0x50550004
	66	#define DDR_TIMING_CFG_1 0xbcb38c56
	67	#define DDR_TIMING_CFG_2 0x0040d120
	68	#define DDR_TIMING_CFG_3 0x010e1000
	69	#define DDR_TIMING_CFG_4 0x00000001
	70	#define DDR_TIMING_CFG_5 0x03401400
	71	#define DDR_SDRAM_CFG_2 0x00401010
	72	#define DDR_SDRAM_MODE 0x00061c60
	73	#define DDR_SDRAM_MODE_2 0x00180000
	74	#define DDR_SDRAM_INTERVAL 0x18600618
	75	#define DDR_DDR_WRLVL_CNTL 0x8655f605
	76	#define DDR_DDR_WRLVL_CNTL_2 0x05060607
	77	#define DDR_DDR_WRLVL_CNTL_3 0x05050505
	78	#define DDR_DDR_CDR1 0x80040000
	79	#define DDR_DDR_CDR2 0x00000001
	80	#define DDR_SDRAM_CLK_CNTL 0x02000000
	81	#define DDR_DDR_ZQ_CNTL 0x89080600
	82	#define DDR_CS0_CONFIG_2 0
	83	#define DDR_SDRAM_CFG_MEM_EN 0x80000000
99e1bd42 TY	84	#define SDRAM_CFG2_D_INIT 0x00000010
	85	#define DDR_CDR2_VREF_TRAIN_EN 0x00000080
	86	#define SDRAM_CFG2_FRC_SR 0x80000000
	87	#define SDRAM_CFG_BI 0x00000001
a88cc3bd	88
8415bb68 AW	89	#ifdef CONFIG_RAMBOOT_PBL
	90	#define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1021atwr/ls102xa_pbi.cfg
	91	#endif
	92
	93	#ifdef CONFIG_SD_BOOT
947cee11 AW	94	#ifdef CONFIG_SD_BOOT_QSPI
	95	#define CONFIG_SYS_FSL_PBL_RCW \
	96	board/freescale/ls1021atwr/ls102xa_rcw_sd_qspi.cfg
	97	#else
	98	#define CONFIG_SYS_FSL_PBL_RCW \
	99	board/freescale/ls1021atwr/ls102xa_rcw_sd_ifc.cfg
	100	#endif
8415bb68 AW	101	#define CONFIG_SPL_FRAMEWORK
8415bb68 AW	102	#define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds"
e7e720c2 SG	103
e7e720c2 SG	104	#ifdef CONFIG_SECURE_BOOT
e7e720c2 SG	105	/*
	106	* HDR would be appended at end of image and copied to DDR along
	107	* with U-Boot image.
	108	*/
693d4c9f	109	#define CONFIG_U_BOOT_HDR_SIZE (16 << 10)
e7e720c2	110	#endif /* ifdef CONFIG_SECURE_BOOT */
8415bb68 AW	111
	112	#define CONFIG_SPL_TEXT_BASE 0x10000000
	113	#define CONFIG_SPL_MAX_SIZE 0x1a000
	114	#define CONFIG_SPL_STACK 0x1001d000
	115	#define CONFIG_SPL_PAD_TO 0x1c000
	116	#define CONFIG_SYS_TEXT_BASE 0x82000000
	117
99e1bd42 TY	118	#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE + \
99e1bd42 TY	119	CONFIG_SYS_MONITOR_LEN)
8415bb68 AW	120	#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
	121	#define CONFIG_SPL_BSS_START_ADDR 0x80100000
	122	#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
e7e720c2 SG	123
	124	#ifdef CONFIG_U_BOOT_HDR_SIZE
	125	/*
	126	* HDR would be appended at end of image and copied to DDR along
	127	* with U-Boot image. Here u-boot max. size is 512K. So if binary
	128	* size increases then increase this size in case of secure boot as
	129	* it uses raw u-boot image instead of fit image.
	130	*/
9b6639fa	131	#define CONFIG_SYS_MONITOR_LEN (0x100000 + CONFIG_U_BOOT_HDR_SIZE)
e7e720c2	132	#else
9b6639fa	133	#define CONFIG_SYS_MONITOR_LEN 0x100000
e7e720c2	134	#endif /* ifdef CONFIG_U_BOOT_HDR_SIZE */
8415bb68 AW	135	#endif
8415bb68 AW	136
d612f0ab AW	137	#ifdef CONFIG_QSPI_BOOT
d612f0ab AW	138	#define CONFIG_SYS_TEXT_BASE 0x40010000
947cee11 AW	139	#endif
947cee11 AW	140
c8a7d9da	141	#ifndef CONFIG_SYS_TEXT_BASE
1c69a51c	142	#define CONFIG_SYS_TEXT_BASE 0x60100000
c8a7d9da WH	143	#endif
	144
	145	#define CONFIG_NR_DRAM_BANKS 1
	146	#define PHYS_SDRAM 0x80000000
	147	#define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024)
	148
	149	#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
	150	#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
	151
4c59ab9c AW	152	#if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \
4c59ab9c AW	153	!defined(CONFIG_QSPI_BOOT)
eaa859e7 ZQ	154	#define CONFIG_U_QE
	155	#endif
	156
c8a7d9da WH	157	/*
	158	* IFC Definitions
	159	*/
947cee11	160	#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
c8a7d9da WH	161	#define CONFIG_FSL_IFC
	162	#define CONFIG_SYS_FLASH_BASE 0x60000000
	163	#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
	164
	165	#define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
	166	#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \| \
	167	CSPR_PORT_SIZE_16 \| \
	168	CSPR_MSEL_NOR \| \
	169	CSPR_V)
	170	#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024)
	171
	172	/* NOR Flash Timing Params */
	173	#define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) \| \
	174	CSOR_NOR_TRHZ_80)
	175	#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) \| \
	176	FTIM0_NOR_TEADC(0x5) \| \
	177	FTIM0_NOR_TAVDS(0x0) \| \
	178	FTIM0_NOR_TEAHC(0x5))
	179	#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) \| \
	180	FTIM1_NOR_TRAD_NOR(0x1A) \| \
	181	FTIM1_NOR_TSEQRAD_NOR(0x13))
	182	#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) \| \
	183	FTIM2_NOR_TCH(0x4) \| \
	184	FTIM2_NOR_TWP(0x1c) \| \
	185	FTIM2_NOR_TWPH(0x0e))
	186	#define CONFIG_SYS_NOR_FTIM3 0
	187
	188	#define CONFIG_FLASH_CFI_DRIVER
	189	#define CONFIG_SYS_FLASH_CFI
	190	#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
	191	#define CONFIG_SYS_FLASH_QUIET_TEST
	192	#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
	193
	194	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
	195	#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
	196	#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
	197	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
	198
	199	#define CONFIG_SYS_FLASH_EMPTY_INFO
	200	#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS }
	201
	202	#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
272c5265	203	#define CONFIG_SYS_WRITE_SWAPPED_DATA
d612f0ab	204	#endif
c8a7d9da WH	205
	206	/* CPLD */
	207
	208	#define CONFIG_SYS_CPLD_BASE 0x7fb00000
	209	#define CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE
	210
	211	#define CONFIG_SYS_FPGA_CSPR_EXT (0x0)
	212	#define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) \| \
	213	CSPR_PORT_SIZE_8 \| \
	214	CSPR_MSEL_GPCM \| \
	215	CSPR_V)
	216	#define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024)
	217	#define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) \| \
	218	CSOR_NOR_NOR_MODE_AVD_NOR \| \
	219	CSOR_NOR_TRHZ_80)
	220
	221	/* CPLD Timing parameters for IFC GPCM */
	222	#define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xf) \| \
	223	FTIM0_GPCM_TEADC(0xf) \| \
	224	FTIM0_GPCM_TEAHC(0xf))
	225	#define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0xff) \| \
	226	FTIM1_GPCM_TRAD(0x3f))
	227	#define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0xf) \| \
	228	FTIM2_GPCM_TCH(0xf) \| \
	229	FTIM2_GPCM_TWP(0xff))
	230	#define CONFIG_SYS_FPGA_FTIM3 0x0
	231	#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
	232	#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
	233	#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
	234	#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
	235	#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
	236	#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
	237	#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
	238	#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
	239	#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_FPGA_CSPR_EXT
	240	#define CONFIG_SYS_CSPR1 CONFIG_SYS_FPGA_CSPR
	241	#define CONFIG_SYS_AMASK1 CONFIG_SYS_FPGA_AMASK
	242	#define CONFIG_SYS_CSOR1 CONFIG_SYS_FPGA_CSOR
	243	#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_FPGA_FTIM0
	244	#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_FPGA_FTIM1
	245	#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_FPGA_FTIM2
	246	#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_FPGA_FTIM3
	247
	248	/*
	249	* Serial Port
	250	*/
55d53ab4	251	#ifdef CONFIG_LPUART
55d53ab4 AW	252	#define CONFIG_LPUART_32B_REG
55d53ab4 AW	253	#else
c8a7d9da	254	#define CONFIG_CONS_INDEX 1
c8a7d9da	255	#define CONFIG_SYS_NS16550_SERIAL
f833cd62	256	#ifndef CONFIG_DM_SERIAL
c8a7d9da	257	#define CONFIG_SYS_NS16550_REG_SIZE 1
f833cd62	258	#endif
c8a7d9da	259	#define CONFIG_SYS_NS16550_CLK get_serial_clock()
55d53ab4	260	#endif
c8a7d9da	261
c8a7d9da WH	262	/*
	263	* I2C
	264	*/
c8a7d9da WH	265	#define CONFIG_SYS_I2C
c8a7d9da WH	266	#define CONFIG_SYS_I2C_MXC
03544c66 AA	267	#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
03544c66 AA	268	#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
f8cb101e	269	#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
c8a7d9da	270
5175a288	271	/* EEPROM */
5175a288 AW	272	#define CONFIG_ID_EEPROM
	273	#define CONFIG_SYS_I2C_EEPROM_NXID
	274	#define CONFIG_SYS_EEPROM_BUS_NUM 1
	275	#define CONFIG_SYS_I2C_EEPROM_ADDR 0x53
	276	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
	277	#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
	278	#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
5175a288	279
c8a7d9da WH	280	/*
	281	* MMC
	282	*/
c8a7d9da	283	#define CONFIG_FSL_ESDHC
c8a7d9da	284
9dd3d3c0	285	/* SPI */
947cee11	286	#if defined(CONFIG_QSPI_BOOT) \|\| defined(CONFIG_SD_BOOT_QSPI)
9dd3d3c0	287	/* QSPI */
d612f0ab AW	288	#define QSPI0_AMBA_BASE 0x40000000
	289	#define FSL_QSPI_FLASH_SIZE (1 << 24)
	290	#define FSL_QSPI_FLASH_NUM 2
	291
03d1d568	292	/* DSPI */
03d1d568 YY	293	#endif
03d1d568 YY	294
9dd3d3c0 HW	295	/* DM SPI */
9dd3d3c0 HW	296	#if defined(CONFIG_FSL_DSPI) \|\| defined(CONFIG_FSL_QSPI)
9dd3d3c0 HW	297	#define CONFIG_DM_SPI_FLASH
9dd3d3c0 HW	298	#endif
d612f0ab	299
b4ecc8c6 WH	300	/*
	301	* Video
	302	*/
b215fb3f	303	#ifdef CONFIG_VIDEO_FSL_DCU_FB
b4ecc8c6	304	#define CONFIG_CMD_BMP
b4ecc8c6 WH	305	#define CONFIG_VIDEO_LOGO
	306	#define CONFIG_VIDEO_BMP_LOGO
	307
	308	#define CONFIG_FSL_DCU_SII9022A
	309	#define CONFIG_SYS_I2C_DVI_BUS_NUM 1
	310	#define CONFIG_SYS_I2C_DVI_ADDR 0x39
	311	#endif
	312
c8a7d9da WH	313	/*
	314	* eTSEC
	315	*/
	316	#define CONFIG_TSEC_ENET
	317
	318	#ifdef CONFIG_TSEC_ENET
	319	#define CONFIG_MII
	320	#define CONFIG_MII_DEFAULT_TSEC 1
	321	#define CONFIG_TSEC1 1
	322	#define CONFIG_TSEC1_NAME "eTSEC1"
	323	#define CONFIG_TSEC2 1
	324	#define CONFIG_TSEC2_NAME "eTSEC2"
	325	#define CONFIG_TSEC3 1
	326	#define CONFIG_TSEC3_NAME "eTSEC3"
	327
	328	#define TSEC1_PHY_ADDR 2
	329	#define TSEC2_PHY_ADDR 0
	330	#define TSEC3_PHY_ADDR 1
	331
	332	#define TSEC1_FLAGS (TSEC_GIGABIT \| TSEC_REDUCED)
	333	#define TSEC2_FLAGS (TSEC_GIGABIT \| TSEC_REDUCED)
	334	#define TSEC3_FLAGS (TSEC_GIGABIT \| TSEC_REDUCED)
	335
	336	#define TSEC1_PHYIDX 0
	337	#define TSEC2_PHYIDX 0
	338	#define TSEC3_PHYIDX 0
	339
	340	#define CONFIG_ETHPRIME "eTSEC1"
	341
	342	#define CONFIG_PHY_GIGE
	343	#define CONFIG_PHYLIB
	344	#define CONFIG_PHY_ATHEROS
	345
	346	#define CONFIG_HAS_ETH0
	347	#define CONFIG_HAS_ETH1
	348	#define CONFIG_HAS_ETH2
	349	#endif
	350
da419027	351	/* PCIe */
b38eaec5 RD	352	#define CONFIG_PCIE1 /* PCIE controller 1 */
b38eaec5 RD	353	#define CONFIG_PCIE2 /* PCIE controller 2 */
da419027	354
180b8688	355	#ifdef CONFIG_PCI
180b8688 ML	356	#define CONFIG_PCI_SCAN_SHOW
180b8688 ML	357	#define CONFIG_CMD_PCI
180b8688 ML	358	#endif
180b8688 ML	359
c8a7d9da WH	360	#define CONFIG_CMDLINE_TAG
c8a7d9da WH	361	#define CONFIG_CMDLINE_EDITING
8415bb68	362
1a2826f6	363	#define CONFIG_PEN_ADDR_BIG_ENDIAN
435acd83	364	#define CONFIG_LAYERSCAPE_NS_ACCESS
1a2826f6	365	#define CONFIG_SMP_PEN_ADDR 0x01ee0200
e4916e85	366	#define COUNTER_FREQUENCY 12500000
1a2826f6	367
c8a7d9da	368	#define CONFIG_HWCONFIG
03c22449 ZZ	369	#define HWCONFIG_BUFFER_SIZE 256
	370
	371	#define CONFIG_FSL_DEVICE_DISABLE
c8a7d9da	372
c8a7d9da	373
55d53ab4 AW	374	#ifdef CONFIG_LPUART
	375	#define CONFIG_EXTRA_ENV_SETTINGS \
	376	"bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0" \
7ff7166c AW	377	"initrd_high=0xffffffff\0" \
7ff7166c AW	378	"fdt_high=0xffffffff\0"
55d53ab4	379	#else
c8a7d9da WH	380	#define CONFIG_EXTRA_ENV_SETTINGS \
c8a7d9da WH	381	"bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \
7ff7166c AW	382	"initrd_high=0xffffffff\0" \
7ff7166c AW	383	"fdt_high=0xffffffff\0"
55d53ab4	384	#endif
c8a7d9da WH	385
	386	/*
	387	* Miscellaneous configurable options
	388	*/
	389	#define CONFIG_SYS_LONGHELP /* undef to save memory */
c8a7d9da WH	390	#define CONFIG_AUTO_COMPLETE
	391	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
	392	#define CONFIG_SYS_PBSIZE \
	393	(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
	394	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	395	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
	396
c8a7d9da WH	397	#define CONFIG_SYS_MEMTEST_START 0x80000000
	398	#define CONFIG_SYS_MEMTEST_END 0x9fffffff
	399
	400	#define CONFIG_SYS_LOAD_ADDR 0x82000000
c8a7d9da	401
660673af XL	402	#define CONFIG_LS102XA_STREAM_ID
660673af XL	403
c8a7d9da WH	404	#define CONFIG_SYS_INIT_SP_OFFSET \
	405	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
	406	#define CONFIG_SYS_INIT_SP_ADDR \
	407	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
	408
8415bb68 AW	409	#ifdef CONFIG_SPL_BUILD
	410	#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
	411	#else
c8a7d9da	412	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
8415bb68	413	#endif
c8a7d9da	414
713bf94f	415	#define CONFIG_SYS_QE_FW_ADDR 0x600c0000
eaa859e7	416
c8a7d9da WH	417	/*
	418	* Environment
	419	*/
	420	#define CONFIG_ENV_OVERWRITE
	421
8415bb68 AW	422	#if defined(CONFIG_SD_BOOT)
	423	#define CONFIG_ENV_OFFSET 0x100000
	424	#define CONFIG_ENV_IS_IN_MMC
	425	#define CONFIG_SYS_MMC_ENV_DEV 0
	426	#define CONFIG_ENV_SIZE 0x20000
d612f0ab AW	427	#elif defined(CONFIG_QSPI_BOOT)
	428	#define CONFIG_ENV_IS_IN_SPI_FLASH
	429	#define CONFIG_ENV_SIZE 0x2000
	430	#define CONFIG_ENV_OFFSET 0x100000
	431	#define CONFIG_ENV_SECT_SIZE 0x10000
8415bb68	432	#else
c8a7d9da WH	433	#define CONFIG_ENV_IS_IN_FLASH
	434	#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
	435	#define CONFIG_ENV_SIZE 0x20000
	436	#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
8415bb68	437	#endif
c8a7d9da	438
4ba4a095 RG	439	#define CONFIG_MISC_INIT_R
	440
	441	/* Hash command with SHA acceleration supported in hardware */
ef6c55a2	442	#ifdef CONFIG_FSL_CAAM
4ba4a095 RG	443	#define CONFIG_CMD_HASH
4ba4a095 RG	444	#define CONFIG_SHA_HW_ACCEL
ef6c55a2 AB	445	#endif
	446
	447	#include <asm/fsl_secure_boot.h>
cc7b8b9a	448	#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
4ba4a095	449
c8a7d9da	450	#endif