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Commit | Line | Data |
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8a3f6bb6 | 1 | /* |
dc7a9e64 EBS |
2 | * Common configuration settings for IGEP technology based boards |
3 | * | |
4 | * (C) Copyright 2012 | |
8a3f6bb6 EBS |
5 | * ISEE 2007 SL, <www.iseebcn.com> |
6 | * | |
3765b3e7 | 7 | * SPDX-License-Identifier: GPL-2.0+ |
8a3f6bb6 EBS |
8 | */ |
9 | ||
dc7a9e64 EBS |
10 | #ifndef __IGEP00X0_H |
11 | #define __IGEP00X0_H | |
12 | ||
e37e954e EBS |
13 | #ifdef CONFIG_BOOT_NAND |
14 | #define CONFIG_NAND | |
15 | #endif | |
8a3f6bb6 | 16 | |
e37e954e | 17 | #define CONFIG_NR_DRAM_BANKS 2 |
8a3f6bb6 | 18 | |
e37e954e | 19 | #include <configs/ti_omap3_common.h> |
aa127df6 | 20 | #include <asm/mach-types.h> |
8a3f6bb6 EBS |
21 | |
22 | /* | |
23 | * Display CPU and Board information | |
24 | */ | |
25 | #define CONFIG_DISPLAY_CPUINFO 1 | |
26 | #define CONFIG_DISPLAY_BOARDINFO 1 | |
27 | ||
8a3f6bb6 EBS |
28 | #define CONFIG_MISC_INIT_R |
29 | ||
8a3f6bb6 EBS |
30 | #define CONFIG_REVISION_TAG 1 |
31 | ||
50bb94c9 EBS |
32 | /* Status LED available for IGEP0020 and IGEP0030 but not IGEP0032 */ |
33 | #if (CONFIG_MACH_TYPE != MACH_TYPE_IGEP0032) | |
f3b4bc45 EBS |
34 | #define CONFIG_STATUS_LED |
35 | #define CONFIG_BOARD_SPECIFIC_LED | |
36 | #define CONFIG_GPIO_LED | |
37 | #if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0020) | |
38 | #define RED_LED_GPIO 27 | |
50bb94c9 | 39 | #elif (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0030) |
f3b4bc45 | 40 | #define RED_LED_GPIO 16 |
50bb94c9 EBS |
41 | #else |
42 | #error "status LED not defined for this machine." | |
d9aacf41 | 43 | #endif |
f3b4bc45 EBS |
44 | #define RED_LED_DEV 0 |
45 | #define STATUS_LED_BIT RED_LED_GPIO | |
46 | #define STATUS_LED_STATE STATUS_LED_ON | |
47 | #define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2) | |
48 | #define STATUS_LED_BOOT RED_LED_DEV | |
50bb94c9 | 49 | #endif |
9d4f5421 | 50 | |
dd1e8583 EBS |
51 | /* GPIO banks */ |
52 | #define CONFIG_OMAP3_GPIO_3 /* GPIO64 .. 95 is in GPIO bank 3 */ | |
53 | #define CONFIG_OMAP3_GPIO_5 /* GPIO128..159 is in GPIO bank 5 */ | |
54 | #define CONFIG_OMAP3_GPIO_6 /* GPIO160..191 is in GPIO bank 6 */ | |
55 | ||
8a3f6bb6 EBS |
56 | /* USB */ |
57 | #define CONFIG_MUSB_UDC 1 | |
58 | #define CONFIG_USB_OMAP3 1 | |
59 | #define CONFIG_TWL4030_USB 1 | |
60 | ||
61 | /* USB device configuration */ | |
62 | #define CONFIG_USB_DEVICE 1 | |
63 | #define CONFIG_USB_TTY 1 | |
64 | #define CONFIG_SYS_CONSOLE_IS_IN_ENV 1 | |
65 | ||
66 | /* Change these to suit your needs */ | |
67 | #define CONFIG_USBD_VENDORID 0x0451 | |
68 | #define CONFIG_USBD_PRODUCTID 0x5678 | |
69 | #define CONFIG_USBD_MANUFACTURER "Texas Instruments" | |
70 | #define CONFIG_USBD_PRODUCT_NAME "IGEP" | |
71 | ||
8a3f6bb6 | 72 | #define CONFIG_CMD_CACHE |
ca511cfb | 73 | #ifdef CONFIG_BOOT_ONENAND |
8a3f6bb6 | 74 | #define CONFIG_CMD_ONENAND /* ONENAND support */ |
ca511cfb | 75 | #endif |
d9aacf41 EBS |
76 | #if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0020) || \ |
77 | (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0032) | |
8a3f6bb6 | 78 | #define CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */ |
77eea280 | 79 | #endif |
8a3f6bb6 EBS |
80 | #define CONFIG_CMD_DHCP |
81 | #define CONFIG_CMD_PING | |
82 | #define CONFIG_CMD_NFS /* NFS support */ | |
8a3f6bb6 | 83 | |
e37e954e | 84 | /*#undef CONFIG_ENV_IS_NOWHERE*/ |
8a3f6bb6 EBS |
85 | |
86 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
304a46ca EBS |
87 | "usbtty=cdc_acm\0" \ |
88 | "loadaddr=0x82000000\0" \ | |
a2fa28bc JMC |
89 | "dtbaddr=0x81600000\0" \ |
90 | "bootdir=/boot\0" \ | |
91 | "bootfile=zImage\0" \ | |
304a46ca | 92 | "usbtty=cdc_acm\0" \ |
e5e73c17 | 93 | "console=ttyO2,115200n8\0" \ |
f1e445c3 | 94 | "mpurate=auto\0" \ |
304a46ca EBS |
95 | "vram=12M\0" \ |
96 | "dvimode=1024x768MR-16@60\0" \ | |
97 | "defaultdisplay=dvi\0" \ | |
98 | "mmcdev=0\0" \ | |
99 | "mmcroot=/dev/mmcblk0p2 rw\0" \ | |
b4ebeb86 | 100 | "mmcrootfstype=ext4 rootwait\0" \ |
304a46ca EBS |
101 | "nandroot=/dev/mtdblock4 rw\0" \ |
102 | "nandrootfstype=jffs2\0" \ | |
103 | "mmcargs=setenv bootargs console=${console} " \ | |
104 | "mpurate=${mpurate} " \ | |
105 | "vram=${vram} " \ | |
106 | "omapfb.mode=dvi:${dvimode} " \ | |
107 | "omapfb.debug=y " \ | |
108 | "omapdss.def_disp=${defaultdisplay} " \ | |
109 | "root=${mmcroot} " \ | |
110 | "rootfstype=${mmcrootfstype}\0" \ | |
111 | "nandargs=setenv bootargs console=${console} " \ | |
112 | "mpurate=${mpurate} " \ | |
113 | "vram=${vram} " \ | |
114 | "omapfb.mode=dvi:${dvimode} " \ | |
115 | "omapfb.debug=y " \ | |
116 | "omapdss.def_disp=${defaultdisplay} " \ | |
117 | "root=${nandroot} " \ | |
118 | "rootfstype=${nandrootfstype}\0" \ | |
2be6bed0 | 119 | "loadbootenv=load mmc ${mmcdev} ${loadaddr} uEnv.txt\0" \ |
1b8ec016 EBS |
120 | "importbootenv=echo Importing environment from mmc ...; " \ |
121 | "env import -t $loadaddr $filesize\0" \ | |
a2fa28bc JMC |
122 | "loadzimage=load mmc ${mmcdev}:2 ${loadaddr} ${bootdir}/${bootfile}\0" \ |
123 | "loadfdt=load mmc ${mmcdev}:2 ${dtbaddr} ${bootdir}/${dtbfile}\0" \ | |
304a46ca EBS |
124 | "mmcboot=echo Booting from mmc ...; " \ |
125 | "run mmcargs; " \ | |
2be6bed0 | 126 | "bootz ${loadaddr}\0" \ |
a2fa28bc JMC |
127 | "mmcbootfdt=echo Booting with DT from mmc ...; " \ |
128 | "bootz ${loadaddr} - ${dtbaddr}\0" \ | |
304a46ca EBS |
129 | "nandboot=echo Booting from onenand ...; " \ |
130 | "run nandargs; " \ | |
131 | "onenand read ${loadaddr} 280000 400000; " \ | |
2be6bed0 | 132 | "bootz ${loadaddr}\0" \ |
304a46ca EBS |
133 | |
134 | #define CONFIG_BOOTCOMMAND \ | |
66968110 | 135 | "mmc dev ${mmcdev}; if mmc rescan; then " \ |
1b8ec016 EBS |
136 | "echo SD/MMC found on device ${mmcdev};" \ |
137 | "if run loadbootenv; then " \ | |
138 | "run importbootenv;" \ | |
139 | "fi;" \ | |
140 | "if test -n $uenvcmd; then " \ | |
141 | "echo Running uenvcmd ...;" \ | |
142 | "run uenvcmd;" \ | |
143 | "fi;" \ | |
2be6bed0 | 144 | "if run loadzimage; then " \ |
a2fa28bc JMC |
145 | "if test -n $dtbfile; then " \ |
146 | "if run loadfdt; then " \ | |
147 | "run mmcbootfdt;" \ | |
148 | "fi;" \ | |
149 | "fi;" \ | |
1b8ec016 EBS |
150 | "run mmcboot;" \ |
151 | "fi;" \ | |
152 | "fi;" \ | |
153 | "run nandboot;" \ | |
8a3f6bb6 | 154 | |
8a3f6bb6 EBS |
155 | /* |
156 | * FLASH and environment organization | |
157 | */ | |
158 | ||
ca511cfb | 159 | #ifdef CONFIG_BOOT_ONENAND |
8a3f6bb6 EBS |
160 | #define CONFIG_SYS_ONENAND_BASE ONENAND_MAP |
161 | ||
162 | #define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */ | |
163 | ||
164 | #define CONFIG_ENV_IS_IN_ONENAND 1 | |
165 | #define CONFIG_ENV_SIZE (512 << 10) /* Total Size Environment */ | |
166 | #define CONFIG_ENV_ADDR ONENAND_ENV_OFFSET | |
ca511cfb JMC |
167 | #endif |
168 | ||
e37e954e | 169 | #ifdef CONFIG_NAND |
ca511cfb JMC |
170 | #define CONFIG_ENV_OFFSET 0x260000 /* environment starts here */ |
171 | #define CONFIG_ENV_IS_IN_NAND 1 | |
172 | #define CONFIG_ENV_SIZE (512 << 10) /* Total Size Environment */ | |
173 | #define CONFIG_ENV_ADDR NAND_ENV_OFFSET | |
ca511cfb | 174 | #endif |
8a3f6bb6 | 175 | |
8a3f6bb6 EBS |
176 | /* |
177 | * SMSC911x Ethernet | |
178 | */ | |
179 | #if defined(CONFIG_CMD_NET) | |
8a3f6bb6 EBS |
180 | #define CONFIG_SMC911X |
181 | #define CONFIG_SMC911X_32_BIT | |
182 | #define CONFIG_SMC911X_BASE 0x2C000000 | |
183 | #endif /* (CONFIG_CMD_NET) */ | |
184 | ||
e37e954e | 185 | /* OneNAND boot config */ |
d271a611 JMC |
186 | #ifdef CONFIG_BOOT_ONENAND |
187 | #define CONFIG_SPL_ONENAND_SUPPORT | |
d271a611 JMC |
188 | #define CONFIG_SYS_ONENAND_U_BOOT_OFFS 0x80000 |
189 | #define CONFIG_SYS_ONENAND_PAGE_SIZE 2048 | |
190 | #define CONFIG_SPL_ONENAND_LOAD_ADDR 0x80000 | |
191 | #define CONFIG_SPL_ONENAND_LOAD_SIZE \ | |
192 | (512 * 1024 - CONFIG_SPL_ONENAND_LOAD_ADDR) | |
193 | ||
194 | #endif | |
195 | ||
d271a611 | 196 | /* NAND boot config */ |
e37e954e | 197 | #ifdef CONFIG_NAND |
b80a6603 | 198 | #define CONFIG_SYS_NAND_BUSWIDTH_16BIT 16 |
d271a611 JMC |
199 | #define CONFIG_SYS_NAND_5_ADDR_CYCLE |
200 | #define CONFIG_SYS_NAND_PAGE_COUNT 64 | |
201 | #define CONFIG_SYS_NAND_PAGE_SIZE 2048 | |
202 | #define CONFIG_SYS_NAND_OOBSIZE 64 | |
203 | #define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) | |
204 | #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 | |
205 | #define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\ | |
206 | 10, 11, 12, 13} | |
207 | #define CONFIG_SYS_NAND_ECCSIZE 512 | |
208 | #define CONFIG_SYS_NAND_ECCBYTES 3 | |
3f719069 | 209 | #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW |
434f2cfc | 210 | #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 |
211 | /* NAND: SPL falcon mode configs */ | |
212 | #ifdef CONFIG_SPL_OS_BOOT | |
213 | #define CONFIG_CMD_SPL_NAND_OFS 0x240000 | |
214 | #define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x280000 | |
215 | #define CONFIG_CMD_SPL_WRITE_SIZE 0x2000 | |
216 | #endif | |
d271a611 JMC |
217 | #endif |
218 | ||
dc7a9e64 | 219 | #endif /* __IGEP00X0_H */ |