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5894ca00 | 1 | /* |
0e063dff | 2 | * Copyright (C) 2012-2015 Panasonic Corporation |
5894ca00 MY |
3 | * Author: Masahiro Yamada <yamada.m@jp.panasonic.com> |
4 | * | |
5 | * SPDX-License-Identifier: GPL-2.0+ | |
6 | */ | |
7 | ||
8 | /* U-boot - Common settings for UniPhier Family */ | |
9 | ||
10 | #ifndef __CONFIG_UNIPHIER_COMMON_H__ | |
11 | #define __CONFIG_UNIPHIER_COMMON_H__ | |
12 | ||
f5d0b9b2 MY |
13 | #if defined(CONFIG_MACH_PH1_PRO4) |
14 | #define CONFIG_DDR_NUM_CH0 2 | |
15 | #define CONFIG_DDR_NUM_CH1 2 | |
16 | ||
17 | /* Physical start address of SDRAM */ | |
18 | #define CONFIG_SDRAM0_BASE 0x80000000 | |
19 | #define CONFIG_SDRAM0_SIZE 0x20000000 | |
20 | #define CONFIG_SDRAM1_BASE 0xa0000000 | |
21 | #define CONFIG_SDRAM1_SIZE 0x20000000 | |
22 | #endif | |
23 | ||
24 | #if defined(CONFIG_MACH_PH1_LD4) | |
25 | #define CONFIG_DDR_NUM_CH0 1 | |
26 | #define CONFIG_DDR_NUM_CH1 1 | |
27 | ||
28 | /* Physical start address of SDRAM */ | |
29 | #define CONFIG_SDRAM0_BASE 0x80000000 | |
30 | #define CONFIG_SDRAM0_SIZE 0x10000000 | |
31 | #define CONFIG_SDRAM1_BASE 0x90000000 | |
32 | #define CONFIG_SDRAM1_SIZE 0x10000000 | |
33 | #endif | |
34 | ||
35 | #if defined(CONFIG_MACH_PH1_SLD8) | |
36 | #define CONFIG_DDR_NUM_CH0 1 | |
37 | #define CONFIG_DDR_NUM_CH1 1 | |
38 | ||
39 | /* Physical start address of SDRAM */ | |
40 | #define CONFIG_SDRAM0_BASE 0x80000000 | |
41 | #define CONFIG_SDRAM0_SIZE 0x10000000 | |
42 | #define CONFIG_SDRAM1_BASE 0x90000000 | |
43 | #define CONFIG_SDRAM1_SIZE 0x10000000 | |
44 | #endif | |
45 | ||
233e42a9 MY |
46 | #define CONFIG_I2C_EEPROM |
47 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 | |
48 | ||
5894ca00 MY |
49 | /* |
50 | * Support card address map | |
51 | */ | |
52 | #if defined(CONFIG_PFC_MICRO_SUPPORT_CARD) | |
53 | # define CONFIG_SUPPORT_CARD_BASE 0x03f00000 | |
54 | # define CONFIG_SUPPORT_CARD_ETHER_BASE (CONFIG_SUPPORT_CARD_BASE + 0x00000000) | |
55 | # define CONFIG_SUPPORT_CARD_LED_BASE (CONFIG_SUPPORT_CARD_BASE + 0x00090000) | |
56 | # define CONFIG_SUPPORT_CARD_UART_BASE (CONFIG_SUPPORT_CARD_BASE + 0x000b0000) | |
57 | #endif | |
58 | ||
59 | #if defined(CONFIG_DCC_MICRO_SUPPORT_CARD) | |
60 | # define CONFIG_SUPPORT_CARD_BASE 0x08000000 | |
61 | # define CONFIG_SUPPORT_CARD_ETHER_BASE (CONFIG_SUPPORT_CARD_BASE + 0x00000000) | |
62 | # define CONFIG_SUPPORT_CARD_LED_BASE (CONFIG_SUPPORT_CARD_BASE + 0x00401630) | |
63 | # define CONFIG_SUPPORT_CARD_UART_BASE (CONFIG_SUPPORT_CARD_BASE + 0x00200000) | |
64 | #endif | |
65 | ||
d064cbff | 66 | #ifdef CONFIG_SYS_NS16550_SERIAL |
5894ca00 MY |
67 | #define CONFIG_SYS_NS16550 |
68 | #define CONFIG_SYS_NS16550_COM1 CONFIG_SUPPORT_CARD_UART_BASE | |
69 | #define CONFIG_SYS_NS16550_CLK 12288000 | |
70 | #define CONFIG_SYS_NS16550_REG_SIZE -2 | |
d064cbff | 71 | #endif |
5894ca00 | 72 | |
f5d0b9b2 MY |
73 | /* TODO: move to Kconfig and device tree */ |
74 | #if 0 | |
75 | #define CONFIG_SYS_NS16550_SERIAL | |
76 | #endif | |
77 | ||
78 | #define CONFIG_SMC911X | |
79 | ||
5894ca00 MY |
80 | #define CONFIG_SMC911X_BASE CONFIG_SUPPORT_CARD_ETHER_BASE |
81 | #define CONFIG_SMC911X_32_BIT | |
82 | ||
5894ca00 MY |
83 | /*----------------------------------------------------------------------- |
84 | * MMU and Cache Setting | |
85 | *----------------------------------------------------------------------*/ | |
86 | ||
87 | /* Comment out the following to enable L1 cache */ | |
88 | /* #define CONFIG_SYS_ICACHE_OFF */ | |
89 | /* #define CONFIG_SYS_DCACHE_OFF */ | |
90 | ||
53c45d4e MY |
91 | #define CONFIG_SYS_CACHELINE_SIZE 32 |
92 | ||
5894ca00 MY |
93 | /* Comment out the following to enable L2 cache */ |
94 | #define CONFIG_UNIPHIER_L2CACHE_ON | |
95 | ||
96 | #define CONFIG_DISPLAY_CPUINFO | |
97 | #define CONFIG_DISPLAY_BOARDINFO | |
08fda258 | 98 | #define CONFIG_MISC_INIT_F |
84ccd791 | 99 | #define CONFIG_BOARD_EARLY_INIT_F |
7a3620b2 | 100 | #define CONFIG_BOARD_EARLY_INIT_R |
5894ca00 MY |
101 | #define CONFIG_BOARD_LATE_INIT |
102 | ||
103 | #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) | |
104 | ||
105 | #define CONFIG_TIMESTAMP | |
106 | ||
107 | /* FLASH related */ | |
108 | #define CONFIG_MTD_DEVICE | |
109 | ||
110 | /* | |
111 | * uncomment the following to disable FLASH related code. | |
112 | */ | |
113 | /* #define CONFIG_SYS_NO_FLASH */ | |
114 | ||
115 | #define CONFIG_FLASH_CFI_DRIVER | |
116 | #define CONFIG_SYS_FLASH_CFI | |
117 | ||
118 | #define CONFIG_SYS_MAX_FLASH_SECT 256 | |
119 | #define CONFIG_SYS_MONITOR_BASE 0 | |
120 | #define CONFIG_SYS_FLASH_BASE 0 | |
121 | ||
122 | /* | |
123 | * flash_toggle does not work for out supoort card. | |
124 | * We need to use flash_status_poll. | |
125 | */ | |
126 | #define CONFIG_SYS_CFI_FLASH_STATUS_POLL | |
127 | ||
128 | #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ | |
129 | ||
7a3620b2 | 130 | #define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 2 |
5894ca00 MY |
131 | |
132 | /* serial console configuration */ | |
133 | #define CONFIG_BAUDRATE 115200 | |
134 | ||
135 | #define CONFIG_SYS_GENERIC_BOARD | |
136 | ||
137 | #if !defined(CONFIG_SPL_BUILD) | |
138 | #define CONFIG_USE_ARCH_MEMSET | |
139 | #define CONFIG_USE_ARCH_MEMCPY | |
140 | #endif | |
141 | ||
142 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ | |
143 | ||
144 | #define CONFIG_CMDLINE_EDITING /* add command line history */ | |
5894ca00 MY |
145 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
146 | /* Print Buffer Size */ | |
147 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) | |
148 | #define CONFIG_SYS_MAXARGS 16 /* max number of command */ | |
149 | /* Boot Argument Buffer Size */ | |
150 | #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) | |
151 | ||
152 | #define CONFIG_CONS_INDEX 1 | |
153 | ||
154 | /* | |
155 | * For NAND booting the environment is embedded in the U-Boot image. Please take | |
156 | * look at the file board/amcc/canyonlands/u-boot-nand.lds for details. | |
157 | */ | |
158 | /* #define CONFIG_ENV_IS_IN_NAND */ | |
159 | #define CONFIG_ENV_IS_NOWHERE | |
160 | #define CONFIG_ENV_SIZE 0x2000 | |
161 | #define CONFIG_ENV_OFFSET 0x0 | |
162 | /* #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) */ | |
163 | ||
164 | /* Time clock 1MHz */ | |
165 | #define CONFIG_SYS_TIMER_RATE 1000000 | |
166 | ||
167 | /* | |
168 | * By default, ARP timeout is 5 sec. | |
169 | * The first ARP request does not seem to work. | |
170 | * So we need to retry ARP request anyway. | |
171 | * We want to shrink the interval until the second ARP request. | |
172 | */ | |
173 | #define CONFIG_ARP_TIMEOUT 500UL /* 0.5 msec */ | |
174 | ||
5894ca00 MY |
175 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 |
176 | #define CONFIG_SYS_NAND_MAX_CHIPS 2 | |
177 | #define CONFIG_SYS_NAND_ONFI_DETECTION | |
178 | ||
179 | #define CONFIG_NAND_DENALI_ECC_SIZE 1024 | |
180 | ||
181 | #define CONFIG_SYS_NAND_REGS_BASE 0x68100000 | |
182 | #define CONFIG_SYS_NAND_DATA_BASE 0x68000000 | |
183 | ||
184 | #define CONFIG_SYS_NAND_BASE (CONFIG_SYS_NAND_DATA_BASE + 0x10) | |
185 | ||
186 | #define CONFIG_SYS_NAND_USE_FLASH_BBT | |
187 | #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 | |
188 | ||
495deb44 | 189 | /* USB */ |
495deb44 | 190 | #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 |
53c45d4e | 191 | #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 4 |
495deb44 MY |
192 | #define CONFIG_CMD_FAT |
193 | #define CONFIG_FAT_WRITE | |
194 | #define CONFIG_DOS_PARTITION | |
195 | ||
5894ca00 MY |
196 | /* memtest works on */ |
197 | #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE | |
198 | #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x01000000) | |
199 | ||
200 | #define CONFIG_BOOTDELAY 3 | |
201 | #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ | |
202 | #define CONFIG_AUTOBOOT_KEYED 1 | |
203 | #define CONFIG_AUTOBOOT_PROMPT \ | |
204 | "Press SPACE to abort autoboot in %d seconds\n", bootdelay | |
205 | #define CONFIG_AUTOBOOT_DELAY_STR "d" | |
206 | #define CONFIG_AUTOBOOT_STOP_STR " " | |
207 | ||
208 | /* | |
209 | * Network Configuration | |
210 | */ | |
211 | #define CONFIG_ETHADDR 00:21:83:24:00:00 | |
212 | #define CONFIG_SERVERIP 192.168.11.1 | |
213 | #define CONFIG_IPADDR 192.168.11.10 | |
214 | #define CONFIG_GATEWAYIP 192.168.11.1 | |
215 | #define CONFIG_NETMASK 255.255.255.0 | |
216 | ||
217 | #define CONFIG_LOADADDR 0x84000000 | |
218 | #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR | |
219 | #define CONFIG_BOOTFILE "fit.itb" | |
220 | ||
221 | #define CONFIG_CMDLINE_EDITING /* add command line history */ | |
222 | ||
223 | #define CONFIG_BOOTCOMMAND "run $bootmode" | |
224 | ||
225 | #define CONFIG_ROOTPATH "/nfs/root/path" | |
226 | #define CONFIG_NFSBOOTCOMMAND \ | |
227 | "setenv bootargs $bootargs root=/dev/nfs rw " \ | |
228 | "nfsroot=$serverip:$rootpath " \ | |
229 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off;" \ | |
230 | "tftpboot; bootm;" | |
231 | ||
232 | #define CONFIG_BOOTARGS " user_debug=0x1f init=/sbin/init" | |
233 | ||
234 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
235 | "netdev=eth0\0" \ | |
236 | "image_offset=0x00080000\0" \ | |
237 | "image_size=0x00f00000\0" \ | |
238 | "verify=n\0" \ | |
75bc8e85 MY |
239 | "nandupdate=nand erase 0 0x100000 &&" \ |
240 | "tftpboot u-boot-spl.bin &&" \ | |
241 | "nand write $loadaddr 0 0x10000 &&" \ | |
242 | "tftpboot u-boot-dtb.img &&" \ | |
243 | "nand write $loadaddr 0x10000 0xf0000\0" \ | |
0e063dff | 244 | "norboot=run add_default_bootargs &&" \ |
5894ca00 | 245 | "bootm $image_offset\0" \ |
0e063dff MY |
246 | "nandboot=run add_default_bootargs &&" \ |
247 | "nand read $loadaddr $image_offset $image_size &&" \ | |
248 | "bootm\0" \ | |
5894ca00 MY |
249 | "add_default_bootargs=setenv bootargs $bootargs" \ |
250 | " console=ttyS0,$baudrate\0" \ | |
251 | ||
5894ca00 MY |
252 | /* Open Firmware flat tree */ |
253 | #define CONFIG_OF_LIBFDT | |
254 | ||
255 | #define CONFIG_HAVE_ARM_SECURE | |
256 | ||
257 | /* Memory Size & Mapping */ | |
258 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SDRAM0_BASE | |
259 | ||
260 | #if CONFIG_SDRAM0_BASE + CONFIG_SDRAM0_SIZE >= CONFIG_SDRAM1_BASE | |
261 | /* Thre is no memory hole */ | |
262 | #define CONFIG_NR_DRAM_BANKS 1 | |
263 | #define CONFIG_SYS_SDRAM_SIZE (CONFIG_SDRAM0_SIZE + CONFIG_SDRAM1_SIZE) | |
264 | #else | |
265 | #define CONFIG_NR_DRAM_BANKS 2 | |
266 | #define CONFIG_SYS_SDRAM_SIZE (CONFIG_SDRAM0_SIZE) | |
267 | #endif | |
268 | ||
269 | #define CONFIG_SYS_TEXT_BASE 0x84000000 | |
270 | ||
f5d0b9b2 MY |
271 | #if defined(CONFIG_MACH_PH1_LD4) || defined(CONFIG_MACH_PH1_SLD8) |
272 | #define CONFIG_SPL_TEXT_BASE 0x00040000 | |
273 | #endif | |
274 | #if defined(CONFIG_MACH_PH1_PRO4) | |
275 | #define CONFIG_SPL_TEXT_BASE 0x00100000 | |
276 | #endif | |
277 | ||
b67932e3 | 278 | #ifndef CONFIG_SPL_BUILD |
5894ca00 MY |
279 | #define CONFIG_SKIP_LOWLEVEL_INIT |
280 | #endif | |
281 | ||
282 | #define CONFIG_SYS_SPL_MALLOC_START (0x0ff00000) | |
283 | #define CONFIG_SYS_SPL_MALLOC_SIZE (0x00004000) | |
284 | ||
7e421d64 | 285 | #ifdef CONFIG_SPL_BUILD |
5894ca00 | 286 | #define CONFIG_SYS_INIT_SP_ADDR (0x0ff08000) |
7e421d64 MY |
287 | #else |
288 | #define CONFIG_SYS_INIT_SP_ADDR ((CONFIG_SYS_TEXT_BASE) - 0x00001000) | |
289 | #endif | |
5894ca00 MY |
290 | |
291 | #define CONFIG_SPL_FRAMEWORK | |
292 | #define CONFIG_SPL_NAND_SUPPORT | |
293 | ||
294 | #define CONFIG_SPL_LIBCOMMON_SUPPORT /* for mem_malloc_init */ | |
295 | #define CONFIG_SPL_LIBGENERIC_SUPPORT | |
296 | ||
297 | #define CONFIG_SPL_BOARD_INIT | |
298 | ||
299 | #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x10000 | |
300 | ||
301 | #endif /* __CONFIG_UNIPHIER_COMMON_H__ */ |