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[thirdparty/binutils-gdb.git] / opcodes / riscv-opc.c

2023-08-15	Tsukasa OI	RISC-V: Add support for the 'Zihintntl' extension	blob \| commitdiff \| raw
2023-08-15	Jan Beulich	RISC-V: remove indirection from register tables	blob \| commitdiff \| raw \| diff to current
2023-08-11	Tsukasa OI	RISC-V: Fix opcode entries of "vmsge{,u}.vx"	blob \| commitdiff \| raw \| diff to current
2023-08-07	Jan Beulich	RISC-V: move comment describing rules for riscv_opcodes[]	blob \| commitdiff \| raw \| diff to current
2023-08-02	Sam James	Revert "2.41 Release sources"	blob \| commitdiff \| raw \| diff to current
2023-08-02	Nick Clifton	2.41 Release sources binutils-2_41-release	blob \| commitdiff \| raw \| diff to current
2023-07-18	Jiawei	RISC-V: Supports Zcb extension.	blob \| commitdiff \| raw \| diff to current
2023-07-01	Christoph Müllner	RISC-V: Add support for the Zvksh ISA extension	blob \| commitdiff \| raw \| diff to current
2023-07-01	Christoph Müllner	RISC-V: Add support for the Zvksed ISA extension	blob \| commitdiff \| raw \| diff to current
2023-07-01	Christoph Müllner	RISC-V: Add support for the Zvknh[a,b] ISA extensions	blob \| commitdiff \| raw \| diff to current
2023-07-01	Christoph Müllner	RISC-V: Add support for the Zvkned ISA extension	blob \| commitdiff \| raw \| diff to current
2023-07-01	Christoph Müllner	RISC-V: Add support for the Zvkg ISA extension	blob \| commitdiff \| raw \| diff to current
2023-07-01	Nathan Huckleberry	RISC-V: Add support for the Zvbc extension	blob \| commitdiff \| raw \| diff to current
2023-07-01	Christoph Müllner	RISC-V: Add support for the Zvbb ISA extension	blob \| commitdiff \| raw \| diff to current
2023-06-30	Christoph Müllner	RISC-V: Add support for the Zfa extension	blob \| commitdiff \| raw \| diff to current
2023-06-27	Philipp Tomsich	RISC-V: Support Zicond extension	blob \| commitdiff \| raw \| diff to current
2023-06-01	Jim Wilson	RISC-V: PR30449, Add lga assembler macro support.	blob \| commitdiff \| raw \| diff to current
2023-04-26	Philipp Tomsich	RISC-V: Support XVentanaCondOps extension	blob \| commitdiff \| raw \| diff to current
2023-03-31	Tsukasa OI	RISC-V: Allocate "various" operand type	blob \| commitdiff \| raw \| diff to current
2023-01-31	Jan Beulich	RISC-V: make C-extension JAL available again for (32...	blob \| commitdiff \| raw \| diff to current
2023-01-01	Alan Modra	Update year range in copyright notice of binutils files	blob \| commitdiff \| raw \| diff to current
2022-11-17	Christoph Müllner	RISC-V: Add T-Head Int vendor extension	blob \| commitdiff \| raw \| diff to current
2022-11-17	Christoph Müllner	RISC-V: Add T-Head Fmv vendor extension	blob \| commitdiff \| raw \| diff to current
2022-11-09	Christoph Müllner	RISC-V: xtheadfmemidx: Use fp register in mnemonics	blob \| commitdiff \| raw \| diff to current
2022-10-14	Tsukasa OI	RISC-V: Move standard hints before all instructions	blob \| commitdiff \| raw \| diff to current
2022-10-14	Tsukasa OI	RISC-V: Move certain arrays to riscv-opc.c	blob \| commitdiff \| raw \| diff to current
2022-10-04	Nelson Chu	RISC-V: Renamed INSN_CLASS for floating point in intege...	blob \| commitdiff \| raw \| diff to current
2022-10-03	Tsukasa OI	RISC-V: Move supervisor instructions after all unprivil...	blob \| commitdiff \| raw \| diff to current
2022-09-30	Tsukasa OI	RISC-V: Relax "fmv.[sdq]" requirements	blob \| commitdiff \| raw \| diff to current
2022-09-30	Jan Beulich	RISC-V: drop stray INSN_ALIAS flags	blob \| commitdiff \| raw \| diff to current
2022-09-30	Jan Beulich	RISC-V: re-arrange opcode table for consistent alias...	blob \| commitdiff \| raw \| diff to current
2022-09-23	Christoph Müllner	RISC-V: Add Zawrs ISA extension support	blob \| commitdiff \| raw \| diff to current
2022-09-22	Christoph Müllner	RISC-V: Add T-Head MemPair vendor extension	blob \| commitdiff \| raw \| diff to current
2022-09-22	Christoph Müllner	RISC-V: Add T-Head MemIdx vendor extension	blob \| commitdiff \| raw \| diff to current
2022-09-22	Christoph Müllner	RISC-V: Add T-Head FMemIdx vendor extension	blob \| commitdiff \| raw \| diff to current
2022-09-22	Christoph Müllner	RISC-V: Add T-Head MAC vendor extension	blob \| commitdiff \| raw \| diff to current
2022-09-22	Christoph Müllner	RISC-V: Add T-Head CondMov vendor extension	blob \| commitdiff \| raw \| diff to current
2022-09-22	Christoph Müllner	RISC-V: Add T-Head Bitmanip vendor extension	blob \| commitdiff \| raw \| diff to current
2022-09-22	Christoph Müllner	RISC-V: Add T-Head SYNC vendor extension	blob \| commitdiff \| raw \| diff to current
2022-09-22	Christoph Müllner	RISC-V: Add T-Head CMO vendor extension	blob \| commitdiff \| raw \| diff to current
2022-08-30	Tsukasa OI	RISC-V: Add 'Zmmul' extension in assembler.	blob \| commitdiff \| raw \| diff to current
2022-07-07	Tsukasa OI	RISC-V: Added Zfhmin and Zhinxmin.	blob \| commitdiff \| raw \| diff to current
2022-06-22	Nelson Chu	RISC-V: Use single h extension to control hypervisor...	blob \| commitdiff \| raw \| diff to current
2022-05-30	jiawei	RISC-V: Add zhinx extension supports.	blob \| commitdiff \| raw \| diff to current
2022-05-20	Jia-Wei Chen	RISC-V: Update zfinx implement with zicsr.	blob \| commitdiff \| raw \| diff to current
2022-05-20	Tsukasa OI	RISC-V: Remove RV128-only fmv instructions	blob \| commitdiff \| raw \| diff to current
2022-05-17	Nelson Chu	RISC-V: Added half-precision floating-point v1.0 instru...	blob \| commitdiff \| raw \| diff to current
2022-03-29	Jan Beulich	RISC-V: correct FCVT.Q.L[U]	blob \| commitdiff \| raw \| diff to current
2022-03-18	Tsukasa OI	RISC-V: Cache management instructions	blob \| commitdiff \| raw \| diff to current
2022-03-18	Tsukasa OI	RISC-V: Prefetch hint instructions and operand set	blob \| commitdiff \| raw \| diff to current
2022-02-25	Tsukasa OI	RISC-V: Fix mask for some fcvt instructions	blob \| commitdiff \| raw \| diff to current
2022-01-02	Alan Modra	Update year range in copyright notice of binutils files	blob \| commitdiff \| raw \| diff to current
2021-12-24	Vineet Gupta	RISC-V: Hypervisor ext: support Privileged Spec 1.12	blob \| commitdiff \| raw \| diff to current
2021-12-16	Nelson Chu	RISC-V: Support svinval extension with frozen version...	blob \| commitdiff \| raw \| diff to current
2021-11-30	Nelson Chu	RISC-V: Dump vset[i]vli immediate as numbers once vsew...	blob \| commitdiff \| raw \| diff to current
2021-11-18	jiawei	RISC-V: Add instructions and operand set for z[fdq]inx	blob \| commitdiff \| raw \| diff to current
2021-11-17	Nelson Chu	RISC-V: Support rvv extension with released version...	blob \| commitdiff \| raw \| diff to current
2021-11-16	jiawei	RISC-V: Scalar crypto instructions and operand set.	blob \| commitdiff \| raw \| diff to current
2021-10-07	Philipp Tomsich	RISC-V: Support aliases for Zbs instructions	blob \| commitdiff \| raw \| diff to current
2021-10-07	Philipp Tomsich	RISC-V: Add support for Zbs instructions	blob \| commitdiff \| raw \| diff to current
2021-10-07	Philipp Tomsich	RISC-V: Split Zb[abc] into commented sections	blob \| commitdiff \| raw \| diff to current
2021-04-16	Lifang Xia	RISC-V: compress "addi d,CV,z" to "c.mv d,CV"	blob \| commitdiff \| raw \| diff to current
2021-03-16	Kuan-Lin Chen	RISC-V : Support bitmanip-0.93 ZBA/ZBB/ZBC instructions	blob \| commitdiff \| raw \| diff to current
2021-02-19	Nelson Chu	RISC-V: PR27158, fixed UJ/SB types and added CSS/CL...	blob \| commitdiff \| raw \| diff to current
2021-02-18	Nelson Chu	RISC-V: Add bfd/cpu-riscv.h to support all spec version...	blob \| commitdiff \| raw \| diff to current
2021-02-04	Nelson Chu	RISC-V: Removed the v0.93 bitmanip ZBA/ZBB/ZBC instruct...	blob \| commitdiff \| raw \| diff to current
2021-01-15	Nelson Chu	RISC-V: Indent and GNU coding standards tidy, also...	blob \| commitdiff \| raw \| diff to current
2021-01-15	Nelson Chu	RISC-V: Comments tidy and improvement.	blob \| commitdiff \| raw \| diff to current
2021-01-07	Philipp Tomsich	RISC-V: Add pause hint instruction.	blob \| commitdiff \| raw \| diff to current
2021-01-07	Claire Xenia Wolf	RISC-V: Support riscv bitmanip frozen ZBA/ZBB/ZBC instr...	blob \| commitdiff \| raw \| diff to current
2021-01-01	Alan Modra	Update year range in copyright notice of binutils files	blob \| commitdiff \| raw \| diff to current
2020-12-10	Nelson Chu	RISC-V: Add sext.[bh] and zext.[bhw] pseudo instructions.	blob \| commitdiff \| raw \| diff to current
2020-12-10	Nelson Chu	RISC-V: Control fence.i and csr instructions by zifence...	blob \| commitdiff \| raw \| diff to current
2020-12-01	Nelson Chu	RISC-V: Remove the unimplemented extensions.	blob \| commitdiff \| raw \| diff to current
2020-12-01	Nelson Chu	RISC-V: Add zifencei and prefixed h class extensions.	blob \| commitdiff \| raw \| diff to current
2020-06-22	Nelson Chu	RISC-V: Report warning when linking the objects with...	blob \| commitdiff \| raw \| diff to current
2020-06-12	Nelson Chu	RISC-V: Drop the privileged spec v1.9 support.	blob \| commitdiff \| raw \| diff to current
2020-06-03	Nelson Chu	RISC-V: Fix the error when building RISC-V linux native...	blob \| commitdiff \| raw \| diff to current
2020-05-20	Nelson Chu	[PATCH v2 0/9] RISC-V: Support version controling for...	blob \| commitdiff \| raw \| diff to current
2020-02-19	Jim Wilson	RISC-V: Convert the ADD/ADDI to the compressed MV/LI...	blob \| commitdiff \| raw \| diff to current
2020-01-01	Alan Modra	Update year range in copyright notice of binutils files	blob \| commitdiff \| raw \| diff to current
2019-11-13	Jim Wilson	RISC-V: Support the INSN_CLASS.F. classes for .insn...	blob \| commitdiff \| raw \| diff to current
2019-09-18	Jim Wilson	RISC-V: Gate opcode tables by enum rather than string.	blob \| commitdiff \| raw \| diff to current
2019-07-30	Jim Wilson	RISC-V: Fix minor issues with FP csr instructions.	blob \| commitdiff \| raw \| diff to current
2019-07-05	Jim Wilson	Kito's 5-part patch set to improve .insn support.	blob \| commitdiff \| raw \| diff to current
2019-02-08	Jim Wilson	RISC-V: Compress 3-operand beq/bne against x0.	blob \| commitdiff \| raw \| diff to current
2019-01-01	Alan Modra	Update year range in copyright notice of binutils files	blob \| commitdiff \| raw \| diff to current
2018-12-07	Jim Wilson	RISC-V: Fix 4-arg add parsing.	blob \| commitdiff \| raw \| diff to current
2018-11-29	Jim Wilson	RISC-V: Add missing c.unimp instruction.	blob \| commitdiff \| raw \| diff to current
2018-11-27	Jim Wilson	RISC-V: Add .insn CA support.	blob \| commitdiff \| raw \| diff to current
2018-10-02	Palmer Dabbelt	RISC-V: Add fence.tso instruction	blob \| commitdiff \| raw \| diff to current
2018-09-17	Jim Wilson	RISC-V: bge[u] should get higher priority than ble[u].	blob \| commitdiff \| raw \| diff to current
2018-08-31	Jim Wilson	RISC-V: Correct the requirement of compressed floating...	blob \| commitdiff \| raw \| diff to current
2018-08-30	Jim Wilson	RISC-V: Allow instruction require more than one extension	blob \| commitdiff \| raw \| diff to current
2018-07-30	Jim Wilson	RISC-V: Set insn info fields correctly when disassembling.	blob \| commitdiff \| raw \| diff to current
2018-06-20	Sebastian Huber	RISC-V: Accept constant operands in la and lla	blob \| commitdiff \| raw \| diff to current
2018-05-08	Jim Wilson	RISC-V: Add missing hint instructions from RV128I.	blob \| commitdiff \| raw \| diff to current
2018-03-14	Jim Wilson	RISC-V: Add .insn support.	blob \| commitdiff \| raw \| diff to current
2018-01-17	Jim Wilson	RISC-V: Fix bug in prior addi/c.nop patch.	blob \| commitdiff \| raw \| diff to current
2018-01-15	Jim Wilson	RISC-V: Add support for addi that compresses to c.nop.	blob \| commitdiff \| raw \| diff to current
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