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23608e23 JL |
1 | /* |
2 | * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. | |
3 | * | |
1a459660 | 4 | * SPDX-License-Identifier: GPL-2.0+ |
23608e23 JL |
5 | */ |
6 | ||
7 | #include <common.h> | |
5a660169 | 8 | #include <div64.h> |
23608e23 JL |
9 | #include <asm/io.h> |
10 | #include <asm/errno.h> | |
11 | #include <asm/arch/imx-regs.h> | |
6a376046 | 12 | #include <asm/arch/crm_regs.h> |
23608e23 | 13 | #include <asm/arch/clock.h> |
6a376046 | 14 | #include <asm/arch/sys_proto.h> |
23608e23 JL |
15 | |
16 | enum pll_clocks { | |
17 | PLL_SYS, /* System PLL */ | |
18 | PLL_BUS, /* System Bus PLL*/ | |
19 | PLL_USBOTG, /* OTG USB PLL */ | |
20 | PLL_ENET, /* ENET PLL */ | |
21 | }; | |
22 | ||
6a376046 | 23 | struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; |
23608e23 | 24 | |
112fd2ec BT |
25 | #ifdef CONFIG_MXC_OCOTP |
26 | void enable_ocotp_clk(unsigned char enable) | |
27 | { | |
28 | u32 reg; | |
29 | ||
30 | reg = __raw_readl(&imx_ccm->CCGR2); | |
31 | if (enable) | |
32 | reg |= MXC_CCM_CCGR2_OCOTP_CTRL_MASK; | |
33 | else | |
34 | reg &= ~MXC_CCM_CCGR2_OCOTP_CTRL_MASK; | |
35 | __raw_writel(reg, &imx_ccm->CCGR2); | |
36 | } | |
37 | #endif | |
38 | ||
224beb83 NK |
39 | #ifdef CONFIG_NAND_MXS |
40 | void setup_gpmi_io_clk(u32 cfg) | |
41 | { | |
42 | /* Disable clocks per ERR007177 from MX6 errata */ | |
43 | clrbits_le32(&imx_ccm->CCGR4, | |
44 | MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK | | |
45 | MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK | | |
46 | MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK | | |
47 | MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK | | |
48 | MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK); | |
49 | ||
50 | clrbits_le32(&imx_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK); | |
51 | ||
52 | clrsetbits_le32(&imx_ccm->cs2cdr, | |
53 | MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK | | |
54 | MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK | | |
55 | MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK, | |
56 | cfg); | |
57 | ||
58 | setbits_le32(&imx_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK); | |
59 | setbits_le32(&imx_ccm->CCGR4, | |
60 | MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK | | |
61 | MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK | | |
62 | MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK | | |
63 | MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK | | |
64 | MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK); | |
65 | } | |
66 | #endif | |
67 | ||
3f467529 WG |
68 | void enable_usboh3_clk(unsigned char enable) |
69 | { | |
70 | u32 reg; | |
71 | ||
72 | reg = __raw_readl(&imx_ccm->CCGR6); | |
73 | if (enable) | |
0bb7e316 | 74 | reg |= MXC_CCM_CCGR6_USBOH3_MASK; |
3f467529 | 75 | else |
0bb7e316 | 76 | reg &= ~(MXC_CCM_CCGR6_USBOH3_MASK); |
3f467529 WG |
77 | __raw_writel(reg, &imx_ccm->CCGR6); |
78 | ||
79 | } | |
80 | ||
3d8f1798 | 81 | #if defined(CONFIG_FEC_MXC) && !defined(CONFIG_MX6SX) |
224beb83 NK |
82 | void enable_enet_clk(unsigned char enable) |
83 | { | |
84 | u32 mask = MXC_CCM_CCGR1_ENET_CLK_ENABLE_MASK; | |
85 | ||
86 | if (enable) | |
87 | setbits_le32(&imx_ccm->CCGR1, mask); | |
88 | else | |
89 | clrbits_le32(&imx_ccm->CCGR1, mask); | |
90 | } | |
91 | #endif | |
92 | ||
93 | #ifdef CONFIG_MXC_UART | |
94 | void enable_uart_clk(unsigned char enable) | |
95 | { | |
96 | u32 mask = MXC_CCM_CCGR5_UART_MASK | MXC_CCM_CCGR5_UART_SERIAL_MASK; | |
97 | ||
98 | if (enable) | |
99 | setbits_le32(&imx_ccm->CCGR5, mask); | |
100 | else | |
101 | clrbits_le32(&imx_ccm->CCGR5, mask); | |
102 | } | |
103 | #endif | |
104 | ||
224beb83 NK |
105 | #ifdef CONFIG_MMC |
106 | int enable_usdhc_clk(unsigned char enable, unsigned bus_num) | |
107 | { | |
108 | u32 mask; | |
109 | ||
110 | if (bus_num > 3) | |
111 | return -EINVAL; | |
112 | ||
113 | mask = MXC_CCM_CCGR_CG_MASK << (bus_num * 2 + 2); | |
114 | if (enable) | |
115 | setbits_le32(&imx_ccm->CCGR6, mask); | |
116 | else | |
117 | clrbits_le32(&imx_ccm->CCGR6, mask); | |
118 | ||
119 | return 0; | |
120 | } | |
121 | #endif | |
122 | ||
fac96408 | 123 | #ifdef CONFIG_SYS_I2C_MXC |
21a26940 | 124 | /* i2c_num can be from 0 - 3 */ |
cc54a0f7 TK |
125 | int enable_i2c_clk(unsigned char enable, unsigned i2c_num) |
126 | { | |
127 | u32 reg; | |
128 | u32 mask; | |
19c6ec70 | 129 | u32 *addr; |
cc54a0f7 | 130 | |
21a26940 | 131 | if (i2c_num > 3) |
cc54a0f7 | 132 | return -EINVAL; |
21a26940 HS |
133 | if (i2c_num < 3) { |
134 | mask = MXC_CCM_CCGR_CG_MASK | |
135 | << (MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET | |
136 | + (i2c_num << 1)); | |
137 | reg = __raw_readl(&imx_ccm->CCGR2); | |
138 | if (enable) | |
139 | reg |= mask; | |
140 | else | |
141 | reg &= ~mask; | |
142 | __raw_writel(reg, &imx_ccm->CCGR2); | |
143 | } else { | |
19c6ec70 PF |
144 | if (is_cpu_type(MXC_CPU_MX6SX)) { |
145 | mask = MXC_CCM_CCGR6_I2C4_MASK; | |
146 | addr = &imx_ccm->CCGR6; | |
147 | } else { | |
148 | mask = MXC_CCM_CCGR1_I2C4_SERIAL_MASK; | |
149 | addr = &imx_ccm->CCGR1; | |
150 | } | |
151 | reg = __raw_readl(addr); | |
21a26940 HS |
152 | if (enable) |
153 | reg |= mask; | |
154 | else | |
155 | reg &= ~mask; | |
19c6ec70 | 156 | __raw_writel(reg, addr); |
21a26940 | 157 | } |
cc54a0f7 TK |
158 | return 0; |
159 | } | |
160 | #endif | |
161 | ||
a0ae0091 HS |
162 | /* spi_num can be from 0 - SPI_MAX_NUM */ |
163 | int enable_spi_clk(unsigned char enable, unsigned spi_num) | |
164 | { | |
165 | u32 reg; | |
166 | u32 mask; | |
167 | ||
168 | if (spi_num > SPI_MAX_NUM) | |
169 | return -EINVAL; | |
170 | ||
171 | mask = MXC_CCM_CCGR_CG_MASK << (spi_num << 1); | |
172 | reg = __raw_readl(&imx_ccm->CCGR1); | |
173 | if (enable) | |
174 | reg |= mask; | |
175 | else | |
176 | reg &= ~mask; | |
177 | __raw_writel(reg, &imx_ccm->CCGR1); | |
178 | return 0; | |
179 | } | |
23608e23 JL |
180 | static u32 decode_pll(enum pll_clocks pll, u32 infreq) |
181 | { | |
182 | u32 div; | |
183 | ||
184 | switch (pll) { | |
185 | case PLL_SYS: | |
186 | div = __raw_readl(&imx_ccm->analog_pll_sys); | |
187 | div &= BM_ANADIG_PLL_SYS_DIV_SELECT; | |
188 | ||
2eb268f6 | 189 | return (infreq * div) >> 1; |
23608e23 JL |
190 | case PLL_BUS: |
191 | div = __raw_readl(&imx_ccm->analog_pll_528); | |
192 | div &= BM_ANADIG_PLL_528_DIV_SELECT; | |
193 | ||
194 | return infreq * (20 + (div << 1)); | |
195 | case PLL_USBOTG: | |
196 | div = __raw_readl(&imx_ccm->analog_usb1_pll_480_ctrl); | |
197 | div &= BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT; | |
198 | ||
199 | return infreq * (20 + (div << 1)); | |
200 | case PLL_ENET: | |
201 | div = __raw_readl(&imx_ccm->analog_pll_enet); | |
202 | div &= BM_ANADIG_PLL_ENET_DIV_SELECT; | |
203 | ||
89cfd0f5 | 204 | return 25000000 * (div + (div >> 1) + 1); |
23608e23 JL |
205 | default: |
206 | return 0; | |
207 | } | |
208 | /* NOTREACHED */ | |
209 | } | |
762a88cc PA |
210 | static u32 mxc_get_pll_pfd(enum pll_clocks pll, int pfd_num) |
211 | { | |
212 | u32 div; | |
213 | u64 freq; | |
214 | ||
215 | switch (pll) { | |
216 | case PLL_BUS: | |
217 | if (pfd_num == 3) { | |
218 | /* No PFD3 on PPL2 */ | |
219 | return 0; | |
220 | } | |
221 | div = __raw_readl(&imx_ccm->analog_pfd_528); | |
222 | freq = (u64)decode_pll(PLL_BUS, MXC_HCLK); | |
223 | break; | |
224 | case PLL_USBOTG: | |
225 | div = __raw_readl(&imx_ccm->analog_pfd_480); | |
226 | freq = (u64)decode_pll(PLL_USBOTG, MXC_HCLK); | |
227 | break; | |
228 | default: | |
229 | /* No PFD on other PLL */ | |
230 | return 0; | |
231 | } | |
232 | ||
5a660169 | 233 | return lldiv(freq * 18, (div & ANATOP_PFD_FRAC_MASK(pfd_num)) >> |
762a88cc PA |
234 | ANATOP_PFD_FRAC_SHIFT(pfd_num)); |
235 | } | |
23608e23 JL |
236 | |
237 | static u32 get_mcu_main_clk(void) | |
238 | { | |
239 | u32 reg, freq; | |
240 | ||
241 | reg = __raw_readl(&imx_ccm->cacrr); | |
242 | reg &= MXC_CCM_CACRR_ARM_PODF_MASK; | |
243 | reg >>= MXC_CCM_CACRR_ARM_PODF_OFFSET; | |
833b6435 | 244 | freq = decode_pll(PLL_SYS, MXC_HCLK); |
23608e23 JL |
245 | |
246 | return freq / (reg + 1); | |
247 | } | |
248 | ||
6a376046 | 249 | u32 get_periph_clk(void) |
23608e23 JL |
250 | { |
251 | u32 reg, freq = 0; | |
252 | ||
253 | reg = __raw_readl(&imx_ccm->cbcdr); | |
254 | if (reg & MXC_CCM_CBCDR_PERIPH_CLK_SEL) { | |
255 | reg = __raw_readl(&imx_ccm->cbcmr); | |
256 | reg &= MXC_CCM_CBCMR_PERIPH_CLK2_SEL_MASK; | |
257 | reg >>= MXC_CCM_CBCMR_PERIPH_CLK2_SEL_OFFSET; | |
258 | ||
259 | switch (reg) { | |
260 | case 0: | |
833b6435 | 261 | freq = decode_pll(PLL_USBOTG, MXC_HCLK); |
23608e23 JL |
262 | break; |
263 | case 1: | |
264 | case 2: | |
833b6435 | 265 | freq = MXC_HCLK; |
23608e23 JL |
266 | break; |
267 | default: | |
268 | break; | |
269 | } | |
270 | } else { | |
271 | reg = __raw_readl(&imx_ccm->cbcmr); | |
272 | reg &= MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK; | |
273 | reg >>= MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET; | |
274 | ||
275 | switch (reg) { | |
276 | case 0: | |
833b6435 | 277 | freq = decode_pll(PLL_BUS, MXC_HCLK); |
23608e23 JL |
278 | break; |
279 | case 1: | |
762a88cc | 280 | freq = mxc_get_pll_pfd(PLL_BUS, 2); |
23608e23 JL |
281 | break; |
282 | case 2: | |
762a88cc | 283 | freq = mxc_get_pll_pfd(PLL_BUS, 0); |
23608e23 JL |
284 | break; |
285 | case 3: | |
762a88cc PA |
286 | /* static / 2 divider */ |
287 | freq = mxc_get_pll_pfd(PLL_BUS, 2) / 2; | |
23608e23 JL |
288 | break; |
289 | default: | |
290 | break; | |
291 | } | |
292 | } | |
293 | ||
294 | return freq; | |
295 | } | |
296 | ||
23608e23 JL |
297 | static u32 get_ipg_clk(void) |
298 | { | |
299 | u32 reg, ipg_podf; | |
300 | ||
301 | reg = __raw_readl(&imx_ccm->cbcdr); | |
302 | reg &= MXC_CCM_CBCDR_IPG_PODF_MASK; | |
303 | ipg_podf = reg >> MXC_CCM_CBCDR_IPG_PODF_OFFSET; | |
304 | ||
305 | return get_ahb_clk() / (ipg_podf + 1); | |
306 | } | |
307 | ||
308 | static u32 get_ipg_per_clk(void) | |
309 | { | |
310 | u32 reg, perclk_podf; | |
311 | ||
312 | reg = __raw_readl(&imx_ccm->cscmr1); | |
e1c2d68b PF |
313 | if (is_cpu_type(MXC_CPU_MX6SL) || is_cpu_type(MXC_CPU_MX6SX) || |
314 | is_mx6dqp()) { | |
315 | if (reg & MXC_CCM_CSCMR1_PER_CLK_SEL_MASK) | |
316 | return MXC_HCLK; /* OSC 24Mhz */ | |
317 | } | |
318 | ||
23608e23 JL |
319 | perclk_podf = reg & MXC_CCM_CSCMR1_PERCLK_PODF_MASK; |
320 | ||
321 | return get_ipg_clk() / (perclk_podf + 1); | |
322 | } | |
323 | ||
324 | static u32 get_uart_clk(void) | |
325 | { | |
326 | u32 reg, uart_podf; | |
762a88cc | 327 | u32 freq = decode_pll(PLL_USBOTG, MXC_HCLK) / 6; /* static divider */ |
23608e23 | 328 | reg = __raw_readl(&imx_ccm->cscdr1); |
e1c2d68b PF |
329 | |
330 | if (is_cpu_type(MXC_CPU_MX6SL) || is_cpu_type(MXC_CPU_MX6SX) || | |
331 | is_mx6dqp()) { | |
332 | if (reg & MXC_CCM_CSCDR1_UART_CLK_SEL) | |
333 | freq = MXC_HCLK; | |
334 | } | |
335 | ||
23608e23 JL |
336 | reg &= MXC_CCM_CSCDR1_UART_CLK_PODF_MASK; |
337 | uart_podf = reg >> MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET; | |
338 | ||
25b4aa14 | 339 | return freq / (uart_podf + 1); |
23608e23 JL |
340 | } |
341 | ||
342 | static u32 get_cspi_clk(void) | |
343 | { | |
344 | u32 reg, cspi_podf; | |
345 | ||
346 | reg = __raw_readl(&imx_ccm->cscdr2); | |
e1c2d68b PF |
347 | cspi_podf = (reg & MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK) >> |
348 | MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET; | |
349 | ||
350 | if (is_mx6dqp()) { | |
351 | if (reg & MXC_CCM_CSCDR2_ECSPI_CLK_SEL_MASK) | |
352 | return MXC_HCLK / (cspi_podf + 1); | |
353 | } | |
23608e23 | 354 | |
762a88cc | 355 | return decode_pll(PLL_USBOTG, MXC_HCLK) / (8 * (cspi_podf + 1)); |
23608e23 JL |
356 | } |
357 | ||
358 | static u32 get_axi_clk(void) | |
359 | { | |
360 | u32 root_freq, axi_podf; | |
361 | u32 cbcdr = __raw_readl(&imx_ccm->cbcdr); | |
362 | ||
363 | axi_podf = cbcdr & MXC_CCM_CBCDR_AXI_PODF_MASK; | |
364 | axi_podf >>= MXC_CCM_CBCDR_AXI_PODF_OFFSET; | |
365 | ||
366 | if (cbcdr & MXC_CCM_CBCDR_AXI_SEL) { | |
367 | if (cbcdr & MXC_CCM_CBCDR_AXI_ALT_SEL) | |
762a88cc | 368 | root_freq = mxc_get_pll_pfd(PLL_BUS, 2); |
23608e23 | 369 | else |
762a88cc | 370 | root_freq = mxc_get_pll_pfd(PLL_USBOTG, 1); |
23608e23 JL |
371 | } else |
372 | root_freq = get_periph_clk(); | |
373 | ||
374 | return root_freq / (axi_podf + 1); | |
375 | } | |
376 | ||
377 | static u32 get_emi_slow_clk(void) | |
378 | { | |
d55e0dab | 379 | u32 emi_clk_sel, emi_slow_podf, cscmr1, root_freq = 0; |
23608e23 JL |
380 | |
381 | cscmr1 = __raw_readl(&imx_ccm->cscmr1); | |
382 | emi_clk_sel = cscmr1 & MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK; | |
383 | emi_clk_sel >>= MXC_CCM_CSCMR1_ACLK_EMI_SLOW_OFFSET; | |
d55e0dab AG |
384 | emi_slow_podf = cscmr1 & MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK; |
385 | emi_slow_podf >>= MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET; | |
23608e23 JL |
386 | |
387 | switch (emi_clk_sel) { | |
388 | case 0: | |
389 | root_freq = get_axi_clk(); | |
390 | break; | |
391 | case 1: | |
833b6435 | 392 | root_freq = decode_pll(PLL_USBOTG, MXC_HCLK); |
23608e23 JL |
393 | break; |
394 | case 2: | |
762a88cc | 395 | root_freq = mxc_get_pll_pfd(PLL_BUS, 2); |
23608e23 JL |
396 | break; |
397 | case 3: | |
762a88cc | 398 | root_freq = mxc_get_pll_pfd(PLL_BUS, 0); |
23608e23 JL |
399 | break; |
400 | } | |
401 | ||
d55e0dab | 402 | return root_freq / (emi_slow_podf + 1); |
23608e23 JL |
403 | } |
404 | ||
05d54b82 | 405 | #if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX)) |
25b4aa14 FE |
406 | static u32 get_mmdc_ch0_clk(void) |
407 | { | |
408 | u32 cbcmr = __raw_readl(&imx_ccm->cbcmr); | |
409 | u32 cbcdr = __raw_readl(&imx_ccm->cbcdr); | |
410 | u32 freq, podf; | |
411 | ||
412 | podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH1_PODF_MASK) \ | |
413 | >> MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET; | |
414 | ||
415 | switch ((cbcmr & MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK) >> | |
416 | MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET) { | |
417 | case 0: | |
418 | freq = decode_pll(PLL_BUS, MXC_HCLK); | |
419 | break; | |
420 | case 1: | |
762a88cc | 421 | freq = mxc_get_pll_pfd(PLL_BUS, 2); |
25b4aa14 FE |
422 | break; |
423 | case 2: | |
762a88cc | 424 | freq = mxc_get_pll_pfd(PLL_BUS, 0); |
25b4aa14 FE |
425 | break; |
426 | case 3: | |
762a88cc PA |
427 | /* static / 2 divider */ |
428 | freq = mxc_get_pll_pfd(PLL_BUS, 2) / 2; | |
25b4aa14 FE |
429 | } |
430 | ||
431 | return freq / (podf + 1); | |
432 | ||
433 | } | |
c655b816 OS |
434 | #else |
435 | static u32 get_mmdc_ch0_clk(void) | |
436 | { | |
437 | u32 cbcdr = __raw_readl(&imx_ccm->cbcdr); | |
438 | u32 mmdc_ch0_podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK) >> | |
439 | MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET; | |
440 | ||
441 | return get_periph_clk() / (mmdc_ch0_podf + 1); | |
442 | } | |
443 | #endif | |
31f07964 | 444 | |
b93ab2ee PF |
445 | #ifdef CONFIG_MX6SX |
446 | /* qspi_num can be from 0 - 1 */ | |
447 | void enable_qspi_clk(int qspi_num) | |
448 | { | |
449 | u32 reg = 0; | |
450 | /* Enable QuadSPI clock */ | |
451 | switch (qspi_num) { | |
452 | case 0: | |
453 | /* disable the clock gate */ | |
454 | clrbits_le32(&imx_ccm->CCGR3, MXC_CCM_CCGR3_QSPI1_MASK); | |
455 | ||
456 | /* set 50M : (50 = 396 / 2 / 4) */ | |
457 | reg = readl(&imx_ccm->cscmr1); | |
458 | reg &= ~(MXC_CCM_CSCMR1_QSPI1_PODF_MASK | | |
459 | MXC_CCM_CSCMR1_QSPI1_CLK_SEL_MASK); | |
460 | reg |= ((1 << MXC_CCM_CSCMR1_QSPI1_PODF_OFFSET) | | |
461 | (2 << MXC_CCM_CSCMR1_QSPI1_CLK_SEL_OFFSET)); | |
462 | writel(reg, &imx_ccm->cscmr1); | |
463 | ||
464 | /* enable the clock gate */ | |
465 | setbits_le32(&imx_ccm->CCGR3, MXC_CCM_CCGR3_QSPI1_MASK); | |
466 | break; | |
467 | case 1: | |
468 | /* | |
469 | * disable the clock gate | |
470 | * QSPI2 and GPMI_BCH_INPUT_GPMI_IO share the same clock gate, | |
471 | * disable both of them. | |
472 | */ | |
473 | clrbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK | | |
474 | MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK); | |
475 | ||
476 | /* set 50M : (50 = 396 / 2 / 4) */ | |
477 | reg = readl(&imx_ccm->cs2cdr); | |
478 | reg &= ~(MXC_CCM_CS2CDR_QSPI2_CLK_PODF_MASK | | |
479 | MXC_CCM_CS2CDR_QSPI2_CLK_PRED_MASK | | |
480 | MXC_CCM_CS2CDR_QSPI2_CLK_SEL_MASK); | |
481 | reg |= (MXC_CCM_CS2CDR_QSPI2_CLK_PRED(0x1) | | |
482 | MXC_CCM_CS2CDR_QSPI2_CLK_SEL(0x3)); | |
483 | writel(reg, &imx_ccm->cs2cdr); | |
484 | ||
485 | /*enable the clock gate*/ | |
486 | setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK | | |
487 | MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK); | |
488 | break; | |
489 | default: | |
490 | break; | |
491 | } | |
492 | } | |
493 | #endif | |
494 | ||
c655b816 | 495 | #ifdef CONFIG_FEC_MXC |
5f98d0b5 | 496 | int enable_fec_anatop_clock(enum enet_freq freq) |
31f07964 FE |
497 | { |
498 | u32 reg = 0; | |
499 | s32 timeout = 100000; | |
500 | ||
501 | struct anatop_regs __iomem *anatop = | |
502 | (struct anatop_regs __iomem *)ANATOP_BASE_ADDR; | |
503 | ||
7731745c | 504 | if (freq < ENET_25MHZ || freq > ENET_125MHZ) |
5f98d0b5 FE |
505 | return -EINVAL; |
506 | ||
31f07964 | 507 | reg = readl(&anatop->pll_enet); |
5f98d0b5 FE |
508 | reg &= ~BM_ANADIG_PLL_ENET_DIV_SELECT; |
509 | reg |= freq; | |
510 | ||
31f07964 FE |
511 | if ((reg & BM_ANADIG_PLL_ENET_POWERDOWN) || |
512 | (!(reg & BM_ANADIG_PLL_ENET_LOCK))) { | |
513 | reg &= ~BM_ANADIG_PLL_ENET_POWERDOWN; | |
514 | writel(reg, &anatop->pll_enet); | |
515 | while (timeout--) { | |
516 | if (readl(&anatop->pll_enet) & BM_ANADIG_PLL_ENET_LOCK) | |
517 | break; | |
518 | } | |
519 | if (timeout < 0) | |
520 | return -ETIMEDOUT; | |
521 | } | |
522 | ||
523 | /* Enable FEC clock */ | |
524 | reg |= BM_ANADIG_PLL_ENET_ENABLE; | |
525 | reg &= ~BM_ANADIG_PLL_ENET_BYPASS; | |
526 | writel(reg, &anatop->pll_enet); | |
527 | ||
5c045cdd FE |
528 | #ifdef CONFIG_MX6SX |
529 | /* | |
530 | * Set enet ahb clock to 200MHz | |
531 | * pll2_pfd2_396m-> ENET_PODF-> ENET_AHB | |
532 | */ | |
533 | reg = readl(&imx_ccm->chsccdr); | |
534 | reg &= ~(MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_MASK | |
535 | | MXC_CCM_CHSCCDR_ENET_PODF_MASK | |
536 | | MXC_CCM_CHSCCDR_ENET_CLK_SEL_MASK); | |
537 | /* PLL2 PFD2 */ | |
538 | reg |= (4 << MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_OFFSET); | |
539 | /* Div = 2*/ | |
540 | reg |= (1 << MXC_CCM_CHSCCDR_ENET_PODF_OFFSET); | |
541 | reg |= (0 << MXC_CCM_CHSCCDR_ENET_CLK_SEL_OFFSET); | |
542 | writel(reg, &imx_ccm->chsccdr); | |
543 | ||
544 | /* Enable enet system clock */ | |
545 | reg = readl(&imx_ccm->CCGR3); | |
546 | reg |= MXC_CCM_CCGR3_ENET_MASK; | |
547 | writel(reg, &imx_ccm->CCGR3); | |
548 | #endif | |
31f07964 FE |
549 | return 0; |
550 | } | |
25b4aa14 | 551 | #endif |
23608e23 JL |
552 | |
553 | static u32 get_usdhc_clk(u32 port) | |
554 | { | |
555 | u32 root_freq = 0, usdhc_podf = 0, clk_sel = 0; | |
556 | u32 cscmr1 = __raw_readl(&imx_ccm->cscmr1); | |
557 | u32 cscdr1 = __raw_readl(&imx_ccm->cscdr1); | |
558 | ||
559 | switch (port) { | |
560 | case 0: | |
561 | usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC1_PODF_MASK) >> | |
562 | MXC_CCM_CSCDR1_USDHC1_PODF_OFFSET; | |
563 | clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC1_CLK_SEL; | |
564 | ||
565 | break; | |
566 | case 1: | |
567 | usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC2_PODF_MASK) >> | |
568 | MXC_CCM_CSCDR1_USDHC2_PODF_OFFSET; | |
569 | clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC2_CLK_SEL; | |
570 | ||
571 | break; | |
572 | case 2: | |
573 | usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC3_PODF_MASK) >> | |
574 | MXC_CCM_CSCDR1_USDHC3_PODF_OFFSET; | |
575 | clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC3_CLK_SEL; | |
576 | ||
577 | break; | |
578 | case 3: | |
579 | usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC4_PODF_MASK) >> | |
580 | MXC_CCM_CSCDR1_USDHC4_PODF_OFFSET; | |
581 | clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC4_CLK_SEL; | |
582 | ||
583 | break; | |
584 | default: | |
585 | break; | |
586 | } | |
587 | ||
588 | if (clk_sel) | |
762a88cc | 589 | root_freq = mxc_get_pll_pfd(PLL_BUS, 0); |
23608e23 | 590 | else |
762a88cc | 591 | root_freq = mxc_get_pll_pfd(PLL_BUS, 2); |
23608e23 JL |
592 | |
593 | return root_freq / (usdhc_podf + 1); | |
594 | } | |
595 | ||
596 | u32 imx_get_uartclk(void) | |
597 | { | |
598 | return get_uart_clk(); | |
599 | } | |
600 | ||
ff167df5 JL |
601 | u32 imx_get_fecclk(void) |
602 | { | |
adadc915 | 603 | return mxc_get_clock(MXC_IPG_CLK); |
ff167df5 JL |
604 | } |
605 | ||
79814492 | 606 | static int enable_enet_pll(uint32_t en) |
64e7cdb5 | 607 | { |
64e7cdb5 EN |
608 | struct mxc_ccm_reg *const imx_ccm |
609 | = (struct mxc_ccm_reg *) CCM_BASE_ADDR; | |
79814492 MV |
610 | s32 timeout = 100000; |
611 | u32 reg = 0; | |
64e7cdb5 EN |
612 | |
613 | /* Enable PLLs */ | |
614 | reg = readl(&imx_ccm->analog_pll_enet); | |
615 | reg &= ~BM_ANADIG_PLL_SYS_POWERDOWN; | |
616 | writel(reg, &imx_ccm->analog_pll_enet); | |
617 | reg |= BM_ANADIG_PLL_SYS_ENABLE; | |
618 | while (timeout--) { | |
619 | if (readl(&imx_ccm->analog_pll_enet) & BM_ANADIG_PLL_SYS_LOCK) | |
620 | break; | |
621 | } | |
622 | if (timeout <= 0) | |
623 | return -EIO; | |
624 | reg &= ~BM_ANADIG_PLL_SYS_BYPASS; | |
625 | writel(reg, &imx_ccm->analog_pll_enet); | |
79814492 | 626 | reg |= en; |
64e7cdb5 | 627 | writel(reg, &imx_ccm->analog_pll_enet); |
79814492 MV |
628 | return 0; |
629 | } | |
64e7cdb5 | 630 | |
d95b6ab8 | 631 | #ifndef CONFIG_MX6SX |
79814492 MV |
632 | static void ungate_sata_clock(void) |
633 | { | |
634 | struct mxc_ccm_reg *const imx_ccm = | |
635 | (struct mxc_ccm_reg *)CCM_BASE_ADDR; | |
636 | ||
637 | /* Enable SATA clock. */ | |
638 | setbits_le32(&imx_ccm->CCGR5, MXC_CCM_CCGR5_SATA_MASK); | |
639 | } | |
d95b6ab8 | 640 | #endif |
79814492 MV |
641 | |
642 | static void ungate_pcie_clock(void) | |
643 | { | |
644 | struct mxc_ccm_reg *const imx_ccm = | |
645 | (struct mxc_ccm_reg *)CCM_BASE_ADDR; | |
646 | ||
647 | /* Enable PCIe clock. */ | |
648 | setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_PCIE_MASK); | |
649 | } | |
650 | ||
d95b6ab8 | 651 | #ifndef CONFIG_MX6SX |
79814492 MV |
652 | int enable_sata_clock(void) |
653 | { | |
654 | ungate_sata_clock(); | |
655 | return enable_enet_pll(BM_ANADIG_PLL_ENET_ENABLE_SATA); | |
656 | } | |
8d29cef5 NK |
657 | |
658 | void disable_sata_clock(void) | |
659 | { | |
660 | struct mxc_ccm_reg *const imx_ccm = | |
661 | (struct mxc_ccm_reg *)CCM_BASE_ADDR; | |
662 | ||
663 | clrbits_le32(&imx_ccm->CCGR5, MXC_CCM_CCGR5_SATA_MASK); | |
664 | } | |
d95b6ab8 | 665 | #endif |
79814492 MV |
666 | |
667 | int enable_pcie_clock(void) | |
668 | { | |
669 | struct anatop_regs *anatop_regs = | |
670 | (struct anatop_regs *)ANATOP_BASE_ADDR; | |
671 | struct mxc_ccm_reg *ccm_regs = (struct mxc_ccm_reg *)CCM_BASE_ADDR; | |
1b8ad74a | 672 | u32 lvds1_clk_sel; |
79814492 MV |
673 | |
674 | /* | |
675 | * Here be dragons! | |
676 | * | |
677 | * The register ANATOP_MISC1 is not documented in the Freescale | |
678 | * MX6RM. The register that is mapped in the ANATOP space and | |
679 | * marked as ANATOP_MISC1 is actually documented in the PMU section | |
680 | * of the datasheet as PMU_MISC1. | |
681 | * | |
1b8ad74a FE |
682 | * Switch LVDS clock source to SATA (0xb) on mx6q/dl or PCI (0xa) on |
683 | * mx6sx, disable clock INPUT and enable clock OUTPUT. This is important | |
684 | * for PCI express link that is clocked from the i.MX6. | |
79814492 MV |
685 | */ |
686 | #define ANADIG_ANA_MISC1_LVDSCLK1_IBEN (1 << 12) | |
687 | #define ANADIG_ANA_MISC1_LVDSCLK1_OBEN (1 << 10) | |
688 | #define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_MASK 0x0000001F | |
1b8ad74a FE |
689 | #define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_PCIE_REF 0xa |
690 | #define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_SATA_REF 0xb | |
691 | ||
692 | if (is_cpu_type(MXC_CPU_MX6SX)) | |
693 | lvds1_clk_sel = ANADIG_ANA_MISC1_LVDS1_CLK_SEL_PCIE_REF; | |
694 | else | |
695 | lvds1_clk_sel = ANADIG_ANA_MISC1_LVDS1_CLK_SEL_SATA_REF; | |
696 | ||
79814492 MV |
697 | clrsetbits_le32(&anatop_regs->ana_misc1, |
698 | ANADIG_ANA_MISC1_LVDSCLK1_IBEN | | |
699 | ANADIG_ANA_MISC1_LVDS1_CLK_SEL_MASK, | |
1b8ad74a | 700 | ANADIG_ANA_MISC1_LVDSCLK1_OBEN | lvds1_clk_sel); |
79814492 MV |
701 | |
702 | /* PCIe reference clock sourced from AXI. */ | |
703 | clrbits_le32(&ccm_regs->cbcmr, MXC_CCM_CBCMR_PCIE_AXI_CLK_SEL); | |
704 | ||
705 | /* Party time! Ungate the clock to the PCIe. */ | |
d95b6ab8 | 706 | #ifndef CONFIG_MX6SX |
79814492 | 707 | ungate_sata_clock(); |
d95b6ab8 | 708 | #endif |
79814492 MV |
709 | ungate_pcie_clock(); |
710 | ||
711 | return enable_enet_pll(BM_ANADIG_PLL_ENET_ENABLE_SATA | | |
712 | BM_ANADIG_PLL_ENET_ENABLE_PCIE); | |
64e7cdb5 EN |
713 | } |
714 | ||
36c1ca4d NG |
715 | #ifdef CONFIG_SECURE_BOOT |
716 | void hab_caam_clock_enable(unsigned char enable) | |
717 | { | |
718 | u32 reg; | |
719 | ||
720 | /* CG4 ~ CG6, CAAM clocks */ | |
721 | reg = __raw_readl(&imx_ccm->CCGR0); | |
722 | if (enable) | |
723 | reg |= (MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK | | |
724 | MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK | | |
725 | MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK); | |
726 | else | |
727 | reg &= ~(MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK | | |
728 | MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK | | |
729 | MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK); | |
730 | __raw_writel(reg, &imx_ccm->CCGR0); | |
731 | ||
732 | /* EMI slow clk */ | |
733 | reg = __raw_readl(&imx_ccm->CCGR6); | |
734 | if (enable) | |
735 | reg |= MXC_CCM_CCGR6_EMI_SLOW_MASK; | |
736 | else | |
737 | reg &= ~MXC_CCM_CCGR6_EMI_SLOW_MASK; | |
738 | __raw_writel(reg, &imx_ccm->CCGR6); | |
739 | } | |
740 | #endif | |
741 | ||
cf202d26 NG |
742 | static void enable_pll3(void) |
743 | { | |
744 | struct anatop_regs __iomem *anatop = | |
745 | (struct anatop_regs __iomem *)ANATOP_BASE_ADDR; | |
746 | ||
747 | /* make sure pll3 is enabled */ | |
748 | if ((readl(&anatop->usb1_pll_480_ctrl) & | |
749 | BM_ANADIG_USB1_PLL_480_CTRL_LOCK) == 0) { | |
750 | /* enable pll's power */ | |
751 | writel(BM_ANADIG_USB1_PLL_480_CTRL_POWER, | |
752 | &anatop->usb1_pll_480_ctrl_set); | |
753 | writel(0x80, &anatop->ana_misc2_clr); | |
754 | /* wait for pll lock */ | |
755 | while ((readl(&anatop->usb1_pll_480_ctrl) & | |
756 | BM_ANADIG_USB1_PLL_480_CTRL_LOCK) == 0) | |
757 | ; | |
758 | /* disable bypass */ | |
759 | writel(BM_ANADIG_USB1_PLL_480_CTRL_BYPASS, | |
760 | &anatop->usb1_pll_480_ctrl_clr); | |
761 | /* enable pll output */ | |
762 | writel(BM_ANADIG_USB1_PLL_480_CTRL_ENABLE, | |
763 | &anatop->usb1_pll_480_ctrl_set); | |
764 | } | |
765 | } | |
766 | ||
767 | void enable_thermal_clk(void) | |
768 | { | |
769 | enable_pll3(); | |
770 | } | |
771 | ||
23608e23 JL |
772 | unsigned int mxc_get_clock(enum mxc_clock clk) |
773 | { | |
774 | switch (clk) { | |
775 | case MXC_ARM_CLK: | |
776 | return get_mcu_main_clk(); | |
777 | case MXC_PER_CLK: | |
778 | return get_periph_clk(); | |
779 | case MXC_AHB_CLK: | |
780 | return get_ahb_clk(); | |
781 | case MXC_IPG_CLK: | |
782 | return get_ipg_clk(); | |
783 | case MXC_IPG_PERCLK: | |
e7bed5c2 | 784 | case MXC_I2C_CLK: |
23608e23 JL |
785 | return get_ipg_per_clk(); |
786 | case MXC_UART_CLK: | |
787 | return get_uart_clk(); | |
788 | case MXC_CSPI_CLK: | |
789 | return get_cspi_clk(); | |
790 | case MXC_AXI_CLK: | |
791 | return get_axi_clk(); | |
792 | case MXC_EMI_SLOW_CLK: | |
793 | return get_emi_slow_clk(); | |
794 | case MXC_DDR_CLK: | |
795 | return get_mmdc_ch0_clk(); | |
796 | case MXC_ESDHC_CLK: | |
797 | return get_usdhc_clk(0); | |
798 | case MXC_ESDHC2_CLK: | |
799 | return get_usdhc_clk(1); | |
800 | case MXC_ESDHC3_CLK: | |
801 | return get_usdhc_clk(2); | |
802 | case MXC_ESDHC4_CLK: | |
803 | return get_usdhc_clk(3); | |
804 | case MXC_SATA_CLK: | |
805 | return get_ahb_clk(); | |
806 | default: | |
eb412d79 | 807 | printf("Unsupported MXC CLK: %d\n", clk); |
23608e23 JL |
808 | break; |
809 | } | |
810 | ||
eb412d79 | 811 | return 0; |
23608e23 JL |
812 | } |
813 | ||
814 | /* | |
815 | * Dump some core clockes. | |
816 | */ | |
817 | int do_mx6_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) | |
818 | { | |
819 | u32 freq; | |
833b6435 | 820 | freq = decode_pll(PLL_SYS, MXC_HCLK); |
23608e23 | 821 | printf("PLL_SYS %8d MHz\n", freq / 1000000); |
833b6435 | 822 | freq = decode_pll(PLL_BUS, MXC_HCLK); |
23608e23 | 823 | printf("PLL_BUS %8d MHz\n", freq / 1000000); |
833b6435 | 824 | freq = decode_pll(PLL_USBOTG, MXC_HCLK); |
23608e23 | 825 | printf("PLL_OTG %8d MHz\n", freq / 1000000); |
833b6435 | 826 | freq = decode_pll(PLL_ENET, MXC_HCLK); |
23608e23 JL |
827 | printf("PLL_NET %8d MHz\n", freq / 1000000); |
828 | ||
829 | printf("\n"); | |
830 | printf("IPG %8d kHz\n", mxc_get_clock(MXC_IPG_CLK) / 1000); | |
831 | printf("UART %8d kHz\n", mxc_get_clock(MXC_UART_CLK) / 1000); | |
cc446726 | 832 | #ifdef CONFIG_MXC_SPI |
23608e23 | 833 | printf("CSPI %8d kHz\n", mxc_get_clock(MXC_CSPI_CLK) / 1000); |
cc446726 | 834 | #endif |
23608e23 JL |
835 | printf("AHB %8d kHz\n", mxc_get_clock(MXC_AHB_CLK) / 1000); |
836 | printf("AXI %8d kHz\n", mxc_get_clock(MXC_AXI_CLK) / 1000); | |
837 | printf("DDR %8d kHz\n", mxc_get_clock(MXC_DDR_CLK) / 1000); | |
838 | printf("USDHC1 %8d kHz\n", mxc_get_clock(MXC_ESDHC_CLK) / 1000); | |
839 | printf("USDHC2 %8d kHz\n", mxc_get_clock(MXC_ESDHC2_CLK) / 1000); | |
840 | printf("USDHC3 %8d kHz\n", mxc_get_clock(MXC_ESDHC3_CLK) / 1000); | |
841 | printf("USDHC4 %8d kHz\n", mxc_get_clock(MXC_ESDHC4_CLK) / 1000); | |
842 | printf("EMI SLOW %8d kHz\n", mxc_get_clock(MXC_EMI_SLOW_CLK) / 1000); | |
843 | printf("IPG PERCLK %8d kHz\n", mxc_get_clock(MXC_IPG_PERCLK) / 1000); | |
844 | ||
845 | return 0; | |
846 | } | |
847 | ||
d95b6ab8 | 848 | #ifndef CONFIG_MX6SX |
5ea7f0e3 PKS |
849 | void enable_ipu_clock(void) |
850 | { | |
851 | struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; | |
852 | int reg; | |
853 | reg = readl(&mxc_ccm->CCGR3); | |
a0a0dacf | 854 | reg |= MXC_CCM_CCGR3_IPU1_IPU_MASK; |
5ea7f0e3 PKS |
855 | writel(reg, &mxc_ccm->CCGR3); |
856 | } | |
d95b6ab8 | 857 | #endif |
23608e23 JL |
858 | /***************************************************/ |
859 | ||
860 | U_BOOT_CMD( | |
861 | clocks, CONFIG_SYS_MAXARGS, 1, do_mx6_showclocks, | |
862 | "display clocks", | |
863 | "" | |
864 | ); |