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ARM: DRA72-evm: Enable HW leveling
[people/ms/u-boot.git] / arch / arm / cpu / armv7 / omap5 / sdram.c
CommitLineData
bb772a59 1/*
971f2ba2 2 * Timing and Organization details of the ddr device parts used in OMAP5
bb772a59
S		 3 * EVM
4 *
5 * (C) Copyright 2010
6 * Texas Instruments, <www.ti.com>
7 *
8 * Aneesh V <aneesh@ti.com>
9 * Sricharan R <r.sricharan@ti.com>
10 *
1a459660 11 * SPDX-License-Identifier: GPL-2.0+
bb772a59
S		 12 */
13
14#include <asm/emif.h>
15#include <asm/arch/sys_proto.h>
16
17/*
18 * This file provides details of the LPDDR2 SDRAM parts used on OMAP5
19 * EVM. Since the parts used and geometry are identical for
20 * evm for a given OMAP5 revision, this information is kept
21 * here instead of being in board directory. However the key functions
22 * exported are weakly linked so that they can be over-ridden in the board
23 * directory if there is a OMAP5 board in the future that uses a different
24 * memory device or geometry.
25 *
26 * For any new board with different memory devices over-ride one or more
27 * of the following functions as per the CONFIG flags you intend to enable:
28 * - emif_get_reg_dump()
29 * - emif_get_dmm_regs()
30 * - emif_get_device_details()
31 * - emif_get_device_timings()
32 */
33
34#ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
971f2ba2 35const struct emif_regs emif_regs_532_mhz_2cs = {
f4010734
S		 36 .sdram_config_init = 0x80800EBA,
37 .sdram_config = 0x808022BA,
bb772a59
S		 38 .ref_ctrl = 0x0000081A,
39 .sdram_tim1 = 0x772F6873,
f4010734
S		 40 .sdram_tim2 = 0x304a129a,
41 .sdram_tim3 = 0x02f7e45f,
42 .read_idle_ctrl = 0x00050000,
43 .zq_config = 0x000b3215,
44 .temp_alert_config = 0x08000a05,
45 .emif_ddr_phy_ctlr_1_init = 0x0E28420d,
46 .emif_ddr_phy_ctlr_1 = 0x0E28420d,
47 .emif_ddr_ext_phy_ctrl_1 = 0x04020080,
48 .emif_ddr_ext_phy_ctrl_2 = 0x28C518A3,
49 .emif_ddr_ext_phy_ctrl_3 = 0x518A3146,
50 .emif_ddr_ext_phy_ctrl_4 = 0x0014628C,
51 .emif_ddr_ext_phy_ctrl_5 = 0x04010040
52};
53
9100edec
LV		 54const struct emif_regs emif_regs_532_mhz_2cs_es2 = {
55 .sdram_config_init = 0x80800EBA,
56 .sdram_config = 0x808022BA,
57 .ref_ctrl = 0x0000081A,
58 .sdram_tim1 = 0x772F6873,
59 .sdram_tim2 = 0x304a129a,
60 .sdram_tim3 = 0x02f7e45f,
61 .read_idle_ctrl = 0x00050000,
62 .zq_config = 0x100b3215,
63 .temp_alert_config = 0x08000a05,
64 .emif_ddr_phy_ctlr_1_init = 0x0E30400d,
65 .emif_ddr_phy_ctlr_1 = 0x0E30400d,
66 .emif_ddr_ext_phy_ctrl_1 = 0x04020080,
67 .emif_ddr_ext_phy_ctrl_2 = 0x28C518A3,
68 .emif_ddr_ext_phy_ctrl_3 = 0x518A3146,
69 .emif_ddr_ext_phy_ctrl_4 = 0x0014628C,
70 .emif_ddr_ext_phy_ctrl_5 = 0xC330CC33,
71};
72
971f2ba2 73const struct emif_regs emif_regs_266_mhz_2cs = {
f4010734
S		 74 .sdram_config_init = 0x80800EBA,
75 .sdram_config = 0x808022BA,
76 .ref_ctrl = 0x0000040D,
77 .sdram_tim1 = 0x2A86B419,
78 .sdram_tim2 = 0x1025094A,
79 .sdram_tim3 = 0x026BA22F,
bb772a59 80 .read_idle_ctrl = 0x00050000,
f4010734
S		 81 .zq_config = 0x000b3215,
82 .temp_alert_config = 0x08000a05,
83 .emif_ddr_phy_ctlr_1_init = 0x0E28420d,
84 .emif_ddr_phy_ctlr_1 = 0x0E28420d,
85 .emif_ddr_ext_phy_ctrl_1 = 0x04020080,
86 .emif_ddr_ext_phy_ctrl_2 = 0x0A414829,
87 .emif_ddr_ext_phy_ctrl_3 = 0x14829052,
88 .emif_ddr_ext_phy_ctrl_4 = 0x000520A4,
89 .emif_ddr_ext_phy_ctrl_5 = 0x04010040
bb772a59
S		 90};
91
43037d76
LV		 92const struct emif_regs emif_regs_ddr3_532_mhz_1cs = {
93 .sdram_config_init = 0x61851B32,
94 .sdram_config = 0x61851B32,
92b0482c 95 .sdram_config2 = 0x0,
43037d76
LV		 96 .ref_ctrl = 0x00001035,
97 .sdram_tim1 = 0xCCCF36B3,
98 .sdram_tim2 = 0x308F7FDA,
99 .sdram_tim3 = 0x027F88A8,
100 .read_idle_ctrl = 0x00050000,
101 .zq_config = 0x0007190B,
102 .temp_alert_config = 0x00000000,
103 .emif_ddr_phy_ctlr_1_init = 0x0020420A,
104 .emif_ddr_phy_ctlr_1 = 0x0024420A,
105 .emif_ddr_ext_phy_ctrl_1 = 0x04040100,
106 .emif_ddr_ext_phy_ctrl_2 = 0x00000000,
107 .emif_ddr_ext_phy_ctrl_3 = 0x00000000,
108 .emif_ddr_ext_phy_ctrl_4 = 0x00000000,
109 .emif_ddr_ext_phy_ctrl_5 = 0x04010040,
110 .emif_rd_wr_lvl_rmp_win = 0x00000000,
111 .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
112 .emif_rd_wr_lvl_ctl = 0x00000000,
113 .emif_rd_wr_exec_thresh = 0x00000305
114};
115
9100edec
LV		 116const struct emif_regs emif_regs_ddr3_532_mhz_1cs_es2 = {
117 .sdram_config_init = 0x61851B32,
118 .sdram_config = 0x61851B32,
92b0482c 119 .sdram_config2 = 0x0,
9100edec
LV		 120 .ref_ctrl = 0x00001035,
121 .sdram_tim1 = 0xCCCF36B3,
122 .sdram_tim2 = 0x308F7FDA,
123 .sdram_tim3 = 0x027F88A8,
124 .read_idle_ctrl = 0x00050000,
125 .zq_config = 0x1007190B,
126 .temp_alert_config = 0x00000000,
127 .emif_ddr_phy_ctlr_1_init = 0x0030400A,
128 .emif_ddr_phy_ctlr_1 = 0x0034400A,
129 .emif_ddr_ext_phy_ctrl_1 = 0x04040100,
130 .emif_ddr_ext_phy_ctrl_2 = 0x00000000,
131 .emif_ddr_ext_phy_ctrl_3 = 0x00000000,
132 .emif_ddr_ext_phy_ctrl_4 = 0x00000000,
133 .emif_ddr_ext_phy_ctrl_5 = 0x4350D435,
134 .emif_rd_wr_lvl_rmp_win = 0x00000000,
135 .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
136 .emif_rd_wr_lvl_ctl = 0x00000000,
137 .emif_rd_wr_exec_thresh = 0x40000305
138};
139
92b0482c
S		 140const struct emif_regs emif_1_regs_ddr3_532_mhz_1cs_dra_es1 = {
141 .sdram_config_init = 0x61851ab2,
142 .sdram_config = 0x61851ab2,
143 .sdram_config2 = 0x08000000,
802bb57a
LV		 144 .ref_ctrl = 0x000040F1,
145 .ref_ctrl_final = 0x00001035,
92b0482c
S		 146 .sdram_tim1 = 0xCCCF36B3,
147 .sdram_tim2 = 0x308F7FDA,
148 .sdram_tim3 = 0x027F88A8,
f2a1b93b 149 .read_idle_ctrl = 0x00050001,
92b0482c
S		 150 .zq_config = 0x0007190B,
151 .temp_alert_config = 0x00000000,
920638fa
LV		 152 .emif_ddr_phy_ctlr_1_init = 0x0024400B,
153 .emif_ddr_phy_ctlr_1 = 0x0E24400B,
6c70935d 154 .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
1860d101
LV		 155 .emif_ddr_ext_phy_ctrl_2 = 0x00910091,
156 .emif_ddr_ext_phy_ctrl_3 = 0x00950095,
157 .emif_ddr_ext_phy_ctrl_4 = 0x009B009B,
158 .emif_ddr_ext_phy_ctrl_5 = 0x009E009E,
92b0482c 159 .emif_rd_wr_lvl_rmp_win = 0x00000000,
920638fa 160 .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
92b0482c
S		 161 .emif_rd_wr_lvl_ctl = 0x00000000,
162 .emif_rd_wr_exec_thresh = 0x00000305
163};
164
165const struct emif_regs emif_2_regs_ddr3_532_mhz_1cs_dra_es1 = {
166 .sdram_config_init = 0x61851B32,
167 .sdram_config = 0x61851B32,
168 .sdram_config2 = 0x08000000,
802bb57a
LV		 169 .ref_ctrl = 0x000040F1,
170 .ref_ctrl_final = 0x00001035,
92b0482c
S		 171 .sdram_tim1 = 0xCCCF36B3,
172 .sdram_tim2 = 0x308F7FDA,
173 .sdram_tim3 = 0x027F88A8,
f2a1b93b 174 .read_idle_ctrl = 0x00050001,
92b0482c
S		 175 .zq_config = 0x0007190B,
176 .temp_alert_config = 0x00000000,
920638fa
LV		 177 .emif_ddr_phy_ctlr_1_init = 0x0024400B,
178 .emif_ddr_phy_ctlr_1 = 0x0E24400B,
6c70935d 179 .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
1860d101
LV		 180 .emif_ddr_ext_phy_ctrl_2 = 0x00910091,
181 .emif_ddr_ext_phy_ctrl_3 = 0x00950095,
182 .emif_ddr_ext_phy_ctrl_4 = 0x009B009B,
183 .emif_ddr_ext_phy_ctrl_5 = 0x009E009E,
92b0482c 184 .emif_rd_wr_lvl_rmp_win = 0x00000000,
920638fa 185 .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
92b0482c
S		 186 .emif_rd_wr_lvl_ctl = 0x00000000,
187 .emif_rd_wr_exec_thresh = 0x00000305
188};
189
681f785f 190const struct emif_regs emif_1_regs_ddr3_666_mhz_1cs_dra_es1 = {
aa8ac436
AS		 191 .sdram_config_init = 0x61862B32,
192 .sdram_config = 0x61862B32,
681f785f 193 .sdram_config2 = 0x08000000,
f308b4fc 194 .ref_ctrl = 0x0000514C,
802bb57a 195 .ref_ctrl_final = 0x0000144A,
aa8ac436 196 .sdram_tim1 = 0xD113781C,
f308b4fc
LV		 197 .sdram_tim2 = 0x305A7FDA,
198 .sdram_tim3 = 0x409F86A8,
681f785f 199 .read_idle_ctrl = 0x00050000,
f308b4fc 200 .zq_config = 0x5007190B,
681f785f 201 .temp_alert_config = 0x00000000,
f308b4fc 202 .emif_ddr_phy_ctlr_1_init = 0x0024400D,
aa8ac436 203 .emif_ddr_phy_ctlr_1 = 0x0E24400D,
681f785f
S		 204 .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
205 .emif_ddr_ext_phy_ctrl_2 = 0x00A400A4,
206 .emif_ddr_ext_phy_ctrl_3 = 0x00A900A9,
207 .emif_ddr_ext_phy_ctrl_4 = 0x00B000B0,
208 .emif_ddr_ext_phy_ctrl_5 = 0x00B000B0,
209 .emif_rd_wr_lvl_rmp_win = 0x00000000,
f308b4fc 210 .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
681f785f
S		 211 .emif_rd_wr_lvl_ctl = 0x00000000,
212 .emif_rd_wr_exec_thresh = 0x00000305
213};
214
f4010734
S		 215const struct dmm_lisa_map_regs lisa_map_4G_x_2_x_2 = {
216 .dmm_lisa_map_0 = 0x0,
77efdeb7
S		 217 .dmm_lisa_map_1 = 0x0,
218 .dmm_lisa_map_2 = 0x80740300,
7831419d
LV		 219 .dmm_lisa_map_3 = 0xFF020100,
220 .is_ma_present = 0x1
221};
222
92b0482c
S		 223/*
224 * DRA752 EVM board has 1.5 GB of memory
225 * EMIF1 --> 2Gb * 2 = 512MB
226 * EMIF2 --> 2Gb * 4 = 1GB
227 * so mapping 1GB interleaved and 512MB non-interleaved
228 */
229const struct dmm_lisa_map_regs lisa_map_2G_x_2_x_2_2G_x_1_x_2 = {
230 .dmm_lisa_map_0 = 0x0,
231 .dmm_lisa_map_1 = 0x80640300,
232 .dmm_lisa_map_2 = 0xC0500220,
233 .dmm_lisa_map_3 = 0xFF020100,
234 .is_ma_present = 0x1
235};
236
237/*
238 * DRA752 EVM EMIF1 ONLY CONFIGURATION
239 */
240const struct dmm_lisa_map_regs lisa_map_2G_x_1_x_2 = {
7831419d
LV		 241 .dmm_lisa_map_0 = 0x0,
242 .dmm_lisa_map_1 = 0x0,
92b0482c
S		 243 .dmm_lisa_map_2 = 0x80500100,
244 .dmm_lisa_map_3 = 0xFF020100,
245 .is_ma_present = 0x1
246};
247
248/*
249 * DRA752 EVM EMIF2 ONLY CONFIGURATION
250 */
251const struct dmm_lisa_map_regs lisa_map_2G_x_2_x_2 = {
252 .dmm_lisa_map_0 = 0x0,
253 .dmm_lisa_map_1 = 0x0,
254 .dmm_lisa_map_2 = 0x80600200,
255 .dmm_lisa_map_3 = 0xFF020100,
7831419d 256 .is_ma_present = 0x1
f4010734
S		 257};
258
9fcf3d3a
LV		 259/*
260 * DRA722 EVM EMIF1 CONFIGURATION
261 */
262const struct dmm_lisa_map_regs lisa_map_2G_x_2 = {
263 .dmm_lisa_map_0 = 0x0,
264 .dmm_lisa_map_1 = 0x0,
265 .dmm_lisa_map_2 = 0x80600100,
266 .dmm_lisa_map_3 = 0xFF020100,
267 .is_ma_present = 0x1
268};
269
e05a4f1f
LV		 270static void emif_get_reg_dump_sdp(u32 emif_nr, const struct emif_regs **regs)
271{
272 switch (omap_revision()) {
273 case OMAP5430_ES1_0:
274 *regs = &emif_regs_532_mhz_2cs;
275 break;
276 case OMAP5432_ES1_0:
277 *regs = &emif_regs_ddr3_532_mhz_1cs;
278 break;
9100edec
LV		 279 case OMAP5430_ES2_0:
280 *regs = &emif_regs_532_mhz_2cs_es2;
281 break;
282 case OMAP5432_ES2_0:
92b0482c
S		 283 *regs = &emif_regs_ddr3_532_mhz_1cs_es2;
284 break;
7831419d 285 case DRA752_ES1_0:
3ac8c0bf 286 case DRA752_ES1_1:
92b0482c
S		 287 switch (emif_nr) {
288 case 1:
289 *regs = &emif_1_regs_ddr3_532_mhz_1cs_dra_es1;
290 break;
291 case 2:
292 *regs = &emif_2_regs_ddr3_532_mhz_1cs_dra_es1;
293 break;
294 }
295 break;
9fcf3d3a 296 case DRA722_ES1_0:
681f785f
S		 297 *regs = &emif_1_regs_ddr3_666_mhz_1cs_dra_es1;
298 break;
e05a4f1f 299 default:
92b0482c 300 *regs = &emif_1_regs_ddr3_532_mhz_1cs_dra_es1;
e05a4f1f
LV		 301 }
302}
303
304void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
305 __attribute__((weak, alias("emif_get_reg_dump_sdp")));
306
307static void emif_get_dmm_regs_sdp(const struct dmm_lisa_map_regs
308 **dmm_lisa_regs)
309{
7831419d
LV		 310 switch (omap_revision()) {
311 case OMAP5430_ES1_0:
312 case OMAP5430_ES2_0:
313 case OMAP5432_ES1_0:
314 case OMAP5432_ES2_0:
315 *dmm_lisa_regs = &lisa_map_4G_x_2_x_2;
316 break;
317 case DRA752_ES1_0:
3ac8c0bf 318 case DRA752_ES1_1:
92b0482c 319 *dmm_lisa_regs = &lisa_map_2G_x_2_x_2_2G_x_1_x_2;
9fcf3d3a
LV		 320 break;
321 case DRA722_ES1_0:
322 default:
323 *dmm_lisa_regs = &lisa_map_2G_x_2;
7831419d
LV		 324 }
325
e05a4f1f
LV		 326}
327
328void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
329 __attribute__((weak, alias("emif_get_dmm_regs_sdp")));
330#else
331
332static const struct lpddr2_device_details dev_4G_S4_details = {
333 .type = LPDDR2_TYPE_S4,
334 .density = LPDDR2_DENSITY_4Gb,
335 .io_width = LPDDR2_IO_WIDTH_32,
336 .manufacturer = LPDDR2_MANUFACTURER_SAMSUNG
337};
338
339static void emif_get_device_details_sdp(u32 emif_nr,
340 struct lpddr2_device_details *cs0_device_details,
341 struct lpddr2_device_details *cs1_device_details)
342{
343 /* EMIF1 & EMIF2 have identical configuration */
344 *cs0_device_details = dev_4G_S4_details;
345 *cs1_device_details = dev_4G_S4_details;
346}
347
348void emif_get_device_details(u32 emif_nr,
349 struct lpddr2_device_details *cs0_device_details,
350 struct lpddr2_device_details *cs1_device_details)
351 __attribute__((weak, alias("emif_get_device_details_sdp")));
352
353#endif /* CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS */
354
6c70935d 355const u32 ext_phy_ctrl_const_base[] = {
f4010734
S		 356 0x01004010,
357 0x00001004,
358 0x04010040,
359 0x01004010,
360 0x00001004,
361 0x00000000,
362 0x00000000,
363 0x00000000,
364 0x80080080,
365 0x00800800,
366 0x08102040,
367 0x00000001,
368 0x540A8150,
369 0xA81502a0,
370 0x002A0540,
371 0x00000000,
372 0x00000000,
373 0x00000000,
92b0482c
S		 374 0x00000077,
375 0x0
bb772a59
S		 376};
377
6c70935d 378const u32 ddr3_ext_phy_ctrl_const_base_es1[] = {
43037d76
LV		 379 0x01004010,
380 0x00001004,
381 0x04010040,
382 0x01004010,
383 0x00001004,
384 0x00000000,
385 0x00000000,
386 0x00000000,
387 0x80080080,
388 0x00800800,
389 0x08102040,
390 0x00000002,
391 0x0,
392 0x0,
393 0x0,
394 0x00000000,
395 0x00000000,
396 0x00000000,
92b0482c
S		 397 0x00000057,
398 0x0
43037d76
LV		 399};
400
6c70935d 401const u32 ddr3_ext_phy_ctrl_const_base_es2[] = {
9100edec
LV		 402 0x50D4350D,
403 0x00000D43,
404 0x04010040,
405 0x01004010,
406 0x00001004,
407 0x00000000,
408 0x00000000,
409 0x00000000,
410 0x80080080,
411 0x00800800,
412 0x08102040,
413 0x00000002,
414 0x00000000,
415 0x00000000,
416 0x00000000,
417 0x00000000,
418 0x00000000,
419 0x00000000,
92b0482c
S		 420 0x00000057,
421 0x0
422};
423
6213db78 424/* Ext phy ctrl 1-35 regs */
92b0482c 425const u32
6c70935d 426dra_ddr3_ext_phy_ctrl_const_base_es1_emif1[] = {
6213db78
LV		 427 0x10040100,
428 0x00910091,
429 0x00950095,
430 0x009B009B,
431 0x009E009E,
1860d101
LV		 432 0x00980098,
433 0x00340034,
434 0x00350035,
435 0x00340034,
436 0x00310031,
437 0x00340034,
f2a1b93b
S		 438 0x007F007F,
439 0x007F007F,
440 0x007F007F,
441 0x007F007F,
442 0x007F007F,
1860d101
LV		 443 0x00480048,
444 0x004A004A,
445 0x00520052,
446 0x00550055,
447 0x00500050,
f2a1b93b
S		 448 0x00000000,
449 0x00600020,
6213db78 450 0x40011080,
6c70935d
S		 451 0x08102040,
452 0x0,
453 0x0,
454 0x0,
455 0x0,
920638fa
LV		 456 0x0,
457 0x0,
458 0x0,
459 0x0,
460 0x0,
6c70935d 461 0x0
92b0482c
S		 462};
463
6213db78 464/* Ext phy ctrl 1-35 regs */
92b0482c 465const u32
6c70935d 466dra_ddr3_ext_phy_ctrl_const_base_es1_emif2[] = {
6213db78
LV		 467 0x10040100,
468 0x00910091,
469 0x00950095,
470 0x009B009B,
471 0x009E009E,
1860d101
LV		 472 0x00980098,
473 0x00330033,
474 0x00330033,
475 0x002F002F,
476 0x00320032,
477 0x00310031,
6c70935d
S		 478 0x007F007F,
479 0x007F007F,
480 0x007F007F,
481 0x007F007F,
482 0x007F007F,
1860d101
LV		 483 0x00520052,
484 0x00520052,
485 0x00470047,
486 0x00490049,
487 0x00500050,
f2a1b93b 488 0x00000000,
6c70935d 489 0x00600020,
6213db78 490 0x40011080,
6c70935d
S		 491 0x08102040,
492 0x0,
493 0x0,
494 0x0,
495 0x0,
920638fa
LV		 496 0x0,
497 0x0,
498 0x0,
499 0x0,
500 0x0,
6c70935d 501 0x0
9100edec
LV		 502};
503
6213db78 504/* Ext phy ctrl 1-35 regs */
681f785f
S		 505const u32
506dra_ddr3_ext_phy_ctrl_const_base_666MHz[] = {
6213db78
LV		 507 0x10040100,
508 0x00A400A4,
509 0x00A900A9,
510 0x00B000B0,
511 0x00B000B0,
681f785f
S		 512 0x00A400A4,
513 0x00390039,
514 0x00320032,
515 0x00320032,
516 0x00320032,
517 0x00440044,
518 0x00550055,
519 0x00550055,
520 0x00550055,
521 0x00550055,
522 0x007F007F,
523 0x004D004D,
524 0x00430043,
525 0x00560056,
526 0x00540054,
527 0x00600060,
528 0x0,
529 0x00600020,
530 0x40010080,
531 0x08102040,
532 0x0,
533 0x0,
534 0x0,
535 0x0,
f308b4fc
LV		 536 0x0,
537 0x0,
538 0x0,
539 0x0,
540 0x0,
681f785f
S		 541 0x0
542};
543
e05a4f1f
LV		 544const struct lpddr2_mr_regs mr_regs = {
545 .mr1 = MR1_BL_8_BT_SEQ_WRAP_EN_NWR_8,
546 .mr2 = 0x6,
547 .mr3 = 0x1,
548 .mr10 = MR10_ZQ_ZQINIT,
549 .mr16 = MR16_REF_FULL_ARRAY
550};
bb772a59 551
eedd9916 552void __weak emif_get_ext_phy_ctrl_const_regs(u32 emif_nr,
6c70935d
S		 553 const u32 **regs,
554 u32 *size)
bb772a59 555{
e05a4f1f
LV		 556 switch (omap_revision()) {
557 case OMAP5430_ES1_0:
9100edec 558 case OMAP5430_ES2_0:
e05a4f1f 559 *regs = ext_phy_ctrl_const_base;
6c70935d 560 *size = ARRAY_SIZE(ext_phy_ctrl_const_base);
e05a4f1f
LV		 561 break;
562 case OMAP5432_ES1_0:
563 *regs = ddr3_ext_phy_ctrl_const_base_es1;
6c70935d 564 *size = ARRAY_SIZE(ddr3_ext_phy_ctrl_const_base_es1);
e05a4f1f 565 break;
9100edec 566 case OMAP5432_ES2_0:
92b0482c 567 *regs = ddr3_ext_phy_ctrl_const_base_es2;
6c70935d 568 *size = ARRAY_SIZE(ddr3_ext_phy_ctrl_const_base_es2);
92b0482c 569 break;
7831419d 570 case DRA752_ES1_0:
3ac8c0bf 571 case DRA752_ES1_1:
6c70935d 572 if (emif_nr == 1) {
92b0482c 573 *regs = dra_ddr3_ext_phy_ctrl_const_base_es1_emif1;
6c70935d
S		 574 *size =
575 ARRAY_SIZE(dra_ddr3_ext_phy_ctrl_const_base_es1_emif1);
576 } else {
92b0482c 577 *regs = dra_ddr3_ext_phy_ctrl_const_base_es1_emif2;
6c70935d
S		 578 *size =
579 ARRAY_SIZE(dra_ddr3_ext_phy_ctrl_const_base_es1_emif2);
580 }
92b0482c 581 break;
681f785f
S		 582 case DRA722_ES1_0:
583 *regs = dra_ddr3_ext_phy_ctrl_const_base_666MHz;
584 *size = ARRAY_SIZE(dra_ddr3_ext_phy_ctrl_const_base_666MHz);
585 break;
e05a4f1f 586 default:
9100edec 587 *regs = ddr3_ext_phy_ctrl_const_base_es2;
6c70935d 588 *size = ARRAY_SIZE(ddr3_ext_phy_ctrl_const_base_es2);
9100edec 589
e05a4f1f 590 }
bb772a59
S		 591}
592
e05a4f1f 593void get_lpddr2_mr_regs(const struct lpddr2_mr_regs **regs)
bb772a59 594{
e05a4f1f 595 *regs = &mr_regs;
bb772a59
S		 596}
597
6213db78 598static void do_ext_phy_settings_omap5(u32 base, const struct emif_regs *regs)
25476382
S		 599{
600 u32 *ext_phy_ctrl_base = 0;
601 u32 *emif_ext_phy_ctrl_base = 0;
92b0482c 602 u32 emif_nr;
e05a4f1f 603 const u32 *ext_phy_ctrl_const_regs;
25476382 604 u32 i = 0;
6c70935d 605 u32 size;
25476382 606
92b0482c
S		 607 emif_nr = (base == EMIF1_BASE) ? 1 : 2;
608
25476382
S		 609 struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
610
611 ext_phy_ctrl_base = (u32 *) &(regs->emif_ddr_ext_phy_ctrl_1);
612 emif_ext_phy_ctrl_base = (u32 *) &(emif->emif_ddr_ext_phy_ctrl_1);
613
614 /* Configure external phy control timing registers */
615 for (i = 0; i < EMIF_EXT_PHY_CTRL_TIMING_REG; i++) {
616 writel(*ext_phy_ctrl_base, emif_ext_phy_ctrl_base++);
617 /* Update shadow registers */
618 writel(*ext_phy_ctrl_base++, emif_ext_phy_ctrl_base++);
619 }
620
621 /*
622 * external phy 6-24 registers do not change with
623 * ddr frequency
624 */
6c70935d
S		 625 emif_get_ext_phy_ctrl_const_regs(emif_nr,
626 &ext_phy_ctrl_const_regs, &size);
627
628 for (i = 0; i < size; i++) {
e05a4f1f
LV		 629 writel(ext_phy_ctrl_const_regs[i],
630 emif_ext_phy_ctrl_base++);
25476382 631 /* Update shadow registers */
e05a4f1f
LV		 632 writel(ext_phy_ctrl_const_regs[i],
633 emif_ext_phy_ctrl_base++);
25476382
S		 634 }
635}
636
6213db78
LV		 637static void do_ext_phy_settings_dra7(u32 base, const struct emif_regs *regs)
638{
639 struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
640 u32 *emif_ext_phy_ctrl_base = 0;
641 u32 emif_nr;
642 const u32 *ext_phy_ctrl_const_regs;
643 u32 i, hw_leveling, size;
644
645 emif_nr = (base == EMIF1_BASE) ? 1 : 2;
646
647 hw_leveling = regs->emif_rd_wr_lvl_rmp_ctl >> EMIF_REG_RDWRLVL_EN_SHIFT;
648
649 emif_ext_phy_ctrl_base = (u32 *)&(emif->emif_ddr_ext_phy_ctrl_1);
650
651 emif_get_ext_phy_ctrl_const_regs(emif_nr,
652 &ext_phy_ctrl_const_regs, &size);
653
654 writel(ext_phy_ctrl_const_regs[0], &emif_ext_phy_ctrl_base[0]);
655 writel(ext_phy_ctrl_const_regs[0], &emif_ext_phy_ctrl_base[1]);
656
657 if (!hw_leveling) {
658 /*
659 * Copy the predefined PHY register values
660 * in case of sw leveling
661 */
662 for (i = 1; i < 25; i++) {
663 writel(ext_phy_ctrl_const_regs[i],
664 &emif_ext_phy_ctrl_base[i * 2]);
665 writel(ext_phy_ctrl_const_regs[i],
666 &emif_ext_phy_ctrl_base[i * 2 + 1]);
667 }
668 } else {
669 /*
670 * Write the init value for HW levling to occur
671 */
672 for (i = 21; i < 35; i++) {
673 writel(ext_phy_ctrl_const_regs[i],
674 &emif_ext_phy_ctrl_base[i * 2]);
675 writel(ext_phy_ctrl_const_regs[i],
676 &emif_ext_phy_ctrl_base[i * 2 + 1]);
677 }
678 }
679}
680
681void do_ext_phy_settings(u32 base, const struct emif_regs *regs)
682{
683 if (is_omap54xx())
684 do_ext_phy_settings_omap5(base, regs);
685 else
686 do_ext_phy_settings_dra7(base, regs);
687}
688
bb772a59
S		 689#ifndef CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
690static const struct lpddr2_ac_timings timings_jedec_532_mhz = {
691 .max_freq = 532000000,
692 .RL = 8,
693 .tRPab = 21,
694 .tRCD = 18,
695 .tWR = 15,
696 .tRASmin = 42,
697 .tRRD = 10,
698 .tWTRx2 = 15,
699 .tXSR = 140,
700 .tXPx2 = 15,
701 .tRFCab = 130,
702 .tRTPx2 = 15,
703 .tCKE = 3,
704 .tCKESR = 15,
705 .tZQCS = 90,
706 .tZQCL = 360,
707 .tZQINIT = 1000,
708 .tDQSCKMAXx2 = 11,
709 .tRASmax = 70,
710 .tFAW = 50
711};
712
971f2ba2 713static const struct lpddr2_min_tck min_tck = {
bb772a59
S		 714 .tRL = 3,
715 .tRP_AB = 3,
716 .tRCD = 3,
717 .tWR = 3,
718 .tRAS_MIN = 3,
719 .tRRD = 2,
720 .tWTR = 2,
721 .tXP = 2,
722 .tRTP = 2,
723 .tCKE = 3,
724 .tCKESR = 3,
725 .tFAW = 8
726};
727
971f2ba2 728static const struct lpddr2_ac_timings *ac_timings[MAX_NUM_SPEEDBINS] = {
bb772a59
S		 729 &timings_jedec_532_mhz
730};
731
971f2ba2
S		 732static const struct lpddr2_device_timings dev_4G_S4_timings = {
733 .ac_timings = ac_timings,
734 .min_tck = &min_tck,
bb772a59
S		 735};
736
54d022e7
S		 737/*
738 * List of status registers to be controlled back to control registers
739 * after initial leveling
740 * readreg, writereg
741 */
742const struct read_write_regs omap5_bug_00339_regs[] = {
743 { 8, 5 },
744 { 9, 6 },
745 { 10, 7 },
746 { 14, 8 },
747 { 15, 9 },
748 { 16, 10 },
749 { 11, 2 },
750 { 12, 3 },
751 { 13, 4 },
752 { 17, 11 },
753 { 18, 12 },
754 { 19, 13 },
755};
756
757const struct read_write_regs dra_bug_00339_regs[] = {
758 { 7, 7 },
759 { 8, 8 },
760 { 9, 9 },
761 { 10, 10 },
762 { 11, 11 },
763 { 12, 2 },
764 { 13, 3 },
765 { 14, 4 },
766 { 15, 5 },
767 { 16, 6 },
768 { 17, 12 },
769 { 18, 13 },
770 { 19, 14 },
771 { 20, 15 },
772 { 21, 16 },
773 { 22, 17 },
774 { 23, 18 },
775 { 24, 19 },
776 { 25, 20 },
777 { 26, 21}
778};
779
780const struct read_write_regs *get_bug_regs(u32 *iterations)
781{
782 const struct read_write_regs *bug_00339_regs_ptr = NULL;
783
784 switch (omap_revision()) {
785 case OMAP5430_ES1_0:
786 case OMAP5430_ES2_0:
787 case OMAP5432_ES1_0:
788 case OMAP5432_ES2_0:
789 bug_00339_regs_ptr = omap5_bug_00339_regs;
790 *iterations = sizeof(omap5_bug_00339_regs)/
791 sizeof(omap5_bug_00339_regs[0]);
792 break;
793 case DRA752_ES1_0:
3ac8c0bf 794 case DRA752_ES1_1:
9fcf3d3a 795 case DRA722_ES1_0:
54d022e7
S		 796 bug_00339_regs_ptr = dra_bug_00339_regs;
797 *iterations = sizeof(dra_bug_00339_regs)/
798 sizeof(dra_bug_00339_regs[0]);
799 break;
800 default:
801 printf("\n Error: UnKnown SOC");
802 }
803
804 return bug_00339_regs_ptr;
805}
806
bb772a59
S		 807void emif_get_device_timings_sdp(u32 emif_nr,
808 const struct lpddr2_device_timings **cs0_device_timings,
809 const struct lpddr2_device_timings **cs1_device_timings)
810{
811 /* Identical devices on EMIF1 & EMIF2 */
971f2ba2
S		 812 *cs0_device_timings = &dev_4G_S4_timings;
813 *cs1_device_timings = &dev_4G_S4_timings;
bb772a59
S		 814}
815
816void emif_get_device_timings(u32 emif_nr,
817 const struct lpddr2_device_timings **cs0_device_timings,
818 const struct lpddr2_device_timings **cs1_device_timings)
819 __attribute__((weak, alias("emif_get_device_timings_sdp")));
820
821#endif /* CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS */
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