[people/ms/u-boot.git] / arch / arm / mach-omap2 / omap3 / sys_info.c

/*
 * (C) Copyright 2008
 * Texas Instruments, <www.ti.com>
 *
 * Author :
 *      Manikandan Pillai <mani.pillai@ti.com>
 *
 * Derived from Beagle Board and 3430 SDP code by
 *      Richard Woodruff <r-woodruff2@ti.com>
 *      Syed Mohammed Khasim <khasim@ti.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <asm/io.h>
#include <asm/arch/mem.h>	/* get mem tables */
#include <asm/arch/sys_proto.h>
#include <asm/bootm.h>

#include <i2c.h>
#include <linux/compiler.h>

extern omap3_sysinfo sysinfo;
static struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE;

#ifdef CONFIG_DISPLAY_CPUINFO
static char *rev_s[CPU_3XX_MAX_REV] = {
				"1.0",
				"2.0",
				"2.1",
				"3.0",
				"3.1",
				"UNKNOWN",
				"UNKNOWN",
				"3.1.2"};

/* this is the revision table for 37xx CPUs */
static char *rev_s_37xx[CPU_37XX_MAX_REV] = {
				"1.0",
				"1.1",
				"1.2"};
#endif /* CONFIG_DISPLAY_CPUINFO */

void omap_die_id(unsigned int *die_id)
{
	struct ctrl_id *id_base = (struct ctrl_id *)OMAP34XX_ID_L4_IO_BASE;

	die_id[0] = readl(&id_base->die_id_0);
	die_id[1] = readl(&id_base->die_id_1);
	die_id[2] = readl(&id_base->die_id_2);
	die_id[3] = readl(&id_base->die_id_3);
}

/******************************************
 * get_cpu_type(void) - extract cpu info
 ******************************************/
u32 get_cpu_type(void)
{
	return readl(&ctrl_base->ctrl_omap_stat);
}

/******************************************
 * get_cpu_id(void) - extract cpu id
 * returns 0 for ES1.0, cpuid otherwise
 ******************************************/
u32 get_cpu_id(void)
{
	struct ctrl_id *id_base;
	u32 cpuid = 0;

	/*
	 * On ES1.0 the IDCODE register is not exposed on L4
	 * so using CPU ID to differentiate between ES1.0 and > ES1.0.
	 */
	__asm__ __volatile__("mrc p15, 0, %0, c0, c0, 0":"=r"(cpuid));
	if ((cpuid & 0xf) == 0x0) {
		return 0;
	} else {
		/* Decode the IDs on > ES1.0 */
		id_base = (struct ctrl_id *) OMAP34XX_ID_L4_IO_BASE;

		cpuid = readl(&id_base->idcode);
	}

	return cpuid;
}

/******************************************
 * get_cpu_family(void) - extract cpu info
 ******************************************/
u32 get_cpu_family(void)
{
	u16 hawkeye;
	u32 cpu_family;
	u32 cpuid = get_cpu_id();

	if (cpuid == 0)
		return CPU_OMAP34XX;

	hawkeye = (cpuid >> HAWKEYE_SHIFT) & 0xffff;
	switch (hawkeye) {
	case HAWKEYE_OMAP34XX:
		cpu_family = CPU_OMAP34XX;
		break;
	case HAWKEYE_AM35XX:
		cpu_family = CPU_AM35XX;
		break;
	case HAWKEYE_OMAP36XX:
		cpu_family = CPU_OMAP36XX;
		break;
	default:
		cpu_family = CPU_OMAP34XX;
	}

	return cpu_family;
}

/******************************************
 * get_cpu_rev(void) - extract version info
 ******************************************/
u32 get_cpu_rev(void)
{
	u32 cpuid = get_cpu_id();

	if (cpuid == 0)
		return CPU_3XX_ES10;
	else
		return (cpuid >> CPU_3XX_ID_SHIFT) & 0xf;
}

/*****************************************************************
 * get_sku_id(void) - read sku_id to get info on max clock rate
 *****************************************************************/
u32 get_sku_id(void)
{
	struct ctrl_id *id_base = (struct ctrl_id *)OMAP34XX_ID_L4_IO_BASE;
	return readl(&id_base->sku_id) & SKUID_CLK_MASK;
}

/***************************************************************************
 *  get_gpmc0_base() - Return current address hardware will be
 *     fetching from. The below effectively gives what is correct, its a bit
 *   mis-leading compared to the TRM.  For the most general case the mask
 *   needs to be also taken into account this does work in practice.
 *   - for u-boot we currently map:
 *       -- 0 to nothing,
 *       -- 4 to flash
 *       -- 8 to enent
 *       -- c to wifi
 ****************************************************************************/
u32 get_gpmc0_base(void)
{
	u32 b;

	b = readl(&gpmc_cfg->cs[0].config7);
	b &= 0x1F;		/* keep base [5:0] */
	b = b << 24;		/* ret 0x0b000000 */
	return b;
}

/*******************************************************************
 * get_gpmc0_width() - See if bus is in x8 or x16 (mainly for nand)
 *******************************************************************/
u32 get_gpmc0_width(void)
{
	return WIDTH_16BIT;
}

/*************************************************************************
 * get_board_rev() - setup to pass kernel board revision information
 * returns:(bit[0-3] sub version, higher bit[7-4] is higher version)
 *************************************************************************/
#ifdef CONFIG_REVISION_TAG
u32 __weak get_board_rev(void)
{
	return 0x20;
}
#endif

/********************************************************
 *  get_base(); get upper addr of current execution
 *******************************************************/
static u32 get_base(void)
{
	u32 val;

	__asm__ __volatile__("mov %0, pc \n":"=r"(val)::"memory");
	val &= 0xF0000000;
	val >>= 28;
	return val;
}

/********************************************************
 *  is_running_in_flash() - tell if currently running in
 *  FLASH.
 *******************************************************/
u32 is_running_in_flash(void)
{
	if (get_base() < 4)
		return 1;	/* in FLASH */

	return 0;		/* running in SRAM or SDRAM */
}

/********************************************************
 *  is_running_in_sram() - tell if currently running in
 *  SRAM.
 *******************************************************/
u32 is_running_in_sram(void)
{
	if (get_base() == 4)
		return 1;	/* in SRAM */

	return 0;		/* running in FLASH or SDRAM */
}

/********************************************************
 *  is_running_in_sdram() - tell if currently running in
 *  SDRAM.
 *******************************************************/
u32 is_running_in_sdram(void)
{
	if (get_base() > 4)
		return 1;	/* in SDRAM */

	return 0;		/* running in SRAM or FLASH */
}

/***************************************************************
 *  get_boot_type() - Is this an XIP type device or a stream one
 *  bits 4-0 specify type. Bit 5 says mem/perif
 ***************************************************************/
u32 get_boot_type(void)
{
	return (readl(&ctrl_base->status) & SYSBOOT_MASK);
}

/*************************************************************
 *  get_device_type(): tell if GP/HS/EMU/TST
 *************************************************************/
u32 get_device_type(void)
{
	return ((readl(&ctrl_base->status) & (DEVICE_MASK)) >> 8);
}

#ifdef CONFIG_DISPLAY_CPUINFO
/**
 * Print CPU information
 */
int print_cpuinfo (void)
{
	char *cpu_family_s, *cpu_s, *sec_s, *max_clk;

	switch (get_cpu_family()) {
	case CPU_OMAP34XX:
		cpu_family_s = "OMAP";
		switch (get_cpu_type()) {
		case OMAP3503:
			cpu_s = "3503";
			break;
		case OMAP3515:
			cpu_s = "3515";
			break;
		case OMAP3525:
			cpu_s = "3525";
			break;
		case OMAP3530:
			cpu_s = "3530";
			break;
		default:
			cpu_s = "35XX";
			break;
		}
		if ((get_cpu_rev() >= CPU_3XX_ES31) &&
		    (get_sku_id() == SKUID_CLK_720MHZ))
			max_clk = "720 MHz";
		else
			max_clk = "600 MHz";

		break;
	case CPU_AM35XX:
		cpu_family_s = "AM";
		switch (get_cpu_type()) {
		case AM3505:
			cpu_s = "3505";
			break;
		case AM3517:
			cpu_s = "3517";
			break;
		default:
			cpu_s = "35XX";
			break;
		}
		max_clk = "600 MHz";
		break;
	case CPU_OMAP36XX:
		switch (get_cpu_type()) {
		case AM3703:
			cpu_family_s = "AM";
			cpu_s = "3703";
			max_clk = "800 MHz";
			break;
		case AM3703_1GHZ:
			cpu_family_s = "AM";
			cpu_s = "3703";
			max_clk = "1 GHz";
			break;
		case AM3715:
			cpu_family_s = "AM";
			cpu_s = "3715";
			max_clk = "800 MHz";
			break;
		case AM3715_1GHZ:
			cpu_family_s = "AM";
			cpu_s = "3715";
			max_clk = "1 GHz";
			break;
		case OMAP3725:
			cpu_family_s = "OMAP";
			cpu_s = "3625/3725";
			max_clk = "800 MHz";
			break;
		case OMAP3725_1GHZ:
			cpu_family_s = "OMAP";
			cpu_s = "3625/3725";
			max_clk = "1 GHz";
			break;
		case OMAP3730:
			cpu_family_s = "OMAP";
			cpu_s = "3630/3730";
			max_clk = "800 MHz";
			break;
		case OMAP3730_1GHZ:
			cpu_family_s = "OMAP";
			cpu_s = "3630/3730";
			max_clk = "1 GHz";
			break;
		default:
			cpu_family_s = "OMAP/AM";
			cpu_s = "36XX/37XX";
			max_clk = "1 GHz";
			break;
		}

		break;
	default:
		cpu_family_s = "OMAP";
		cpu_s = "35XX";
		max_clk = "600 MHz";
	}

	switch (get_device_type()) {
	case TST_DEVICE:
		sec_s = "TST";
		break;
	case EMU_DEVICE:
		sec_s = "EMU";
		break;
	case HS_DEVICE:
		sec_s = "HS";
		break;
	case GP_DEVICE:
		sec_s = "GP";
		break;
	default:
		sec_s = "?";
	}

	if (CPU_OMAP36XX == get_cpu_family())
		printf("%s%s-%s ES%s, CPU-OPP2, L3-200MHz, Max CPU Clock %s\n",
		       cpu_family_s, cpu_s, sec_s,
		       rev_s_37xx[get_cpu_rev()], max_clk);
	else
		printf("%s%s-%s ES%s, CPU-OPP2, L3-165MHz, Max CPU Clock %s\n",
			cpu_family_s, cpu_s, sec_s,
			rev_s[get_cpu_rev()], max_clk);

	return 0;
}
#endif	/* CONFIG_DISPLAY_CPUINFO */
Commit	Line	Data
91eee546 DB	1	/*
	2	* (C) Copyright 2008
	3	* Texas Instruments, <www.ti.com>
	4	*
	5	* Author :
	6	* Manikandan Pillai <mani.pillai@ti.com>
	7	*
	8	* Derived from Beagle Board and 3430 SDP code by
	9	* Richard Woodruff <r-woodruff2@ti.com>
	10	* Syed Mohammed Khasim <khasim@ti.com>
	11	*
1a459660	12	* SPDX-License-Identifier: GPL-2.0+
91eee546 DB	13	*/
	14
	15	#include <common.h>
	16	#include <asm/io.h>
	17	#include <asm/arch/mem.h> /* get mem tables */
	18	#include <asm/arch/sys_proto.h>
bf855028 JH	19	#include <asm/bootm.h>
bf855028 JH	20
91eee546	21	#include <i2c.h>
715462dd	22	#include <linux/compiler.h>
91eee546 DB	23
91eee546 DB	24	extern omap3_sysinfo sysinfo;
97a099ea	25	static struct ctrl ctrl_base = (struct ctrl )OMAP34XX_CTRL_BASE;
80bb756d SP	26
80bb756d SP	27	#ifdef CONFIG_DISPLAY_CPUINFO
cba0b778 SP	28	static char *rev_s[CPU_3XX_MAX_REV] = {
	29	"1.0",
	30	"2.0",
	31	"2.1",
	32	"3.0",
b2b9169f SS	33	"3.1",
	34	"UNKNOWN",
	35	"UNKNOWN",
	36	"3.1.2"};
91eee546	37
32b58ce7 HG	38	/* this is the revision table for 37xx CPUs */
	39	static char *rev_s_37xx[CPU_37XX_MAX_REV] = {
	40	"1.0",
	41	"1.1",
	42	"1.2"};
939e7222	43	#endif /* CONFIG_DISPLAY_CPUINFO */
32b58ce7	44
b50a7685	45	void omap_die_id(unsigned int *die_id)
79e7e87f NM	46	{
	47	struct ctrl_id id_base = (struct ctrl_id )OMAP34XX_ID_L4_IO_BASE;
	48
b50a7685 PK	49	die_id[0] = readl(&id_base->die_id_0);
	50	die_id[1] = readl(&id_base->die_id_1);
	51	die_id[2] = readl(&id_base->die_id_2);
	52	die_id[3] = readl(&id_base->die_id_3);
79e7e87f NM	53	}
79e7e87f NM	54
6530a8bf DB	55	/******************************************
	56	* get_cpu_type(void) - extract cpu info
	57	******************************************/
	58	u32 get_cpu_type(void)
	59	{
	60	return readl(&ctrl_base->ctrl_omap_stat);
	61	}
	62
91eee546	63	/******************************************
b2b9169f SS	64	* get_cpu_id(void) - extract cpu id
b2b9169f SS	65	* returns 0 for ES1.0, cpuid otherwise
91eee546	66	******************************************/
b2b9169f	67	u32 get_cpu_id(void)
91eee546	68	{
97a099ea	69	struct ctrl_id *id_base;
b2b9169f	70	u32 cpuid = 0;
91eee546 DB	71
	72	/*
	73	* On ES1.0 the IDCODE register is not exposed on L4
cba0b778	74	* so using CPU ID to differentiate between ES1.0 and > ES1.0.
91eee546 DB	75	*/
91eee546 DB	76	__asm__ __volatile__("mrc p15, 0, %0, c0, c0, 0":"=r"(cpuid));
b2b9169f SS	77	if ((cpuid & 0xf) == 0x0) {
	78	return 0;
	79	} else {
cba0b778	80	/* Decode the IDs on > ES1.0 */
97a099ea	81	id_base = (struct ctrl_id *) OMAP34XX_ID_L4_IO_BASE;
91eee546	82
b2b9169f SS	83	cpuid = readl(&id_base->idcode);
b2b9169f SS	84	}
cba0b778	85
b2b9169f SS	86	return cpuid;
b2b9169f SS	87	}
cba0b778	88
b2b9169f SS	89	/******************************************
	90	* get_cpu_family(void) - extract cpu info
	91	******************************************/
	92	u32 get_cpu_family(void)
	93	{
	94	u16 hawkeye;
	95	u32 cpu_family;
	96	u32 cpuid = get_cpu_id();
	97
	98	if (cpuid == 0)
	99	return CPU_OMAP34XX;
	100
	101	hawkeye = (cpuid >> HAWKEYE_SHIFT) & 0xffff;
	102	switch (hawkeye) {
	103	case HAWKEYE_OMAP34XX:
	104	cpu_family = CPU_OMAP34XX;
	105	break;
	106	case HAWKEYE_AM35XX:
	107	cpu_family = CPU_AM35XX;
	108	break;
	109	case HAWKEYE_OMAP36XX:
	110	cpu_family = CPU_OMAP36XX;
	111	break;
	112	default:
	113	cpu_family = CPU_OMAP34XX;
cba0b778	114	}
b2b9169f SS	115
	116	return cpu_family;
	117	}
	118
	119	/******************************************
	120	* get_cpu_rev(void) - extract version info
	121	******************************************/
	122	u32 get_cpu_rev(void)
	123	{
	124	u32 cpuid = get_cpu_id();
	125
	126	if (cpuid == 0)
	127	return CPU_3XX_ES10;
	128	else
	129	return (cpuid >> CPU_3XX_ID_SHIFT) & 0xf;
	130	}
	131
	132	/*****************************************************************
	133	* get_sku_id(void) - read sku_id to get info on max clock rate
	134	*****************************************************************/
	135	u32 get_sku_id(void)
	136	{
	137	struct ctrl_id id_base = (struct ctrl_id )OMAP34XX_ID_L4_IO_BASE;
	138	return readl(&id_base->sku_id) & SKUID_CLK_MASK;
91eee546 DB	139	}
91eee546 DB	140
91eee546 DB	141	/***************************************************************************
	142	* get_gpmc0_base() - Return current address hardware will be
	143	* fetching from. The below effectively gives what is correct, its a bit
	144	* mis-leading compared to the TRM. For the most general case the mask
	145	* needs to be also taken into account this does work in practice.
	146	* - for u-boot we currently map:
	147	* -- 0 to nothing,
	148	* -- 4 to flash
	149	* -- 8 to enent
	150	* -- c to wifi
	151	****************************************************************************/
	152	u32 get_gpmc0_base(void)
	153	{
	154	u32 b;
	155
89411352	156	b = readl(&gpmc_cfg->cs[0].config7);
91eee546 DB	157	b &= 0x1F; /* keep base [5:0] */
	158	b = b << 24; /* ret 0x0b000000 */
	159	return b;
	160	}
	161
	162	/*******************************************************************
	163	* get_gpmc0_width() - See if bus is in x8 or x16 (mainly for nand)
	164	*******************************************************************/
	165	u32 get_gpmc0_width(void)
	166	{
	167	return WIDTH_16BIT;
	168	}
	169
	170	/*************************************************************************
	171	* get_board_rev() - setup to pass kernel board revision information
	172	* returns:(bit[0-3] sub version, higher bit[7-4] is higher version)
	173	*************************************************************************/
fb9006c3	174	#ifdef CONFIG_REVISION_TAG
715462dd	175	u32 __weak get_board_rev(void)
91eee546 DB	176	{
	177	return 0x20;
	178	}
fb9006c3	179	#endif
91eee546	180
91eee546 DB	181	/********************************************************
	182	* get_base(); get upper addr of current execution
	183	*******************************************************/
98431d58	184	static u32 get_base(void)
91eee546 DB	185	{
	186	u32 val;
	187
	188	__asm__ __volatile__("mov %0, pc \n":"=r"(val)::"memory");
	189	val &= 0xF0000000;
	190	val >>= 28;
	191	return val;
	192	}
	193
	194	/********************************************************
	195	* is_running_in_flash() - tell if currently running in
	196	* FLASH.
	197	*******************************************************/
	198	u32 is_running_in_flash(void)
	199	{
	200	if (get_base() < 4)
	201	return 1; /* in FLASH */
	202
	203	return 0; /* running in SRAM or SDRAM */
	204	}
	205
	206	/********************************************************
	207	* is_running_in_sram() - tell if currently running in
	208	* SRAM.
	209	*******************************************************/
	210	u32 is_running_in_sram(void)
	211	{
	212	if (get_base() == 4)
	213	return 1; /* in SRAM */
	214
	215	return 0; /* running in FLASH or SDRAM */
	216	}
	217
	218	/********************************************************
	219	* is_running_in_sdram() - tell if currently running in
	220	* SDRAM.
	221	*******************************************************/
	222	u32 is_running_in_sdram(void)
	223	{
	224	if (get_base() > 4)
	225	return 1; /* in SDRAM */
	226
	227	return 0; /* running in SRAM or FLASH */
	228	}
	229
	230	/***************************************************************
	231	* get_boot_type() - Is this an XIP type device or a stream one
	232	* bits 4-0 specify type. Bit 5 says mem/perif
	233	***************************************************************/
	234	u32 get_boot_type(void)
	235	{
	236	return (readl(&ctrl_base->status) & SYSBOOT_MASK);
	237	}
	238
	239	/*************************************************************
	240	* get_device_type(): tell if GP/HS/EMU/TST
	241	*************************************************************/
	242	u32 get_device_type(void)
	243	{
	244	return ((readl(&ctrl_base->status) & (DEVICE_MASK)) >> 8);
	245	}
6a6b62e3 SP	246
	247	#ifdef CONFIG_DISPLAY_CPUINFO
	248	/**
	249	* Print CPU information
	250	*/
	251	int print_cpuinfo (void)
	252	{
b2b9169f SS	253	char cpu_family_s, cpu_s, sec_s, max_clk;
	254
	255	switch (get_cpu_family()) {
	256	case CPU_OMAP34XX:
	257	cpu_family_s = "OMAP";
	258	switch (get_cpu_type()) {
	259	case OMAP3503:
	260	cpu_s = "3503";
	261	break;
	262	case OMAP3515:
	263	cpu_s = "3515";
	264	break;
	265	case OMAP3525:
	266	cpu_s = "3525";
	267	break;
	268	case OMAP3530:
	269	cpu_s = "3530";
	270	break;
	271	default:
	272	cpu_s = "35XX";
	273	break;
	274	}
	275	if ((get_cpu_rev() >= CPU_3XX_ES31) &&
	276	(get_sku_id() == SKUID_CLK_720MHZ))
9d0fd10c	277	max_clk = "720 MHz";
b2b9169f	278	else
9d0fd10c	279	max_clk = "600 MHz";
6a6b62e3	280
6a6b62e3	281	break;
b2b9169f SS	282	case CPU_AM35XX:
	283	cpu_family_s = "AM";
	284	switch (get_cpu_type()) {
	285	case AM3505:
	286	cpu_s = "3505";
	287	break;
	288	case AM3517:
	289	cpu_s = "3517";
	290	break;
	291	default:
	292	cpu_s = "35XX";
	293	break;
	294	}
d5c9d4fb	295	max_clk = "600 MHz";
6a6b62e3	296	break;
b2b9169f	297	case CPU_OMAP36XX:
b2b9169f	298	switch (get_cpu_type()) {
7f668a6f AF	299	case AM3703:
	300	cpu_family_s = "AM";
	301	cpu_s = "3703";
	302	max_clk = "800 MHz";
	303	break;
	304	case AM3703_1GHZ:
	305	cpu_family_s = "AM";
	306	cpu_s = "3703";
	307	max_clk = "1 GHz";
	308	break;
	309	case AM3715:
	310	cpu_family_s = "AM";
	311	cpu_s = "3715";
	312	max_clk = "800 MHz";
	313	break;
	314	case AM3715_1GHZ:
	315	cpu_family_s = "AM";
	316	cpu_s = "3715";
	317	max_clk = "1 GHz";
	318	break;
	319	case OMAP3725:
	320	cpu_family_s = "OMAP";
	321	cpu_s = "3625/3725";
	322	max_clk = "800 MHz";
	323	break;
	324	case OMAP3725_1GHZ:
	325	cpu_family_s = "OMAP";
	326	cpu_s = "3625/3725";
	327	max_clk = "1 GHz";
	328	break;
b2b9169f	329	case OMAP3730:
7f668a6f	330	cpu_family_s = "OMAP";
b2b9169f	331	cpu_s = "3630/3730";
7f668a6f AF	332	max_clk = "800 MHz";
	333	break;
	334	case OMAP3730_1GHZ:
	335	cpu_family_s = "OMAP";
	336	cpu_s = "3630/3730";
	337	max_clk = "1 GHz";
b2b9169f SS	338	break;
b2b9169f SS	339	default:
7f668a6f	340	cpu_family_s = "OMAP/AM";
b2b9169f	341	cpu_s = "36XX/37XX";
7f668a6f	342	max_clk = "1 GHz";
b2b9169f SS	343	break;
b2b9169f SS	344	}
7f668a6f	345
6a6b62e3 SP	346	break;
6a6b62e3 SP	347	default:
b2b9169f	348	cpu_family_s = "OMAP";
6a6b62e3	349	cpu_s = "35XX";
d5c9d4fb	350	max_clk = "600 MHz";
6a6b62e3 SP	351	}
	352
	353	switch (get_device_type()) {
	354	case TST_DEVICE:
	355	sec_s = "TST";
	356	break;
	357	case EMU_DEVICE:
	358	sec_s = "EMU";
	359	break;
	360	case HS_DEVICE:
	361	sec_s = "HS";
	362	break;
	363	case GP_DEVICE:
	364	sec_s = "GP";
	365	break;
	366	default:
	367	sec_s = "?";
	368	}
	369
32b58ce7	370	if (CPU_OMAP36XX == get_cpu_family())
c4ec2818 AB	371	printf("%s%s-%s ES%s, CPU-OPP2, L3-200MHz, Max CPU Clock %s\n",
	372	cpu_family_s, cpu_s, sec_s,
	373	rev_s_37xx[get_cpu_rev()], max_clk);
32b58ce7 HG	374	else
32b58ce7 HG	375	printf("%s%s-%s ES%s, CPU-OPP2, L3-165MHz, Max CPU Clock %s\n",
b2b9169f SS	376	cpu_family_s, cpu_s, sec_s,
b2b9169f SS	377	rev_s[get_cpu_rev()], max_clk);
6a6b62e3 SP	378
	379	return 0;
	380	}
	381	#endif /* CONFIG_DISPLAY_CPUINFO */