[people/ms/u-boot.git] / arch / arm / mach-sunxi / board.c

/*
 * (C) Copyright 2012 Henrik Nordstrom <henrik@henriknordstrom.net>
 *
 * (C) Copyright 2007-2011
 * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
 * Tom Cubie <tangliang@allwinnertech.com>
 *
 * Some init for sunxi platform.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <mmc.h>
#include <i2c.h>
#include <serial.h>
#ifdef CONFIG_SPL_BUILD
#include <spl.h>
#endif
#include <asm/gpio.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/gpio.h>
#include <asm/arch/spl.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/timer.h>
#include <asm/arch/tzpc.h>
#include <asm/arch/mmc.h>

#include <linux/compiler.h>

struct fel_stash {
	uint32_t sp;
	uint32_t lr;
	uint32_t cpsr;
	uint32_t sctlr;
	uint32_t vbar;
	uint32_t cr;
};

struct fel_stash fel_stash __attribute__((section(".data")));

#ifdef CONFIG_MACH_SUN50I
#include <asm/armv8/mmu.h>

static struct mm_region sunxi_mem_map[] = {
	{
		/* SRAM, MMIO regions */
		.base = 0x0UL,
		.size = 0x40000000UL,
		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
			 PTE_BLOCK_NON_SHARE
	}, {
		/* RAM */
		.base = 0x40000000UL,
		.size = 0x80000000UL,
		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
			 PTE_BLOCK_INNER_SHARE
	}, {
		/* List terminator */
		0,
	}
};
struct mm_region *mem_map = sunxi_mem_map;
#endif

static int gpio_init(void)
{
#if CONFIG_CONS_INDEX == 1 && defined(CONFIG_UART0_PORT_F)
#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I)
	/* disable GPB22,23 as uart0 tx,rx to avoid conflict */
	sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUNXI_GPIO_INPUT);
	sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUNXI_GPIO_INPUT);
#endif
#if defined(CONFIG_MACH_SUN8I)
	sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUN8I_GPF_UART0);
	sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUN8I_GPF_UART0);
#else
	sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUNXI_GPF_UART0);
	sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUNXI_GPF_UART0);
#endif
	sunxi_gpio_set_pull(SUNXI_GPF(4), 1);
#elif CONFIG_CONS_INDEX == 1 && (defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I))
	sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUN4I_GPB_UART0);
	sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUN4I_GPB_UART0);
	sunxi_gpio_set_pull(SUNXI_GPB(23), SUNXI_GPIO_PULL_UP);
#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN5I)
	sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN5I_GPB_UART0);
	sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN5I_GPB_UART0);
	sunxi_gpio_set_pull(SUNXI_GPB(20), SUNXI_GPIO_PULL_UP);
#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN6I)
	sunxi_gpio_set_cfgpin(SUNXI_GPH(20), SUN6I_GPH_UART0);
	sunxi_gpio_set_cfgpin(SUNXI_GPH(21), SUN6I_GPH_UART0);
	sunxi_gpio_set_pull(SUNXI_GPH(21), SUNXI_GPIO_PULL_UP);
#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_A33)
	sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN8I_A33_GPB_UART0);
	sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN8I_A33_GPB_UART0);
	sunxi_gpio_set_pull(SUNXI_GPB(1), SUNXI_GPIO_PULL_UP);
#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_H3)
	sunxi_gpio_set_cfgpin(SUNXI_GPA(4), SUN8I_H3_GPA_UART0);
	sunxi_gpio_set_cfgpin(SUNXI_GPA(5), SUN8I_H3_GPA_UART0);
	sunxi_gpio_set_pull(SUNXI_GPA(5), SUNXI_GPIO_PULL_UP);
#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN50I)
	sunxi_gpio_set_cfgpin(SUNXI_GPB(8), SUN50I_GPB_UART0);
	sunxi_gpio_set_cfgpin(SUNXI_GPB(9), SUN50I_GPB_UART0);
	sunxi_gpio_set_pull(SUNXI_GPB(9), SUNXI_GPIO_PULL_UP);
#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_A83T)
	sunxi_gpio_set_cfgpin(SUNXI_GPB(9), SUN8I_A83T_GPB_UART0);
	sunxi_gpio_set_cfgpin(SUNXI_GPB(10), SUN8I_A83T_GPB_UART0);
	sunxi_gpio_set_pull(SUNXI_GPB(10), SUNXI_GPIO_PULL_UP);
#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN9I)
	sunxi_gpio_set_cfgpin(SUNXI_GPH(12), SUN9I_GPH_UART0);
	sunxi_gpio_set_cfgpin(SUNXI_GPH(13), SUN9I_GPH_UART0);
	sunxi_gpio_set_pull(SUNXI_GPH(13), SUNXI_GPIO_PULL_UP);
#elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_MACH_SUN5I)
	sunxi_gpio_set_cfgpin(SUNXI_GPG(3), SUN5I_GPG_UART1);
	sunxi_gpio_set_cfgpin(SUNXI_GPG(4), SUN5I_GPG_UART1);
	sunxi_gpio_set_pull(SUNXI_GPG(4), SUNXI_GPIO_PULL_UP);
#elif CONFIG_CONS_INDEX == 3 && defined(CONFIG_MACH_SUN8I)
	sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN8I_GPB_UART2);
	sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN8I_GPB_UART2);
	sunxi_gpio_set_pull(SUNXI_GPB(1), SUNXI_GPIO_PULL_UP);
#elif CONFIG_CONS_INDEX == 5 && defined(CONFIG_MACH_SUN8I)
	sunxi_gpio_set_cfgpin(SUNXI_GPL(2), SUN8I_GPL_R_UART);
	sunxi_gpio_set_cfgpin(SUNXI_GPL(3), SUN8I_GPL_R_UART);
	sunxi_gpio_set_pull(SUNXI_GPL(3), SUNXI_GPIO_PULL_UP);
#else
#error Unsupported console port number. Please fix pin mux settings in board.c
#endif

	return 0;
}

int spl_board_load_image(void)
{
	debug("Returning to FEL sp=%x, lr=%x\n", fel_stash.sp, fel_stash.lr);
	return_to_fel(fel_stash.sp, fel_stash.lr);

	return 0;
}

void s_init(void)
{
	/*
	 * Undocumented magic taken from boot0, without this DRAM
	 * access gets messed up (seems cache related).
	 * The boot0 sources describe this as: "config ema for cache sram"
	 */
#if defined CONFIG_MACH_SUN6I
	setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0x1800);
#elif defined CONFIG_MACH_SUN8I
	__maybe_unused uint version;

	/* Unlock sram version info reg, read it, relock */
	setbits_le32(SUNXI_SRAMC_BASE + 0x24, (1 << 15));
	version = readl(SUNXI_SRAMC_BASE + 0x24) >> 16;
	clrbits_le32(SUNXI_SRAMC_BASE + 0x24, (1 << 15));

	/*
	 * Ideally this would be a switch case, but we do not know exactly
	 * which versions there are and which version needs which settings,
	 * so reproduce the per SoC code from the BSP.
	 */
#if defined CONFIG_MACH_SUN8I_A23
	if (version == 0x1650)
		setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0x1800);
	else /* 0x1661 ? */
		setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0xc0);
#elif defined CONFIG_MACH_SUN8I_A33
	if (version != 0x1667)
		setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0xc0);
#endif
	/* A83T BSP never modifies SUNXI_SRAMC_BASE + 0x44 */
	/* No H3 BSP, boot0 seems to not modify SUNXI_SRAMC_BASE + 0x44 */
#endif

#if defined CONFIG_MACH_SUN6I || \
    defined CONFIG_MACH_SUN7I || \
    defined CONFIG_MACH_SUN8I
	/* Enable SMP mode for CPU0, by setting bit 6 of Auxiliary Ctl reg */
	asm volatile(
		"mrc p15, 0, r0, c1, c0, 1\n"
		"orr r0, r0, #1 << 6\n"
		"mcr p15, 0, r0, c1, c0, 1\n");
#endif
#if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I_H3
	/* Enable non-secure access to some peripherals */
	tzpc_init();
#endif

	clock_init();
	timer_init();
	gpio_init();
	i2c_init_board();
	eth_init_board();
}

#ifdef CONFIG_SPL_BUILD
DECLARE_GLOBAL_DATA_PTR;

/* The sunxi internal brom will try to loader external bootloader
 * from mmc0, nand flash, mmc2.
 */
u32 spl_boot_device(void)
{
	__maybe_unused struct mmc *mmc0, *mmc1;
	/*
	 * When booting from the SD card or NAND memory, the "eGON.BT0"
	 * signature is expected to be found in memory at the address 0x0004
	 * (see the "mksunxiboot" tool, which generates this header).
	 *
	 * When booting in the FEL mode over USB, this signature is patched in
	 * memory and replaced with something else by the 'fel' tool. This other
	 * signature is selected in such a way, that it can't be present in a
	 * valid bootable SD card image (because the BROM would refuse to
	 * execute the SPL in this case).
	 *
	 * This checks for the signature and if it is not found returns to
	 * the FEL code in the BROM to wait and receive the main u-boot
	 * binary over USB. If it is found, it determines where SPL was
	 * read from.
	 */
	if (!is_boot0_magic(SPL_ADDR + 4)) /* eGON.BT0 */
		return BOOT_DEVICE_BOARD;

	/* The BROM will try to boot from mmc0 first, so try that first. */
#ifdef CONFIG_MMC
	mmc_initialize(gd->bd);
	mmc0 = find_mmc_device(0);
	if (sunxi_mmc_has_egon_boot_signature(mmc0))
		return BOOT_DEVICE_MMC1;
#endif

	/* Fallback to booting NAND if enabled. */
	if (IS_ENABLED(CONFIG_SPL_NAND_SUPPORT))
		return BOOT_DEVICE_NAND;

#ifdef CONFIG_MMC
	if (CONFIG_MMC_SUNXI_SLOT_EXTRA == 2) {
		mmc1 = find_mmc_device(1);
		if (sunxi_mmc_has_egon_boot_signature(mmc1))
			return BOOT_DEVICE_MMC2;
	}
#endif

	panic("Could not determine boot source\n");
	return -1;		/* Never reached */
}

/*
 * Properly announce BOOT_DEVICE_BOARD as "FEL".
 * Overrides weak function from common/spl/spl.c
 */
void spl_board_announce_boot_device(void)
{
	printf("FEL");
}

/* No confirmation data available in SPL yet. Hardcode bootmode */
u32 spl_boot_mode(const u32 boot_device)
{
	return MMCSD_MODE_RAW;
}

void board_init_f(ulong dummy)
{
	spl_init();
	preloader_console_init();

#ifdef CONFIG_SPL_I2C_SUPPORT
	/* Needed early by sunxi_board_init if PMU is enabled */
	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
#endif
	sunxi_board_init();
}
#endif

void reset_cpu(ulong addr)
{
#ifdef CONFIG_SUNXI_GEN_SUN4I
	static const struct sunxi_wdog *wdog =
		 &((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog;

	/* Set the watchdog for its shortest interval (.5s) and wait */
	writel(WDT_MODE_RESET_EN | WDT_MODE_EN, &wdog->mode);
	writel(WDT_CTRL_KEY | WDT_CTRL_RESTART, &wdog->ctl);

	while (1) {
		/* sun5i sometimes gets stuck without this */
		writel(WDT_MODE_RESET_EN | WDT_MODE_EN, &wdog->mode);
	}
#endif
#ifdef CONFIG_SUNXI_GEN_SUN6I
	static const struct sunxi_wdog *wdog =
		 ((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog;

	/* Set the watchdog for its shortest interval (.5s) and wait */
	writel(WDT_CFG_RESET, &wdog->cfg);
	writel(WDT_MODE_EN, &wdog->mode);
	writel(WDT_CTRL_KEY | WDT_CTRL_RESTART, &wdog->ctl);
	while (1) { }
#endif
}

#if !defined(CONFIG_SYS_DCACHE_OFF) && !defined(CONFIG_ARM64)
void enable_caches(void)
{
	/* Enable D-cache. I-cache is already enabled in start.S */
	dcache_enable();
}
#endif
Commit	Line	Data
cba69eee IC	1	/*
	2	* (C) Copyright 2012 Henrik Nordstrom <henrik@henriknordstrom.net>
	3	*
	4	* (C) Copyright 2007-2011
	5	* Allwinner Technology Co., Ltd. <www.allwinnertech.com>
	6	* Tom Cubie <tangliang@allwinnertech.com>
	7	*
	8	* Some init for sunxi platform.
	9	*
	10	* SPDX-License-Identifier: GPL-2.0+
	11	*/
	12
	13	#include <common.h>
a151403f	14	#include <mmc.h>
6620377e	15	#include <i2c.h>
cba69eee IC	16	#include <serial.h>
	17	#ifdef CONFIG_SPL_BUILD
	18	#include <spl.h>
	19	#endif
	20	#include <asm/gpio.h>
	21	#include <asm/io.h>
	22	#include <asm/arch/clock.h>
	23	#include <asm/arch/gpio.h>
af654d14	24	#include <asm/arch/spl.h>
cba69eee IC	25	#include <asm/arch/sys_proto.h>
cba69eee IC	26	#include <asm/arch/timer.h>
92369844	27	#include <asm/arch/tzpc.h>
a151403f	28	#include <asm/arch/mmc.h>
cba69eee	29
799aff38 IC	30	#include <linux/compiler.h>
799aff38 IC	31
942cb0b6 SG	32	struct fel_stash {
	33	uint32_t sp;
	34	uint32_t lr;
840fe95c SS	35	uint32_t cpsr;
	36	uint32_t sctlr;
	37	uint32_t vbar;
	38	uint32_t cr;
942cb0b6 SG	39	};
	40
	41	struct fel_stash fel_stash __attribute__((section(".data")));
	42
d96ebc46 SS	43	#ifdef CONFIG_MACH_SUN50I
	44	#include <asm/armv8/mmu.h>
	45
	46	static struct mm_region sunxi_mem_map[] = {
	47	{
	48	/* SRAM, MMIO regions */
	49	.base = 0x0UL,
	50	.size = 0x40000000UL,
	51	.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) \|
	52	PTE_BLOCK_NON_SHARE
	53	}, {
	54	/* RAM */
	55	.base = 0x40000000UL,
	56	.size = 0x80000000UL,
	57	.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) \|
	58	PTE_BLOCK_INNER_SHARE
	59	}, {
	60	/* List terminator */
	61	0,
	62	}
	63	};
	64	struct mm_region *mem_map = sunxi_mem_map;
	65	#endif
	66
f630974c	67	static int gpio_init(void)
cba69eee	68	{
ff2b47f6	69	#if CONFIG_CONS_INDEX == 1 && defined(CONFIG_UART0_PORT_F)
ed41e62f	70	#if defined(CONFIG_MACH_SUN4I) \|\| defined(CONFIG_MACH_SUN7I)
ff2b47f6 CYT	71	/* disable GPB22,23 as uart0 tx,rx to avoid conflict */
	72	sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUNXI_GPIO_INPUT);
	73	sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUNXI_GPIO_INPUT);
	74	#endif
487b3277	75	#if defined(CONFIG_MACH_SUN8I)
6ad8c743 CYT	76	sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUN8I_GPF_UART0);
6ad8c743 CYT	77	sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUN8I_GPF_UART0);
487b3277	78	#else
6ad8c743 CYT	79	sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUNXI_GPF_UART0);
6ad8c743 CYT	80	sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUNXI_GPF_UART0);
487b3277	81	#endif
ff2b47f6	82	sunxi_gpio_set_pull(SUNXI_GPF(4), 1);
ed41e62f	83	#elif CONFIG_CONS_INDEX == 1 && (defined(CONFIG_MACH_SUN4I) \|\| defined(CONFIG_MACH_SUN7I))
487b3277 PK	84	sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUN4I_GPB_UART0);
487b3277 PK	85	sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUN4I_GPB_UART0);
ea520947	86	sunxi_gpio_set_pull(SUNXI_GPB(23), SUNXI_GPIO_PULL_UP);
ed41e62f	87	#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN5I)
487b3277 PK	88	sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN5I_GPB_UART0);
487b3277 PK	89	sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN5I_GPB_UART0);
ea520947	90	sunxi_gpio_set_pull(SUNXI_GPB(20), SUNXI_GPIO_PULL_UP);
ed41e62f	91	#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN6I)
487b3277 PK	92	sunxi_gpio_set_cfgpin(SUNXI_GPH(20), SUN6I_GPH_UART0);
487b3277 PK	93	sunxi_gpio_set_cfgpin(SUNXI_GPH(21), SUN6I_GPH_UART0);
77115397	94	sunxi_gpio_set_pull(SUNXI_GPH(21), SUNXI_GPIO_PULL_UP);
e506889c CYT	95	#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_A33)
	96	sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN8I_A33_GPB_UART0);
	97	sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN8I_A33_GPB_UART0);
	98	sunxi_gpio_set_pull(SUNXI_GPB(1), SUNXI_GPIO_PULL_UP);
1c27b7dc JK	99	#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_H3)
	100	sunxi_gpio_set_cfgpin(SUNXI_GPA(4), SUN8I_H3_GPA_UART0);
	101	sunxi_gpio_set_cfgpin(SUNXI_GPA(5), SUN8I_H3_GPA_UART0);
	102	sunxi_gpio_set_pull(SUNXI_GPA(5), SUNXI_GPIO_PULL_UP);
d96ebc46 SS	103	#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN50I)
	104	sunxi_gpio_set_cfgpin(SUNXI_GPB(8), SUN50I_GPB_UART0);
	105	sunxi_gpio_set_cfgpin(SUNXI_GPB(9), SUN50I_GPB_UART0);
	106	sunxi_gpio_set_pull(SUNXI_GPB(9), SUNXI_GPIO_PULL_UP);
d5a3357f	107	#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_A83T)
	108	sunxi_gpio_set_cfgpin(SUNXI_GPB(9), SUN8I_A83T_GPB_UART0);
	109	sunxi_gpio_set_cfgpin(SUNXI_GPB(10), SUN8I_A83T_GPB_UART0);
	110	sunxi_gpio_set_pull(SUNXI_GPB(10), SUNXI_GPIO_PULL_UP);
1871a8ca HG	111	#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN9I)
	112	sunxi_gpio_set_cfgpin(SUNXI_GPH(12), SUN9I_GPH_UART0);
	113	sunxi_gpio_set_cfgpin(SUNXI_GPH(13), SUN9I_GPH_UART0);
	114	sunxi_gpio_set_pull(SUNXI_GPH(13), SUNXI_GPIO_PULL_UP);
ed41e62f	115	#elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_MACH_SUN5I)
487b3277 PK	116	sunxi_gpio_set_cfgpin(SUNXI_GPG(3), SUN5I_GPG_UART1);
487b3277 PK	117	sunxi_gpio_set_cfgpin(SUNXI_GPG(4), SUN5I_GPG_UART1);
ea520947	118	sunxi_gpio_set_pull(SUNXI_GPG(4), SUNXI_GPIO_PULL_UP);
5cd83b11 LI	119	#elif CONFIG_CONS_INDEX == 3 && defined(CONFIG_MACH_SUN8I)
	120	sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN8I_GPB_UART2);
	121	sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN8I_GPB_UART2);
	122	sunxi_gpio_set_pull(SUNXI_GPB(1), SUNXI_GPIO_PULL_UP);
ed41e62f	123	#elif CONFIG_CONS_INDEX == 5 && defined(CONFIG_MACH_SUN8I)
487b3277 PK	124	sunxi_gpio_set_cfgpin(SUNXI_GPL(2), SUN8I_GPL_R_UART);
487b3277 PK	125	sunxi_gpio_set_cfgpin(SUNXI_GPL(3), SUN8I_GPL_R_UART);
c757a50b	126	sunxi_gpio_set_pull(SUNXI_GPL(3), SUNXI_GPIO_PULL_UP);
f84269c5 HG	127	#else
	128	#error Unsupported console port number. Please fix pin mux settings in board.c
	129	#endif
cba69eee IC	130
	131	return 0;
	132	}
	133
36afd451	134	int spl_board_load_image(void)
942cb0b6 SG	135	{
	136	debug("Returning to FEL sp=%x, lr=%x\n", fel_stash.sp, fel_stash.lr);
	137	return_to_fel(fel_stash.sp, fel_stash.lr);
36afd451 NK	138
36afd451 NK	139	return 0;
942cb0b6 SG	140	}
942cb0b6 SG	141
b56f6e2b	142	void s_init(void)
f630974c	143	{
583fede8 HG	144	/*
	145	* Undocumented magic taken from boot0, without this DRAM
	146	* access gets messed up (seems cache related).
	147	* The boot0 sources describe this as: "config ema for cache sram"
	148	*/
	149	#if defined CONFIG_MACH_SUN6I
f630974c	150	setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0x1800);
5f8afd70 HG	151	#elif defined CONFIG_MACH_SUN8I
5f8afd70 HG	152	__maybe_unused uint version;
583fede8 HG	153
	154	/* Unlock sram version info reg, read it, relock */
	155	setbits_le32(SUNXI_SRAMC_BASE + 0x24, (1 << 15));
5f8afd70	156	version = readl(SUNXI_SRAMC_BASE + 0x24) >> 16;
583fede8 HG	157	clrbits_le32(SUNXI_SRAMC_BASE + 0x24, (1 << 15));
583fede8 HG	158
5f8afd70 HG	159	/*
	160	* Ideally this would be a switch case, but we do not know exactly
	161	* which versions there are and which version needs which settings,
	162	* so reproduce the per SoC code from the BSP.
	163	*/
	164	#if defined CONFIG_MACH_SUN8I_A23
	165	if (version == 0x1650)
583fede8 HG	166	setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0x1800);
	167	else /* 0x1661 ? */
	168	setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0xc0);
5f8afd70 HG	169	#elif defined CONFIG_MACH_SUN8I_A33
	170	if (version != 0x1667)
	171	setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0xc0);
	172	#endif
	173	/* A83T BSP never modifies SUNXI_SRAMC_BASE + 0x44 */
	174	/* No H3 BSP, boot0 seems to not modify SUNXI_SRAMC_BASE + 0x44 */
f630974c	175	#endif
583fede8	176
92bcc6cb HG	177	#if defined CONFIG_MACH_SUN6I \|\| \
	178	defined CONFIG_MACH_SUN7I \|\| \
	179	defined CONFIG_MACH_SUN8I
f630974c SG	180	/* Enable SMP mode for CPU0, by setting bit 6 of Auxiliary Ctl reg */
	181	asm volatile(
	182	"mrc p15, 0, r0, c1, c0, 1\n"
	183	"orr r0, r0, #1 << 6\n"
	184	"mcr p15, 0, r0, c1, c0, 1\n");
	185	#endif
5823664f CYT	186	#if defined CONFIG_MACH_SUN6I \|\| defined CONFIG_MACH_SUN8I_H3
5823664f CYT	187	/* Enable non-secure access to some peripherals */
92369844 CYT	188	tzpc_init();
92369844 CYT	189	#endif
f630974c SG	190
	191	clock_init();
	192	timer_init();
	193	gpio_init();
	194	i2c_init_board();
fc8991c6	195	eth_init_board();
b56f6e2b	196	}
f630974c	197
b56f6e2b	198	#ifdef CONFIG_SPL_BUILD
a151403f DK	199	DECLARE_GLOBAL_DATA_PTR;
a151403f DK	200
b56f6e2b HG	201	/* The sunxi internal brom will try to loader external bootloader
b56f6e2b HG	202	* from mmc0, nand flash, mmc2.
b56f6e2b HG	203	*/
	204	u32 spl_boot_device(void)
	205	{
f7d6b3cc	206	__maybe_unused struct mmc mmc0, mmc1;
840fe95c	207	/*
a151403f DK	208	* When booting from the SD card or NAND memory, the "eGON.BT0"
	209	* signature is expected to be found in memory at the address 0x0004
	210	* (see the "mksunxiboot" tool, which generates this header).
840fe95c SS	211	*
	212	* When booting in the FEL mode over USB, this signature is patched in
	213	* memory and replaced with something else by the 'fel' tool. This other
	214	* signature is selected in such a way, that it can't be present in a
	215	* valid bootable SD card image (because the BROM would refuse to
	216	* execute the SPL in this case).
	217	*
a151403f DK	218	* This checks for the signature and if it is not found returns to
	219	* the FEL code in the BROM to wait and receive the main u-boot
	220	* binary over USB. If it is found, it determines where SPL was
	221	* read from.
840fe95c	222	*/
af654d14	223	if (!is_boot0_magic(SPL_ADDR + 4)) /* eGON.BT0 */
942cb0b6	224	return BOOT_DEVICE_BOARD;
a151403f DK	225
a151403f DK	226	/* The BROM will try to boot from mmc0 first, so try that first. */
f7d6b3cc	227	#ifdef CONFIG_MMC
a151403f DK	228	mmc_initialize(gd->bd);
	229	mmc0 = find_mmc_device(0);
	230	if (sunxi_mmc_has_egon_boot_signature(mmc0))
	231	return BOOT_DEVICE_MMC1;
f7d6b3cc	232	#endif
a151403f DK	233
	234	/* Fallback to booting NAND if enabled. */
	235	if (IS_ENABLED(CONFIG_SPL_NAND_SUPPORT))
	236	return BOOT_DEVICE_NAND;
	237
f7d6b3cc	238	#ifdef CONFIG_MMC
a151403f DK	239	if (CONFIG_MMC_SUNXI_SLOT_EXTRA == 2) {
a151403f DK	240	mmc1 = find_mmc_device(1);
a1e56cf6	241	if (sunxi_mmc_has_egon_boot_signature(mmc1))
a151403f	242	return BOOT_DEVICE_MMC2;
a151403f	243	}
f7d6b3cc	244	#endif
a151403f DK	245
	246	panic("Could not determine boot source\n");
	247	return -1; /* Never reached */
b56f6e2b HG	248	}
b56f6e2b HG	249
28d68045 BN	250	/*
	251	* Properly announce BOOT_DEVICE_BOARD as "FEL".
	252	* Overrides weak function from common/spl/spl.c
	253	*/
	254	void spl_board_announce_boot_device(void)
	255	{
	256	printf("FEL");
	257	}
	258
b56f6e2b	259	/* No confirmation data available in SPL yet. Hardcode bootmode */
2b1cdafa	260	u32 spl_boot_mode(const u32 boot_device)
b56f6e2b HG	261	{
	262	return MMCSD_MODE_RAW;
	263	}
	264
	265	void board_init_f(ulong dummy)
	266	{
6d0bdfdd	267	spl_init();
f630974c SG	268	preloader_console_init();
	269
	270	#ifdef CONFIG_SPL_I2C_SUPPORT
	271	/* Needed early by sunxi_board_init if PMU is enabled */
	272	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
	273	#endif
	274	sunxi_board_init();
f630974c SG	275	}
	276	#endif
	277
cba69eee IC	278	void reset_cpu(ulong addr)
cba69eee IC	279	{
44d8ae5b	280	#ifdef CONFIG_SUNXI_GEN_SUN4I
c7e79dec HG	281	static const struct sunxi_wdog *wdog =
	282	&((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog;
	283
	284	/* Set the watchdog for its shortest interval (.5s) and wait */
	285	writel(WDT_MODE_RESET_EN \| WDT_MODE_EN, &wdog->mode);
	286	writel(WDT_CTRL_KEY \| WDT_CTRL_RESTART, &wdog->ctl);
ae5de5a1 HG	287
	288	while (1) {
	289	/* sun5i sometimes gets stuck without this */
	290	writel(WDT_MODE_RESET_EN \| WDT_MODE_EN, &wdog->mode);
	291	}
44d8ae5b HG	292	#endif
44d8ae5b HG	293	#ifdef CONFIG_SUNXI_GEN_SUN6I
78c396a1 CYT	294	static const struct sunxi_wdog *wdog =
	295	((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog;
	296
	297	/* Set the watchdog for its shortest interval (.5s) and wait */
	298	writel(WDT_CFG_RESET, &wdog->cfg);
	299	writel(WDT_MODE_EN, &wdog->mode);
	300	writel(WDT_CTRL_KEY \| WDT_CTRL_RESTART, &wdog->ctl);
fc175434	301	while (1) { }
78c396a1	302	#endif
cba69eee IC	303	}
cba69eee IC	304
d96ebc46	305	#if !defined(CONFIG_SYS_DCACHE_OFF) && !defined(CONFIG_ARM64)
cba69eee IC	306	void enable_caches(void)
	307	{
	308	/* Enable D-cache. I-cache is already enabled in start.S */
	309	dcache_enable();
	310	}
	311	#endif