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Kconfig: Add CONFIG_SATA to enable SATA
[people/ms/u-boot.git] / arch / powerpc / cpu / mpc85xx / cpu_init.c
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42d1f039 1/*
a09b9b68 2 * Copyright 2007-2011 Freescale Semiconductor, Inc.
29372ff3 3 *
42d1f039
WD		 4 * (C) Copyright 2003 Motorola Inc.
5 * Modified by Xianghua Xiao, X.Xiao@motorola.com
6 *
7 * (C) Copyright 2000
8 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
9 *
1a459660 10 * SPDX-License-Identifier: GPL-2.0+
42d1f039
WD		 11 */
12
13#include <common.h>
14#include <watchdog.h>
15#include <asm/processor.h>
16#include <ioports.h>
f54fe87a 17#include <sata.h>
c916d7c9 18#include <fm_eth.h>
42d1f039 19#include <asm/io.h>
fd3c9bef 20#include <asm/cache.h>
87163180 21#include <asm/mmu.h>
a07bdad7 22#include <fsl_errata.h>
83d40dfd 23#include <asm/fsl_law.h>
f54fe87a 24#include <asm/fsl_serdes.h>
5ffa88ec 25#include <asm/fsl_srio.h>
2c0d6971
PK		 26#ifdef CONFIG_FSL_CORENET
27#include <asm/fsl_portals.h>
28#include <asm/fsl_liodn.h>
29#endif
9dee205d 30#include <fsl_usb.h>
57125f22 31#include <hwconfig.h>
fbc20aab 32#include <linux/compiler.h>
ec2b74ff 33#include "mp.h"
d0a6d7ce
AB		 34#ifdef CONFIG_CHAIN_OF_TRUST
35#include <fsl_validate.h>
36#endif
b9eebfad
RG		 37#ifdef CONFIG_FSL_CAAM
38#include <fsl_sec.h>
39#endif
f698e9f3
AB		 40#if defined(CONFIG_SECURE_BOOT) && defined(CONFIG_FSL_CORENET)
41#include <asm/fsl_pamu.h>
42#include <fsl_secboot_err.h>
43#endif
f2717b47 44#ifdef CONFIG_SYS_QE_FMAN_FW_IN_NAND
a7b1e1b7
HW		 45#include <nand.h>
46#include <errno.h>
47#endif
02fb2761
SL		 48#ifndef CONFIG_ARCH_QEMU_E500
49#include <fsl_ddr.h>
50#endif
fbc20aab 51#include "../../../../drivers/block/fsl_sata.h"
2a44efeb 52#ifdef CONFIG_U_QE
2459afb1 53#include <fsl_qe.h>
2a44efeb 54#endif
fbc20aab 55
d87080b7
WD		 56DECLARE_GLOBAL_DATA_PTR;
57
d1c561cd
NB		 58#ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
59/*
60 * For deriving usb clock from 100MHz sysclk, reference divisor is set
61 * to a value of 5, which gives an intermediate value 20(100/5). The
62 * multiplication factor integer is set to 24, which when multiplied to
63 * above intermediate value provides clock for usb ip.
64 */
65void usb_single_source_clk_configure(struct ccsr_usb_phy *usb_phy)
66{
67 sys_info_t sysinfo;
68
69 get_sys_info(&sysinfo);
70 if (sysinfo.diff_sysclk == 1) {
71 clrbits_be32(&usb_phy->pllprg[1],
72 CONFIG_SYS_FSL_USB_PLLPRG2_MFI);
73 setbits_be32(&usb_phy->pllprg[1],
74 CONFIG_SYS_FSL_USB_PLLPRG2_REF_DIV_INTERNAL_CLK |
75 CONFIG_SYS_FSL_USB_PLLPRG2_MFI_INTERNAL_CLK |
76 CONFIG_SYS_FSL_USB_INTERNAL_SOC_CLK_EN);
77 }
78}
79#endif
80
9c641a87
SG		 81#ifdef CONFIG_SYS_FSL_ERRATUM_A006261
82void fsl_erratum_a006261_workaround(struct ccsr_usb_phy __iomem *usb_phy)
83{
84#ifdef CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
85 u32 xcvrprg = in_be32(&usb_phy->port1.xcvrprg);
86
87 /* Increase Disconnect Threshold by 50mV */
88 xcvrprg &= ~CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_MASK |
89 INC_DCNT_THRESHOLD_50MV;
90 /* Enable programming of USB High speed Disconnect threshold */
91 xcvrprg |= CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_EN;
92 out_be32(&usb_phy->port1.xcvrprg, xcvrprg);
93
94 xcvrprg = in_be32(&usb_phy->port2.xcvrprg);
95 /* Increase Disconnect Threshold by 50mV */
96 xcvrprg &= ~CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_MASK |
97 INC_DCNT_THRESHOLD_50MV;
98 /* Enable programming of USB High speed Disconnect threshold */
99 xcvrprg |= CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_EN;
100 out_be32(&usb_phy->port2.xcvrprg, xcvrprg);
101#else
102
103 u32 temp = 0;
104 u32 status = in_be32(&usb_phy->status1);
105
106 u32 squelch_prog_rd_0_2 =
107 (status >> CONFIG_SYS_FSL_USB_SQUELCH_PROG_RD_0)
108 & CONFIG_SYS_FSL_USB_SQUELCH_PROG_MASK;
109
110 u32 squelch_prog_rd_3_5 =
111 (status >> CONFIG_SYS_FSL_USB_SQUELCH_PROG_RD_3)
112 & CONFIG_SYS_FSL_USB_SQUELCH_PROG_MASK;
113
114 setbits_be32(&usb_phy->config1,
115 CONFIG_SYS_FSL_USB_HS_DISCNCT_INC);
116 setbits_be32(&usb_phy->config2,
117 CONFIG_SYS_FSL_USB_RX_AUTO_CAL_RD_WR_SEL);
118
08efeac5 119 temp = squelch_prog_rd_0_2 << CONFIG_SYS_FSL_USB_SQUELCH_PROG_WR_3;
9c641a87
SG		 120 out_be32(&usb_phy->config2, in_be32(&usb_phy->config2) | temp);
121
08efeac5 122 temp = squelch_prog_rd_3_5 << CONFIG_SYS_FSL_USB_SQUELCH_PROG_WR_0;
9c641a87
SG		 123 out_be32(&usb_phy->config2, in_be32(&usb_phy->config2) | temp);
124#endif
125}
126#endif
127
128
2a44efeb 129#if defined(CONFIG_QE) && !defined(CONFIG_U_QE)
da9d4610
AF		 130extern qe_iop_conf_t qe_iop_conf_tab[];
131extern void qe_config_iopin(u8 port, u8 pin, int dir,
132 int open_drain, int assign);
133extern void qe_init(uint qe_base);
134extern void qe_reset(void);
135
136static void config_qe_ioports(void)
137{
138 u8 port, pin;
139 int dir, open_drain, assign;
140 int i;
141
142 for (i = 0; qe_iop_conf_tab[i].assign != QE_IOP_TAB_END; i++) {
143 port = qe_iop_conf_tab[i].port;
144 pin = qe_iop_conf_tab[i].pin;
145 dir = qe_iop_conf_tab[i].dir;
146 open_drain = qe_iop_conf_tab[i].open_drain;
147 assign = qe_iop_conf_tab[i].assign;
148 qe_config_iopin(port, pin, dir, open_drain, assign);
149 }
150}
151#endif
40d5fa35 152
9c4c5ae3 153#ifdef CONFIG_CPM2
aafeefbd 154void config_8560_ioports (volatile ccsr_cpm_t * cpm)
42d1f039
WD		 155{
156 int portnum;
157
158 for (portnum = 0; portnum < 4; portnum++) {
159 uint pmsk = 0,
160 ppar = 0,
161 psor = 0,
162 pdir = 0,
163 podr = 0,
164 pdat = 0;
165 iop_conf_t *iopc = (iop_conf_t *) & iop_conf_tab[portnum][0];
166 iop_conf_t *eiopc = iopc + 32;
167 uint msk = 1;
168
169 /*
170 * NOTE:
171 * index 0 refers to pin 31,
172 * index 31 refers to pin 0
173 */
174 while (iopc < eiopc) {
175 if (iopc->conf) {
176 pmsk |= msk;
177 if (iopc->ppar)
178 ppar |= msk;
179 if (iopc->psor)
180 psor |= msk;
181 if (iopc->pdir)
182 pdir |= msk;
183 if (iopc->podr)
184 podr |= msk;
185 if (iopc->pdat)
186 pdat |= msk;
187 }
188
189 msk <<= 1;
190 iopc++;
191 }
192
193 if (pmsk != 0) {
aafeefbd 194 volatile ioport_t *iop = ioport_addr (cpm, portnum);
42d1f039
WD		 195 uint tpmsk = ~pmsk;
196
197 /*
198 * the (somewhat confused) paragraph at the
199 * bottom of page 35-5 warns that there might
200 * be "unknown behaviour" when programming
201 * PSORx and PDIRx, if PPARx = 1, so I
202 * decided this meant I had to disable the
203 * dedicated function first, and enable it
204 * last.
205 */
206 iop->ppar &= tpmsk;
207 iop->psor = (iop->psor & tpmsk) | psor;
208 iop->podr = (iop->podr & tpmsk) | podr;
209 iop->pdat = (iop->pdat & tpmsk) | pdat;
210 iop->pdir = (iop->pdir & tpmsk) | pdir;
211 iop->ppar |= ppar;
212 }
213 }
214}
215#endif
216
6aba33e9 217#ifdef CONFIG_SYS_FSL_CPC
fb4a2409 218#if defined(CONFIG_RAMBOOT_PBL) || defined(CONFIG_SYS_CPC_REINIT_F)
7cb72723 219void disable_cpc_sram(void)
6aba33e9
KG		 220{
221 int i;
6aba33e9
KG		 222
223 cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR;
224
225 for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) {
2a9fab82
SX		 226 if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN) {
227 /* find and disable LAW of SRAM */
228 struct law_entry law = find_law(CONFIG_SYS_INIT_L3_ADDR);
229
230 if (law.index == -1) {
231 printf("\nFatal error happened\n");
232 return;
233 }
234 disable_law(law.index);
235
236 clrbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_CDQ_SPEC_DIS);
237 out_be32(&cpc->cpccsr0, 0);
238 out_be32(&cpc->cpcsrcr0, 0);
239 }
fb4a2409
AB		 240 }
241}
2a9fab82 242#endif
6aba33e9 243
377ffcfa
SS		 244#if defined(T1040_TDM_QUIRK_CCSR_BASE)
245#ifdef CONFIG_POST
246#error POST memory test cannot be enabled with TDM
247#endif
248static void enable_tdm_law(void)
249{
250 int ret;
251 char buffer[HWCONFIG_BUFFER_SIZE] = {0};
252 int tdm_hwconfig_enabled = 0;
253
254 /*
255 * Extract hwconfig from environment since environment
256 * is not setup properly yet. Search for tdm entry in
257 * hwconfig.
258 */
259 ret = getenv_f("hwconfig", buffer, sizeof(buffer));
260 if (ret > 0) {
261 tdm_hwconfig_enabled = hwconfig_f("tdm", buffer);
262 /* If tdm is defined in hwconfig, set law for tdm workaround */
263 if (tdm_hwconfig_enabled)
264 set_next_law(T1040_TDM_QUIRK_CCSR_BASE, LAW_SIZE_16M,
265 LAW_TRGT_IF_CCSR);
266 }
267}
268#endif
269
7cb72723 270void enable_cpc(void)
fb4a2409
AB		 271{
272 int i;
390619dd 273 int ret;
fb4a2409 274 u32 size = 0;
390619dd
SL		 275 u32 cpccfg0;
276 char buffer[HWCONFIG_BUFFER_SIZE];
277 char cpc_subarg[16];
278 bool have_hwconfig = false;
279 int cpc_args = 0;
fb4a2409
AB		 280 cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR;
281
390619dd
SL		 282 /* Extract hwconfig from environment */
283 ret = getenv_f("hwconfig", buffer, sizeof(buffer));
284 if (ret > 0) {
285 /*
286 * If "en_cpc" is not defined in hwconfig then by default all
287 * cpcs are enable. If this config is defined then individual
288 * cpcs which have to be enabled should also be defined.
289 * e.g en_cpc:cpc1,cpc2;
290 */
291 if (hwconfig_f("en_cpc", buffer))
292 have_hwconfig = true;
293 }
294
fb4a2409 295 for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) {
390619dd
SL		 296 if (have_hwconfig) {
297 sprintf(cpc_subarg, "cpc%u", i + 1);
298 cpc_args = hwconfig_sub_f("en_cpc", cpc_subarg, buffer);
299 if (cpc_args == 0)
300 continue;
301 }
302 cpccfg0 = in_be32(&cpc->cpccfg0);
fb4a2409
AB		 303 size += CPC_CFG0_SZ_K(cpccfg0);
304
1d2c2a62
KG		 305#ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A002
306 setbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_TAG_ECC_SCRUB_DIS);
307#endif
868da593
KG		 308#ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A003
309 setbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_DATA_ECC_SCRUB_DIS);
310#endif
82125192
SW		 311#ifdef CONFIG_SYS_FSL_ERRATUM_A006593
312 setbits_be32(&cpc->cpchdbcr0, 1 << (31 - 21));
313#endif
133fbfa9
YS		 314#ifdef CONFIG_SYS_FSL_ERRATUM_A006379
315 if (has_erratum_a006379()) {
316 setbits_be32(&cpc->cpchdbcr0,
317 CPC_HDBCR0_SPLRU_LEVEL_EN);
318 }
319#endif
1d2c2a62 320
6aba33e9
KG		 321 out_be32(&cpc->cpccsr0, CPC_CSR0_CE | CPC_CSR0_PE);
322 /* Read back to sync write */
323 in_be32(&cpc->cpccsr0);
324
325 }
326
2f848f97
SK		 327 puts("Corenet Platform Cache: ");
328 print_size(size * 1024, " enabled\n");
6aba33e9
KG		 329}
330
e56143e5 331static void invalidate_cpc(void)
6aba33e9
KG		 332{
333 int i;
334 cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR;
335
336 for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) {
2a9fab82
SX		 337 /* skip CPC when it used as all SRAM */
338 if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN)
339 continue;
6aba33e9
KG		 340 /* Flash invalidate the CPC and clear all the locks */
341 out_be32(&cpc->cpccsr0, CPC_CSR0_FI | CPC_CSR0_LFC);
342 while (in_be32(&cpc->cpccsr0) & (CPC_CSR0_FI | CPC_CSR0_LFC))
343 ;
344 }
345}
346#else
347#define enable_cpc()
348#define invalidate_cpc()
7cb72723 349#define disable_cpc_sram()
6aba33e9
KG		 350#endif /* CONFIG_SYS_FSL_CPC */
351
42d1f039
WD		 352/*
353 * Breathe some life into the CPU...
354 *
355 * Set up the memory map
356 * initialize a bunch of registers
357 */
358
3c2a67ee
KG		 359#ifdef CONFIG_FSL_CORENET
360static void corenet_tb_init(void)
361{
362 volatile ccsr_rcpm_t *rcpm =
363 (void *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR);
364 volatile ccsr_pic_t *pic =
680c613a 365 (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR);
3c2a67ee
KG		 366 u32 whoami = in_be32(&pic->whoami);
367
368 /* Enable the timebase register for this core */
369 out_be32(&rcpm->ctbenrl, (1 << whoami));
370}
371#endif
372
c3678b09
YS		 373#ifdef CONFIG_SYS_FSL_ERRATUM_A007212
374void fsl_erratum_a007212_workaround(void)
375{
376 ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
377 u32 ddr_pll_ratio;
378 u32 __iomem *plldgdcr1 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c20);
379 u32 __iomem *plldadcr1 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c28);
380 u32 __iomem *dpdovrcr4 = (void *)(CONFIG_SYS_DCSRBAR + 0x21e80);
51370d56 381#if (CONFIG_SYS_NUM_DDR_CTLRS >= 2)
c3678b09
YS		 382 u32 __iomem *plldgdcr2 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c40);
383 u32 __iomem *plldadcr2 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c48);
51370d56 384#if (CONFIG_SYS_NUM_DDR_CTLRS >= 3)
c3678b09
YS		 385 u32 __iomem *plldgdcr3 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c60);
386 u32 __iomem *plldadcr3 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c68);
387#endif
388#endif
389 /*
390 * Even this workaround applies to selected version of SoCs, it is
391 * safe to apply to all versions, with the limitation of odd ratios.
392 * If RCW has disabled DDR PLL, we have to apply this workaround,
393 * otherwise DDR will not work.
394 */
395 ddr_pll_ratio = (in_be32(&gur->rcwsr[0]) >>
396 FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT) &
397 FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK;
398 /* check if RCW sets ratio to 0, required by this workaround */
399 if (ddr_pll_ratio != 0)
400 return;
401 ddr_pll_ratio = (in_be32(&gur->rcwsr[0]) >>
402 FSL_CORENET_RCWSR0_MEM_PLL_RAT_RESV_SHIFT) &
403 FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK;
404 /* check if reserved bits have the desired ratio */
405 if (ddr_pll_ratio == 0) {
406 printf("Error: Unknown DDR PLL ratio!\n");
407 return;
408 }
409 ddr_pll_ratio >>= 1;
410
411 setbits_be32(plldadcr1, 0x02000001);
51370d56 412#if (CONFIG_SYS_NUM_DDR_CTLRS >= 2)
c3678b09 413 setbits_be32(plldadcr2, 0x02000001);
51370d56 414#if (CONFIG_SYS_NUM_DDR_CTLRS >= 3)
c3678b09
YS		 415 setbits_be32(plldadcr3, 0x02000001);
416#endif
417#endif
418 setbits_be32(dpdovrcr4, 0xe0000000);
419 out_be32(plldgdcr1, 0x08000001 | (ddr_pll_ratio << 1));
51370d56 420#if (CONFIG_SYS_NUM_DDR_CTLRS >= 2)
c3678b09 421 out_be32(plldgdcr2, 0x08000001 | (ddr_pll_ratio << 1));
51370d56 422#if (CONFIG_SYS_NUM_DDR_CTLRS >= 3)
c3678b09
YS		 423 out_be32(plldgdcr3, 0x08000001 | (ddr_pll_ratio << 1));
424#endif
425#endif
426 udelay(100);
427 clrbits_be32(plldadcr1, 0x02000001);
51370d56 428#if (CONFIG_SYS_NUM_DDR_CTLRS >= 2)
c3678b09 429 clrbits_be32(plldadcr2, 0x02000001);
51370d56 430#if (CONFIG_SYS_NUM_DDR_CTLRS >= 3)
c3678b09
YS		 431 clrbits_be32(plldadcr3, 0x02000001);
432#endif
433#endif
434 clrbits_be32(dpdovrcr4, 0xe0000000);
435}
436#endif
437
701e6401 438ulong cpu_init_f(void)
42d1f039 439{
42d1f039 440 extern void m8560_cpm_reset (void);
f698e9f3 441#ifdef CONFIG_SYS_DCSRBAR_PHYS
f110fe94
SG		 442 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
443#endif
aa36c84e 444#if defined(CONFIG_SECURE_BOOT) && !defined(CONFIG_SYS_RAMBOOT)
7065b7d4
RG		 445 struct law_entry law;
446#endif
281ed4c7 447#ifdef CONFIG_ARCH_MPC8548
a2cd50ed
PT		 448 ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
449 uint svr = get_svr();
450
451 /*
452 * CPU2 errata workaround: A core hang possible while executing
453 * a msync instruction and a snoopable transaction from an I/O
454 * master tagged to make quick forward progress is present.
455 * Fixed in silicon rev 2.1.
456 */
457 if ((SVR_MAJ(svr) == 1) || ((SVR_MAJ(svr) == 2 && SVR_MIN(svr) == 0x0)))
458 out_be32(&ecm->eebpcr, in_be32(&ecm->eebpcr) | (1 << 16));
459#endif
42d1f039 460
87163180
KG		 461 disable_tlb(14);
462 disable_tlb(15);
463
aa36c84e 464#if defined(CONFIG_SECURE_BOOT) && !defined(CONFIG_SYS_RAMBOOT)
7065b7d4
RG		 465 /* Disable the LAW created for NOR flash by the PBI commands */
466 law = find_law(CONFIG_SYS_PBI_FLASH_BASE);
467 if (law.index != -1)
468 disable_law(law.index);
fb4a2409
AB		 469
470#if defined(CONFIG_SYS_CPC_REINIT_F)
471 disable_cpc_sram();
472#endif
7065b7d4
RG		 473#endif
474
9c4c5ae3 475#ifdef CONFIG_CPM2
6d0f6bcf 476 config_8560_ioports((ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR);
42d1f039
WD		 477#endif
478
f51cdaf1 479 init_early_memctl_regs();
42d1f039 480
9c4c5ae3 481#if defined(CONFIG_CPM2)
42d1f039
WD		 482 m8560_cpm_reset();
483#endif
2a44efeb
ZQ		 484
485#if defined(CONFIG_QE) && !defined(CONFIG_U_QE)
da9d4610
AF		 486 /* Config QE ioports */
487 config_qe_ioports();
488#endif
2a44efeb 489
79f4333c
PT		 490#if defined(CONFIG_FSL_DMA)
491 dma_init();
492#endif
3c2a67ee
KG		 493#ifdef CONFIG_FSL_CORENET
494 corenet_tb_init();
495#endif
94e9411b 496 init_used_tlb_cams();
6aba33e9
KG		 497
498 /* Invalidate the CPC before DDR gets enabled */
499 invalidate_cpc();
f110fe94
SG		 500
501 #ifdef CONFIG_SYS_DCSRBAR_PHYS
502 /* set DCSRCR so that DCSR space is 1G */
503 setbits_be32(&gur->dcsrcr, FSL_CORENET_DCSR_SZ_1G);
504 in_be32(&gur->dcsrcr);
505#endif
506
c3678b09
YS		 507#ifdef CONFIG_SYS_FSL_ERRATUM_A007212
508 fsl_erratum_a007212_workaround();
509#endif
510
59d34ed0 511 return 0;
42d1f039
WD		 512}
513
35079aa9
KG		 514/* Implement a dummy function for those platforms w/o SERDES */
515static void __fsl_serdes__init(void)
516{
517 return ;
518}
519__attribute__((weak, alias("__fsl_serdes__init"))) void fsl_serdes_init(void);
d9b94f28 520
e9827468 521#if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500)
6d2b9da1
YS		 522int enable_cluster_l2(void)
523{
524 int i = 0;
5122dfae 525 u32 cluster, svr = get_svr();
6d2b9da1
YS		 526 ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
527 struct ccsr_cluster_l2 __iomem *l2cache;
528
5122dfae
SL		 529 /* only the L2 of first cluster should be enabled as expected on T4080,
530 * but there is no EOC in the first cluster as HW sake, so return here
531 * to skip enabling L2 cache of the 2nd cluster.
532 */
533 if (SVR_SOC_VER(svr) == SVR_T4080)
534 return 0;
535
6d2b9da1
YS		 536 cluster = in_be32(&gur->tp_cluster[i].lower);
537 if (cluster & TP_CLUSTER_EOC)
538 return 0;
539
540 /* The first cache has already been set up, so skip it */
541 i++;
542
543 /* Look through the remaining clusters, and set up their caches */
544 do {
db9a8070
PK		 545 int j, cluster_valid = 0;
546
6d2b9da1 547 l2cache = (void __iomem *)(CONFIG_SYS_FSL_CLUSTER_1_L2 + i * 0x40000);
db9a8070 548
6d2b9da1
YS		 549 cluster = in_be32(&gur->tp_cluster[i].lower);
550
db9a8070
PK		 551 /* check that at least one core/accel is enabled in cluster */
552 for (j = 0; j < 4; j++) {
553 u32 idx = (cluster >> (j*8)) & TP_CLUSTER_INIT_MASK;
554 u32 type = in_be32(&gur->tp_ityp[idx]);
6d2b9da1 555
a1399a91
SL		 556 if ((type & TP_ITYP_AV) &&
557 TP_ITYP_TYPE(type) == TP_ITYP_TYPE_PPC)
db9a8070
PK		 558 cluster_valid = 1;
559 }
6d2b9da1 560
db9a8070
PK		 561 if (cluster_valid) {
562 /* set stash ID to (cluster) * 2 + 32 + 1 */
563 clrsetbits_be32(&l2cache->l2csr1, 0xff, 32 + i * 2 + 1);
564
565 printf("enable l2 for cluster %d %p\n", i, l2cache);
566
567 out_be32(&l2cache->l2csr0, L2CSR0_L2FI|L2CSR0_L2LFC);
568 while ((in_be32(&l2cache->l2csr0)
569 & (L2CSR0_L2FI|L2CSR0_L2LFC)) != 0)
570 ;
9cd95ac7 571 out_be32(&l2cache->l2csr0, L2CSR0_L2E|L2CSR0_L2PE|L2CSR0_L2REP_MODE);
db9a8070 572 }
6d2b9da1
YS		 573 i++;
574 } while (!(cluster & TP_CLUSTER_EOC));
575
576 return 0;
577}
578#endif
579
42d1f039 580/*
d9b94f28 581 * Initialize L2 as cache.
42d1f039 582 */
7cb72723 583int l2cache_init(void)
42d1f039 584{
fbc20aab 585 __maybe_unused u32 svr = get_svr();
6d2b9da1
YS		 586#ifdef CONFIG_L2_CACHE
587 ccsr_l2cache_t *l2cache = (void __iomem *)CONFIG_SYS_MPC85xx_L2_ADDR;
e9827468 588#elif defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500)
6d2b9da1 589 struct ccsr_cluster_l2 * l2cache = (void __iomem *)CONFIG_SYS_FSL_CLUSTER_1_L2;
3f0202ed 590#endif
2a5fcb83 591
6beecfbb
WG		 592 puts ("L2: ");
593
42d1f039 594#if defined(CONFIG_L2_CACHE)
d9b94f28 595 volatile uint cache_ctl;
fbc20aab 596 uint ver;
73f15a06 597 u32 l2siz_field;
d9b94f28 598
f3e04bdc 599 ver = SVR_SOC_VER(svr);
42d1f039 600
d65cfe89 601 asm("msync;isync");
d9b94f28 602 cache_ctl = l2cache->l2ctl;
7da53351
MH		 603
604#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR)
605 if (cache_ctl & MPC85xx_L2CTL_L2E) {
606 /* Clear L2 SRAM memory-mapped base address */
607 out_be32(&l2cache->l2srbar0, 0x0);
608 out_be32(&l2cache->l2srbar1, 0x0);
609
610 /* set MBECCDIS=0, SBECCDIS=0 */
611 clrbits_be32(&l2cache->l2errdis,
612 (MPC85xx_L2ERRDIS_MBECC |
613 MPC85xx_L2ERRDIS_SBECC));
614
615 /* set L2E=0, L2SRAM=0 */
616 clrbits_be32(&l2cache->l2ctl,
617 (MPC85xx_L2CTL_L2E |
618 MPC85xx_L2CTL_L2SRAM_ENTIRE));
619 }
620#endif
621
73f15a06 622 l2siz_field = (cache_ctl >> 28) & 0x3;
d9b94f28 623
73f15a06
KG		 624 switch (l2siz_field) {
625 case 0x0:
626 printf(" unknown size (0x%08x)\n", cache_ctl);
627 return -1;
628 break;
629 case 0x1:
630 if (ver == SVR_8540 || ver == SVR_8560 ||
48f6a5c3 631 ver == SVR_8541 || ver == SVR_8555) {
6b44d9e5
SK		 632 puts("128 KiB ");
633 /* set L2E=1, L2I=1, & L2BLKSZ=1 (128 KiBibyte) */
73f15a06 634 cache_ctl = 0xc4000000;
d9b94f28 635 } else {
6b44d9e5 636 puts("256 KiB ");
73f15a06
KG		 637 cache_ctl = 0xc0000000; /* set L2E=1, L2I=1, & L2SRAM=0 */
638 }
639 break;
640 case 0x2:
641 if (ver == SVR_8540 || ver == SVR_8560 ||
48f6a5c3 642 ver == SVR_8541 || ver == SVR_8555) {
6b44d9e5
SK		 643 puts("256 KiB ");
644 /* set L2E=1, L2I=1, & L2BLKSZ=2 (256 KiBibyte) */
29372ff3 645 cache_ctl = 0xc8000000;
73f15a06 646 } else {
6b44d9e5 647 puts("512 KiB ");
73f15a06
KG		 648 /* set L2E=1, L2I=1, & L2SRAM=0 */
649 cache_ctl = 0xc0000000;
d9b94f28 650 }
d65cfe89 651 break;
73f15a06 652 case 0x3:
6b44d9e5 653 puts("1024 KiB ");
73f15a06
KG		 654 /* set L2E=1, L2I=1, & L2SRAM=0 */
655 cache_ctl = 0xc0000000;
29372ff3 656 break;
d65cfe89
JL		 657 }
658
76b474e2 659 if (l2cache->l2ctl & MPC85xx_L2CTL_L2E) {
6beecfbb 660 puts("already enabled");
888279b5 661#if defined(CONFIG_SYS_INIT_L2_ADDR) && defined(CONFIG_SYS_FLASH_BASE)
e4c9a35d 662 u32 l2srbar = l2cache->l2srbar0;
76b474e2
MH		 663 if (l2cache->l2ctl & MPC85xx_L2CTL_L2SRAM_ENTIRE
664 && l2srbar >= CONFIG_SYS_FLASH_BASE) {
6d0f6bcf 665 l2srbar = CONFIG_SYS_INIT_L2_ADDR;
29372ff3 666 l2cache->l2srbar0 = l2srbar;
9a511bd6 667 printf(", moving to 0x%08x", CONFIG_SYS_INIT_L2_ADDR);
29372ff3 668 }
6d0f6bcf 669#endif /* CONFIG_SYS_INIT_L2_ADDR */
29372ff3
ES		 670 puts("\n");
671 } else {
672 asm("msync;isync");
673 l2cache->l2ctl = cache_ctl; /* invalidate & enable */
674 asm("msync;isync");
6beecfbb 675 puts("enabled\n");
29372ff3 676 }
1b3e4044 677#elif defined(CONFIG_BACKSIDE_L2_CACHE)
48f6a5c3 678 if (SVR_SOC_VER(svr) == SVR_P2040) {
acf3f8da
KG		 679 puts("N/A\n");
680 goto skip_l2;
681 }
682
1b3e4044
KG		 683 u32 l2cfg0 = mfspr(SPRN_L2CFG0);
684
685 /* invalidate the L2 cache */
25bacf7a
KG		 686 mtspr(SPRN_L2CSR0, (L2CSR0_L2FI|L2CSR0_L2LFC));
687 while (mfspr(SPRN_L2CSR0) & (L2CSR0_L2FI|L2CSR0_L2LFC))
1b3e4044
KG		 688 ;
689
82fd1f8d
KG		 690#ifdef CONFIG_SYS_CACHE_STASHING
691 /* set stash id to (coreID) * 2 + 32 + L2 (1) */
692 mtspr(SPRN_L2CSR1, (32 + 1));
693#endif
694
1b3e4044
KG		 695 /* enable the cache */
696 mtspr(SPRN_L2CSR0, CONFIG_SYS_INIT_L2CSR0);
697
654ea1f3
DL		 698 if (CONFIG_SYS_INIT_L2CSR0 & L2CSR0_L2E) {
699 while (!(mfspr(SPRN_L2CSR0) & L2CSR0_L2E))
700 ;
2f848f97 701 print_size((l2cfg0 & 0x3fff) * 64 * 1024, " enabled\n");
654ea1f3 702 }
acf3f8da
KG		 703
704skip_l2:
e9827468 705#elif defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500)
6d2b9da1 706 if (l2cache->l2csr0 & L2CSR0_L2E)
2f848f97
SK		 707 print_size((l2cache->l2cfg0 & 0x3fff) * 64 * 1024,
708 " enabled\n");
6d2b9da1
YS		 709
710 enable_cluster_l2();
42d1f039 711#else
6beecfbb 712 puts("disabled\n");
42d1f039 713#endif
6aba33e9 714
7cb72723
TY		 715 return 0;
716}
717
718/*
719 *
720 * The newer 8548, etc, parts have twice as much cache, but
721 * use the same bit-encoding as the older 8555, etc, parts.
722 *
723 */
724int cpu_init_r(void)
725{
726 __maybe_unused u32 svr = get_svr();
727#ifdef CONFIG_SYS_LBC_LCRR
728 fsl_lbc_t *lbc = (void __iomem *)LBC_BASE_ADDR;
729#endif
730#if defined(CONFIG_PPC_SPINTABLE_COMPATIBLE) && defined(CONFIG_MP)
731 extern int spin_table_compat;
732 const char *spin;
733#endif
734#ifdef CONFIG_SYS_FSL_ERRATUM_SEC_A003571
735 ccsr_sec_t __iomem *sec = (void *)CONFIG_SYS_FSL_SEC_ADDR;
736#endif
737#if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) || \
738 defined(CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011)
739 /*
740 * CPU22 and NMG_CPU_A011 share the same workaround.
741 * CPU22 applies to P4080 rev 1.0, 2.0, fixed in 3.0
742 * NMG_CPU_A011 applies to P4080 rev 1.0, 2.0, fixed in 3.0
743 * also applies to P3041 rev 1.0, 1.1, P2041 rev 1.0, 1.1, both
744 * fixed in 2.0. NMG_CPU_A011 is activated by default and can
745 * be disabled by hwconfig with syntax:
746 *
747 * fsl_cpu_a011:disable
748 */
749 extern int enable_cpu_a011_workaround;
750#ifdef CONFIG_SYS_P4080_ERRATUM_CPU22
751 enable_cpu_a011_workaround = (SVR_MAJ(svr) < 3);
752#else
753 char buffer[HWCONFIG_BUFFER_SIZE];
754 char *buf = NULL;
755 int n, res;
756
757 n = getenv_f("hwconfig", buffer, sizeof(buffer));
758 if (n > 0)
759 buf = buffer;
760
761 res = hwconfig_arg_cmp_f("fsl_cpu_a011", "disable", buf);
762 if (res > 0) {
763 enable_cpu_a011_workaround = 0;
764 } else {
765 if (n >= HWCONFIG_BUFFER_SIZE) {
766 printf("fsl_cpu_a011 was not found. hwconfig variable "
767 "may be too long\n");
768 }
769 enable_cpu_a011_workaround =
770 (SVR_SOC_VER(svr) == SVR_P4080 && SVR_MAJ(svr) < 3) ||
771 (SVR_SOC_VER(svr) != SVR_P4080 && SVR_MAJ(svr) < 2);
772 }
773#endif
774 if (enable_cpu_a011_workaround) {
775 flush_dcache();
776 mtspr(L1CSR2, (mfspr(L1CSR2) | L1CSR2_DCWS));
777 sync();
778 }
779#endif
06ad970b
DD		 780
781#ifdef CONFIG_SYS_FSL_ERRATUM_A007907
782 flush_dcache();
783 mtspr(L1CSR2, (mfspr(L1CSR2) & ~L1CSR2_DCSTASHID));
784 sync();
785#endif
786
7cb72723
TY		 787#ifdef CONFIG_SYS_FSL_ERRATUM_A005812
788 /*
789 * A-005812 workaround sets bit 32 of SPR 976 for SoCs running
790 * in write shadow mode. Checking DCWS before setting SPR 976.
791 */
792 if (mfspr(L1CSR2) & L1CSR2_DCWS)
793 mtspr(SPRN_HDBCR0, (mfspr(SPRN_HDBCR0) | 0x80000000));
794#endif
795
796#if defined(CONFIG_PPC_SPINTABLE_COMPATIBLE) && defined(CONFIG_MP)
797 spin = getenv("spin_table_compat");
798 if (spin && (*spin == 'n'))
799 spin_table_compat = 0;
800 else
801 spin_table_compat = 1;
802#endif
803
2c0d6971
PK		 804#ifdef CONFIG_FSL_CORENET
805 set_liodns();
806#ifdef CONFIG_SYS_DPAA_QBMAN
807 setup_portals();
808#endif
809#endif
810
7cb72723 811 l2cache_init();
fb4a2409
AB		 812#if defined(CONFIG_RAMBOOT_PBL)
813 disable_cpc_sram();
814#endif
6aba33e9 815 enable_cpc();
377ffcfa
SS		 816#if defined(T1040_TDM_QUIRK_CCSR_BASE)
817 enable_tdm_law();
818#endif
6aba33e9 819
cb93071b 820#ifndef CONFIG_SYS_FSL_NO_SERDES
af025065
KG		 821 /* needs to be in ram since code uses global static vars */
822 fsl_serdes_init();
cb93071b 823#endif
af025065 824
424bf942
SL		 825#ifdef CONFIG_SYS_FSL_ERRATUM_SEC_A003571
826#define MCFGR_AXIPIPE 0x000000f0
827 if (IS_SVR_REV(svr, 1, 0))
028dbb8d 828 sec_clrbits32(&sec->mcfgr, MCFGR_AXIPIPE);
424bf942
SL		 829#endif
830
72bd83cd
SL		 831#ifdef CONFIG_SYS_FSL_ERRATUM_A005871
832 if (IS_SVR_REV(svr, 1, 0)) {
833 int i;
834 __be32 *p = (void __iomem *)CONFIG_SYS_DCSRBAR + 0xb004c;
835
836 for (i = 0; i < 12; i++) {
837 p += i + (i > 5 ? 11 : 0);
838 out_be32(p, 0x2);
839 }
840 p = (void __iomem *)CONFIG_SYS_DCSRBAR + 0xb0108;
841 out_be32(p, 0x34);
842 }
843#endif
844
a09b9b68
KG		 845#ifdef CONFIG_SYS_SRIO
846 srio_init();
c8b28152 847#ifdef CONFIG_SRIO_PCIE_BOOT_MASTER
ff65f126
LG		 848 char *s = getenv("bootmaster");
849 if (s) {
850 if (!strcmp(s, "SRIO1")) {
851 srio_boot_master(1);
852 srio_boot_master_release_slave(1);
853 }
854 if (!strcmp(s, "SRIO2")) {
855 srio_boot_master(2);
856 srio_boot_master_release_slave(2);
857 }
858 }
5ffa88ec 859#endif
a09b9b68
KG		 860#endif
861
ec2b74ff
KG		 862#if defined(CONFIG_MP)
863 setup_mp();
864#endif
3f0202ed 865
4e0be34a 866#ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC13
ae026ffd 867 {
4e0be34a
ZRR		 868 if (SVR_MAJ(svr) < 3) {
869 void *p;
870 p = (void *)CONFIG_SYS_DCSRBAR + 0x20520;
871 setbits_be32(p, 1 << (31 - 14));
872 }
ae026ffd
RZ		 873 }
874#endif
875
3f0202ed
LC		 876#ifdef CONFIG_SYS_LBC_LCRR
877 /*
878 * Modify the CLKDIV field of LCRR register to improve the writing
879 * speed for NOR flash.
880 */
881 clrsetbits_be32(&lbc->lcrr, LCRR_CLKDIV, CONFIG_SYS_LBC_LCRR);
882 __raw_readl(&lbc->lcrr);
883 isync();
2b3a1cdd
KG		 884#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_LBC103
885 udelay(100);
886#endif
3f0202ed
LC		 887#endif
888
86221f09
RZ		 889#ifdef CONFIG_SYS_FSL_USB1_PHY_ENABLE
890 {
9dee205d 891 struct ccsr_usb_phy __iomem *usb_phy1 =
86221f09 892 (void *)CONFIG_SYS_MPC85xx_USB1_PHY_ADDR;
9c641a87
SG		 893#ifdef CONFIG_SYS_FSL_ERRATUM_A006261
894 if (has_erratum_a006261())
895 fsl_erratum_a006261_workaround(usb_phy1);
896#endif
86221f09
RZ		 897 out_be32(&usb_phy1->usb_enable_override,
898 CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE);
899 }
900#endif
901#ifdef CONFIG_SYS_FSL_USB2_PHY_ENABLE
902 {
9dee205d 903 struct ccsr_usb_phy __iomem *usb_phy2 =
86221f09 904 (void *)CONFIG_SYS_MPC85xx_USB2_PHY_ADDR;
9c641a87
SG		 905#ifdef CONFIG_SYS_FSL_ERRATUM_A006261
906 if (has_erratum_a006261())
907 fsl_erratum_a006261_workaround(usb_phy2);
908#endif
86221f09
RZ		 909 out_be32(&usb_phy2->usb_enable_override,
910 CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE);
911 }
912#endif
913
99d7b0a4
X		 914#ifdef CONFIG_SYS_FSL_ERRATUM_USB14
915 /* On P204x/P304x/P50x0 Rev1.0, USB transmit will result internal
916 * multi-bit ECC errors which has impact on performance, so software
917 * should disable all ECC reporting from USB1 and USB2.
918 */
919 if (IS_SVR_REV(get_svr(), 1, 0)) {
920 struct dcsr_dcfg_regs *dcfg = (struct dcsr_dcfg_regs *)
921 (CONFIG_SYS_DCSRBAR + CONFIG_SYS_DCSR_DCFG_OFFSET);
922 setbits_be32(&dcfg->ecccr1,
923 (DCSR_DCFG_ECC_DISABLE_USB1 |
924 DCSR_DCFG_ECC_DISABLE_USB2));
925 }
926#endif
927
3fa75c87 928#if defined(CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE)
9dee205d 929 struct ccsr_usb_phy __iomem *usb_phy =
3fa75c87
RZ		 930 (void *)CONFIG_SYS_MPC85xx_USB1_PHY_ADDR;
931 setbits_be32(&usb_phy->pllprg[1],
932 CONFIG_SYS_FSL_USB_PLLPRG2_PHY2_CLK_EN |
933 CONFIG_SYS_FSL_USB_PLLPRG2_PHY1_CLK_EN |
934 CONFIG_SYS_FSL_USB_PLLPRG2_MFI |
935 CONFIG_SYS_FSL_USB_PLLPRG2_PLL_EN);
d1c561cd
NB		 936#ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
937 usb_single_source_clk_configure(usb_phy);
938#endif
3fa75c87
RZ		 939 setbits_be32(&usb_phy->port1.ctrl,
940 CONFIG_SYS_FSL_USB_CTRL_PHY_EN);
941 setbits_be32(&usb_phy->port1.drvvbuscfg,
942 CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN);
943 setbits_be32(&usb_phy->port1.pwrfltcfg,
944 CONFIG_SYS_FSL_USB_PWRFLT_CR_EN);
945 setbits_be32(&usb_phy->port2.ctrl,
946 CONFIG_SYS_FSL_USB_CTRL_PHY_EN);
947 setbits_be32(&usb_phy->port2.drvvbuscfg,
948 CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN);
949 setbits_be32(&usb_phy->port2.pwrfltcfg,
950 CONFIG_SYS_FSL_USB_PWRFLT_CR_EN);
9c641a87
SG		 951
952#ifdef CONFIG_SYS_FSL_ERRATUM_A006261
953 if (has_erratum_a006261())
954 fsl_erratum_a006261_workaround(usb_phy);
3fa75c87
RZ		 955#endif
956
9c641a87
SG		 957#endif /* CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE */
958
02fb2761
SL		 959#ifdef CONFIG_SYS_FSL_ERRATUM_A009942
960 erratum_a009942_check_cpo();
961#endif
962
c916d7c9
KG		 963#ifdef CONFIG_FMAN_ENET
964 fman_enet_init();
965#endif
966
f698e9f3
AB		 967#if defined(CONFIG_SECURE_BOOT) && defined(CONFIG_FSL_CORENET)
968 if (pamu_init() < 0)
969 fsl_secboot_handle_error(ERROR_ESBC_PAMU_INIT);
970#endif
971
b9eebfad
RG		 972#ifdef CONFIG_FSL_CAAM
973 sec_init();
76394c9c 974
4fd64746 975#if defined(CONFIG_ARCH_C29X)
76394c9c
AP		 976 if ((SVR_SOC_VER(svr) == SVR_C292) ||
977 (SVR_SOC_VER(svr) == SVR_C293))
978 sec_init_idx(1);
979
980 if (SVR_SOC_VER(svr) == SVR_C293)
981 sec_init_idx(2);
982#endif
b9eebfad
RG		 983#endif
984
63659ff3 985#if defined(CONFIG_FSL_SATA_V2) && defined(CONFIG_SYS_FSL_ERRATUM_SATA_A001)
fbc20aab
TT		 986 /*
987 * For P1022/1013 Rev1.0 silicon, after power on SATA host
988 * controller is configured in legacy mode instead of the
989 * expected enterprise mode. Software needs to clear bit[28]
990 * of HControl register to change to enterprise mode from
991 * legacy mode. We assume that the controller is offline.
992 */
993 if (IS_SVR_REV(svr, 1, 0) &&
994 ((SVR_SOC_VER(svr) == SVR_P1022) ||
48f6a5c3 995 (SVR_SOC_VER(svr) == SVR_P1013))) {
fbc20aab
TT		 996 fsl_sata_reg_t *reg;
997
998 /* first SATA controller */
999 reg = (void *)CONFIG_SYS_MPC85xx_SATA1_ADDR;
1000 clrbits_le32(&reg->hcontrol, HCONTROL_ENTERPRISE_EN);
1001
1002 /* second SATA controller */
1003 reg = (void *)CONFIG_SYS_MPC85xx_SATA2_ADDR;
1004 clrbits_le32(&reg->hcontrol, HCONTROL_ENTERPRISE_EN);
1005 }
1006#endif
1007
f13c9156 1008 init_used_tlb_cams();
fbc20aab 1009
42d1f039
WD		 1010 return 0;
1011}
26f4cdba 1012
26f4cdba
KG		 1013void arch_preboot_os(void)
1014{
15fba327
KG		 1015 u32 msr;
1016
1017 /*
1018 * We are changing interrupt offsets and are about to boot the OS so
1019 * we need to make sure we disable all async interrupts. EE is already
1020 * disabled by the time we get called.
1021 */
1022 msr = mfmsr();
5344f7a2 1023 msr &= ~(MSR_ME|MSR_CE);
15fba327 1024 mtmsr(msr);
26f4cdba 1025}
f54fe87a 1026
10e40d54 1027#if defined(CONFIG_SATA) && defined(CONFIG_FSL_SATA)
f54fe87a
KG		 1028int sata_initialize(void)
1029{
1030 if (is_serdes_configured(SATA1) || is_serdes_configured(SATA2))
1031 return __sata_initialize();
1032
1033 return 1;
1034}
1035#endif
f9a33f1c
KG		 1036
1037void cpu_secondary_init_r(void)
1038{
2a44efeb
ZQ		 1039#ifdef CONFIG_U_QE
1040 uint qe_base = CONFIG_SYS_IMMR + 0x00140000; /* QE immr base */
1041#elif defined CONFIG_QE
f9a33f1c 1042 uint qe_base = CONFIG_SYS_IMMR + 0x00080000; /* QE immr base */
2a44efeb
ZQ		 1043#endif
1044
1045#ifdef CONFIG_QE
f9a33f1c
KG		 1046 qe_init(qe_base);
1047 qe_reset();
1048#endif
1049}
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AB		 1050
1051#ifdef CONFIG_BOARD_LATE_INIT
1052int board_late_init(void)
1053{
1054#ifdef CONFIG_CHAIN_OF_TRUST
1055 fsl_setenv_chain_of_trust();
1056#endif
1057
1058 return 0;
1059}
1060#endif
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