[people/ms/u-boot.git] / board / amcc / canyonlands / canyonlands.c

/*
 * (C) Copyright 2008
 * Stefan Roese, DENX Software Engineering, sr@denx.de.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <asm/ppc440.h>
#include <libfdt.h>
#include <fdt_support.h>
#include <i2c.h>
#include <asm/processor.h>
#include <asm/io.h>
#include <asm/mmu.h>
#include <asm/4xx_pcie.h>
#include <asm/ppc4xx-gpio.h>
#include <linux/errno.h>
#include <usb.h>

extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */

DECLARE_GLOBAL_DATA_PTR;

struct board_bcsr {
	u8	board_id;
	u8	cpld_rev;
	u8	led_user;
	u8	board_status;
	u8	reset_ctrl;
	u8	flash_ctrl;
	u8	eth_ctrl;
	u8	usb_ctrl;
	u8	irq_ctrl;
};

#define BOARD_CANYONLANDS_PCIE	1
#define BOARD_CANYONLANDS_SATA	2
#define BOARD_GLACIER		3
#define BOARD_ARCHES		4

/*
 * Override the default functions in arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c with
 * board specific values.
 */
#if defined(CONFIG_ARCHES)
u32 ddr_wrdtr(u32 default_val) {
	return (SDRAM_WRDTR_LLWP_1_CYC | SDRAM_WRDTR_WTR_0_DEG | 0x823);
}
#else
u32 ddr_wrdtr(u32 default_val) {
	return (SDRAM_WRDTR_LLWP_1_CYC | SDRAM_WRDTR_WTR_180_DEG_ADV | 0x823);
}

u32 ddr_clktr(u32 default_val) {
	return (SDRAM_CLKTR_CLKP_90_DEG_ADV);
}
#endif

#if defined(CONFIG_ARCHES)
/*
 * FPGA read/write helper macros
 */
static inline int board_fpga_read(int offset)
{
	return in_8((void *)(CONFIG_SYS_FPGA_BASE + offset));
}

static inline void board_fpga_write(int offset, int data)
{
	out_8((void *)(CONFIG_SYS_FPGA_BASE + offset), data);
}

/*
 * CPLD read/write helper macros
 */
static inline int board_cpld_read(int offset)
{
	int data;

	out_8((void *)(CONFIG_SYS_CPLD_ADDR), offset);
	data = in_8((void *)(CONFIG_SYS_CPLD_DATA));

	return data;
}

static inline void board_cpld_write(int offset, int data)
{
	out_8((void *)(CONFIG_SYS_CPLD_ADDR), offset);
	out_8((void *)(CONFIG_SYS_CPLD_DATA), data);
}
#else
static int pvr_460ex(void)
{
	u32 pvr = get_pvr();

	if ((pvr == PVR_460EX_RA) || (pvr == PVR_460EX_SE_RA) ||
	    (pvr == PVR_460EX_RB))
		return 1;

	return 0;
}
#endif	/* defined(CONFIG_ARCHES) */

int board_early_init_f(void)
{
#if !defined(CONFIG_ARCHES)
	u32 sdr0_cust0;
	struct board_bcsr *bcsr_data =
		(struct board_bcsr *)CONFIG_SYS_BCSR_BASE;

#endif

	/*
	 * Setup the interrupt controller polarities, triggers, etc.
	 */
	mtdcr(UIC0SR, 0xffffffff);	/* clear all */
	mtdcr(UIC0ER, 0x00000000);	/* disable all */
	mtdcr(UIC0CR, 0x00000005);	/* ATI & UIC1 crit are critical */
	mtdcr(UIC0PR, 0xffffffff);	/* per ref-board manual */
	mtdcr(UIC0TR, 0x00000000);	/* per ref-board manual */
	mtdcr(UIC0VR, 0x00000000);	/* int31 highest, base=0x000 */
	mtdcr(UIC0SR, 0xffffffff);	/* clear all */

	mtdcr(UIC1SR, 0xffffffff);	/* clear all */
	mtdcr(UIC1ER, 0x00000000);	/* disable all */
	mtdcr(UIC1CR, 0x00000000);	/* all non-critical */
	mtdcr(UIC1PR, 0xffffffff);	/* per ref-board manual */
	mtdcr(UIC1TR, 0x00000000);	/* per ref-board manual */
	mtdcr(UIC1VR, 0x00000000);	/* int31 highest, base=0x000 */
	mtdcr(UIC1SR, 0xffffffff);	/* clear all */

	mtdcr(UIC2SR, 0xffffffff);	/* clear all */
	mtdcr(UIC2ER, 0x00000000);	/* disable all */
	mtdcr(UIC2CR, 0x00000000);	/* all non-critical */
	mtdcr(UIC2PR, 0xffffffff);	/* per ref-board manual */
	mtdcr(UIC2TR, 0x00000000);	/* per ref-board manual */
	mtdcr(UIC2VR, 0x00000000);	/* int31 highest, base=0x000 */
	mtdcr(UIC2SR, 0xffffffff);	/* clear all */

	mtdcr(UIC3SR, 0xffffffff);	/* clear all */
	mtdcr(UIC3ER, 0x00000000);	/* disable all */
	mtdcr(UIC3CR, 0x00000000);	/* all non-critical */
	mtdcr(UIC3PR, 0xffffffff);	/* per ref-board manual */
	mtdcr(UIC3TR, 0x00000000);	/* per ref-board manual */
	mtdcr(UIC3VR, 0x00000000);	/* int31 highest, base=0x000 */
	mtdcr(UIC3SR, 0xffffffff);	/* clear all */

#if !defined(CONFIG_ARCHES)
	/* SDR Setting - enable NDFC */
	mfsdr(SDR0_CUST0, sdr0_cust0);
	sdr0_cust0 = SDR0_CUST0_MUX_NDFC_SEL	|
		SDR0_CUST0_NDFC_ENABLE		|
		SDR0_CUST0_NDFC_BW_8_BIT	|
		SDR0_CUST0_NDFC_ARE_MASK	|
		SDR0_CUST0_NDFC_BAC_ENCODE(3)	|
		(0x80000000 >> (28 + CONFIG_SYS_NAND_CS));
	mtsdr(SDR0_CUST0, sdr0_cust0);
#endif

	/*
	 * Configure PFC (Pin Function Control) registers
	 * UART0: 4 pins
	 */
	mtsdr(SDR0_PFC1, 0x00040000);

	/* Enable PCI host functionality in SDR0_PCI0 */
	mtsdr(SDR0_PCI0, 0xe0000000);

#if !defined(CONFIG_ARCHES)
	/* Enable ethernet and take out of reset */
	out_8(&bcsr_data->eth_ctrl, 0) ;

	/* Remove NOR-FLASH, NAND-FLASH & EEPROM hardware write protection */
	out_8(&bcsr_data->flash_ctrl, 0) ;
	mtsdr(SDR0_SRST1, 0);	/* Pull AHB out of reset default=1 */

	/* Setup PLB4-AHB bridge based on the system address map */
	mtdcr(AHB_TOP, 0x8000004B);
	mtdcr(AHB_BOT, 0x8000004B);

#endif

	return 0;
}

#if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_BOARD_INIT)
int board_usb_init(int index, enum usb_init_type init)
{
	struct board_bcsr *bcsr_data =
		(struct board_bcsr *)CONFIG_SYS_BCSR_BASE;
	u8 val;

	/* Enable USB host & USB-OTG */
	val = in_8(&bcsr_data->usb_ctrl);
	val &= ~(BCSR_USBCTRL_OTG_RST | BCSR_USBCTRL_HOST_RST);
	out_8(&bcsr_data->usb_ctrl, val);

	/*
	 * Configure USB-STP pins as alternate and not GPIO
	 * It seems to be neccessary to configure the STP pins as GPIO
	 * input at powerup (perhaps while USB reset is asserted). So
	 * we configure those pins to their "real" function now.
	 */
	gpio_config(16, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1);
	gpio_config(19, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1);

	return 0;
}

int usb_board_stop(void)
{
	struct board_bcsr *bcsr_data =
		(struct board_bcsr *)CONFIG_SYS_BCSR_BASE;
	u8 val;

	/* Disable USB host & USB-OTG */
	val = in_8(&bcsr_data->usb_ctrl);
	val |= (BCSR_USBCTRL_OTG_RST | BCSR_USBCTRL_HOST_RST);
	out_8(&bcsr_data->usb_ctrl, val);

	/* Reconfigure USB-STP pins as input */
	gpio_config(16, GPIO_IN , GPIO_SEL, GPIO_OUT_0);
	gpio_config(19, GPIO_IN , GPIO_SEL, GPIO_OUT_0);

	return 0;
}

int board_usb_cleanup(int index, enum usb_init_type init)
{
	return usb_board_stop();
}
#endif /* CONFIG_USB_OHCI_NEW && CONFIG_SYS_USB_OHCI_BOARD_INIT */

#if !defined(CONFIG_ARCHES)
static void canyonlands_sata_init(int board_type)
{
	u32 reg;

	if (board_type == BOARD_CANYONLANDS_SATA) {
		/* Put SATA in reset */
		SDR_WRITE(SDR0_SRST1, 0x00020001);

		/* Set the phy for SATA, not PCI-E port 0 */
		reg = SDR_READ(PESDR0_PHY_CTL_RST);
		SDR_WRITE(PESDR0_PHY_CTL_RST, (reg & 0xeffffffc) | 0x00000001);
		reg = SDR_READ(PESDR0_L0CLK);
		SDR_WRITE(PESDR0_L0CLK, (reg & 0xfffffff8) | 0x00000007);
		SDR_WRITE(PESDR0_L0CDRCTL, 0x00003111);
		SDR_WRITE(PESDR0_L0DRV, 0x00000104);

		/* Bring SATA out of reset */
		SDR_WRITE(SDR0_SRST1, 0x00000000);
	}
}
#endif	/* !defined(CONFIG_ARCHES) */

int get_cpu_num(void)
{
	int cpu = NA_OR_UNKNOWN_CPU;

#if defined(CONFIG_ARCHES)
	int cpu_num;

	cpu_num = board_fpga_read(0x3);

	/* sanity check; assume cpu numbering starts and increments from 0 */
	if ((cpu_num >= 0) && (cpu_num < CONFIG_BD_NUM_CPUS))
		cpu = cpu_num;
#endif

	return cpu;
}

#if !defined(CONFIG_ARCHES)
int checkboard(void)
{
	struct board_bcsr *bcsr_data =
		(struct board_bcsr *)CONFIG_SYS_BCSR_BASE;
	char buf[64];
	int i = getenv_f("serial#", buf, sizeof(buf));

	if (pvr_460ex()) {
		printf("Board: Canyonlands - AMCC PPC460EX Evaluation Board");
		if (in_8(&bcsr_data->board_status) & BCSR_SELECT_PCIE)
			gd->board_type = BOARD_CANYONLANDS_PCIE;
		else
			gd->board_type = BOARD_CANYONLANDS_SATA;
	} else {
		printf("Board: Glacier - AMCC PPC460GT Evaluation Board");
		gd->board_type = BOARD_GLACIER;
	}

	switch (gd->board_type) {
	case BOARD_CANYONLANDS_PCIE:
	case BOARD_GLACIER:
		puts(", 2*PCIe");
		break;

	case BOARD_CANYONLANDS_SATA:
		puts(", 1*PCIe/1*SATA");
		break;
	}

	printf(", Rev. %X", in_8(&bcsr_data->cpld_rev));

	if (i > 0) {
		puts(", serial# ");
		puts(buf);
	}
	putc('\n');

	canyonlands_sata_init(gd->board_type);

	return (0);
}

#else	/* defined(CONFIG_ARCHES) */

int checkboard(void)
{
	char *s = getenv("serial#");

	printf("Board: Arches - AMCC DUAL PPC460GT Reference Design\n");
	printf("       Revision %02x.%02x ",
				board_fpga_read(0x0), board_fpga_read(0x1));

	gd->board_type = BOARD_ARCHES;

	/* Only CPU0 has access to CPLD registers */
	if (get_cpu_num() == 0) {
		u8 cfg_sw = board_cpld_read(0x1);
		printf("(FPGA=%02x, CPLD=%02x)\n",
				board_fpga_read(0x2), board_cpld_read(0x0));
		printf("       Configuration Switch %d%d%d%d\n",
				((cfg_sw >> 3) & 0x01),
				((cfg_sw >> 2) & 0x01),
				((cfg_sw >> 1) & 0x01),
				((cfg_sw >> 0) & 0x01));
	} else
		printf("(FPGA=%02x, CPLD=xx)\n", board_fpga_read(0x2));


	if (s != NULL)
		printf("       Serial# %s\n", s);

	return 0;
}
#endif	/* !defined(CONFIG_ARCHES) */

#if defined(CONFIG_PCI)
int board_pcie_first(void)
{
	/*
	 * Canyonlands with SATA enabled has only one PCIe slot
	 * (2nd one).
	 */
	if (gd->board_type == BOARD_CANYONLANDS_SATA)
		return 1;

	return 0;
}
#endif /* CONFIG_PCI */

int board_early_init_r (void)
{
	/*
	 * Canyonlands has 64MBytes of NOR FLASH (Spansion 29GL512), but the
	 * boot EBC mapping only supports a maximum of 16MBytes
	 * (4.ff00.0000 - 4.ffff.ffff).
	 * To solve this problem, the FLASH has to get remapped to another
	 * EBC address which accepts bigger regions:
	 *
	 * 0xfc00.0000 -> 4.cc00.0000
	 */

	/* Remap the NOR FLASH to 0xcc00.0000 ... 0xcfff.ffff */
	mtebc(PB0CR, CONFIG_SYS_FLASH_BASE_PHYS_L | 0xda000);

	/* Remove TLB entry of boot EBC mapping */
	remove_tlb(CONFIG_SYS_BOOT_BASE_ADDR, 16 << 20);

	/* Add TLB entry for 0xfc00.0000 -> 0x4.cc00.0000 */
	program_tlb(CONFIG_SYS_FLASH_BASE_PHYS, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_SIZE,
		    TLB_WORD2_I_ENABLE);

	/*
	 * Now accessing of the whole 64Mbytes of NOR FLASH at virtual address
	 * 0xfc00.0000 is possible
	 */

	/*
	 * Clear potential errors resulting from auto-calibration.
	 * If not done, then we could get an interrupt later on when
	 * exceptions are enabled.
	 */
	set_mcsr(get_mcsr());

	return 0;
}

#if !defined(CONFIG_ARCHES)
int misc_init_r(void)
{
	u32 sdr0_srst1 = 0;
	u32 eth_cfg;
	u8 val;

	/*
	 * Set EMAC mode/configuration (GMII, SGMII, RGMII...).
	 * This is board specific, so let's do it here.
	 */
	mfsdr(SDR0_ETH_CFG, eth_cfg);
	/* disable SGMII mode */
	eth_cfg &= ~(SDR0_ETH_CFG_SGMII2_ENABLE |
		     SDR0_ETH_CFG_SGMII1_ENABLE |
		     SDR0_ETH_CFG_SGMII0_ENABLE);
	/* Set the for 2 RGMII mode */
	/* GMC0 EMAC4_0, GMC0 EMAC4_1, RGMII Bridge 0 */
	eth_cfg &= ~SDR0_ETH_CFG_GMC0_BRIDGE_SEL;
	if (pvr_460ex())
		eth_cfg |= SDR0_ETH_CFG_GMC1_BRIDGE_SEL;
	else
		eth_cfg &= ~SDR0_ETH_CFG_GMC1_BRIDGE_SEL;
	mtsdr(SDR0_ETH_CFG, eth_cfg);

	/*
	 * The AHB Bridge core is held in reset after power-on or reset
	 * so enable it now
	 */
	mfsdr(SDR0_SRST1, sdr0_srst1);
	sdr0_srst1 &= ~SDR0_SRST1_AHB;
	mtsdr(SDR0_SRST1, sdr0_srst1);

	/*
	 * RTC/M41T62:
	 * Disable square wave output: Batterie will be drained
	 * quickly, when this output is not disabled
	 */
	val = i2c_reg_read(CONFIG_SYS_I2C_RTC_ADDR, 0xa);
	val &= ~0x40;
	i2c_reg_write(CONFIG_SYS_I2C_RTC_ADDR, 0xa, val);

	return 0;
}

#else	/* defined(CONFIG_ARCHES) */

int misc_init_r(void)
{
	u32 eth_cfg = 0;
	u32 eth_pll;
	u32 reg;

	/*
	 * Set EMAC mode/configuration (GMII, SGMII, RGMII...).
	 * This is board specific, so let's do it here.
	 */

	/* enable SGMII mode */
	eth_cfg |= (SDR0_ETH_CFG_SGMII0_ENABLE |
			SDR0_ETH_CFG_SGMII1_ENABLE |
			SDR0_ETH_CFG_SGMII2_ENABLE);

	/* Set EMAC for MDIO */
	eth_cfg |= SDR0_ETH_CFG_MDIO_SEL_EMAC0;

	/* bypass the TAHOE0/TAHOE1 cores for U-Boot */
	eth_cfg |= (SDR0_ETH_CFG_TAHOE0_BYPASS | SDR0_ETH_CFG_TAHOE1_BYPASS);

	mtsdr(SDR0_ETH_CFG, eth_cfg);

	/* reset all SGMII interfaces */
	mfsdr(SDR0_SRST1,   reg);
	reg |= (SDR0_SRST1_SGMII0 | SDR0_SRST1_SGMII1 | SDR0_SRST1_SGMII2);
	mtsdr(SDR0_SRST1, reg);
	mtsdr(SDR0_ETH_STS, 0xFFFFFFFF);
	mtsdr(SDR0_SRST1,   0x00000000);

	do {
		mfsdr(SDR0_ETH_PLL, eth_pll);
	} while (!(eth_pll & SDR0_ETH_PLL_PLLLOCK));

	return 0;
}
#endif	/* !defined(CONFIG_ARCHES) */

#ifdef CONFIG_OF_BOARD_SETUP
extern int __ft_board_setup(void *blob, bd_t *bd);

int ft_board_setup(void *blob, bd_t *bd)
{
	__ft_board_setup(blob, bd);

	if (gd->board_type == BOARD_CANYONLANDS_SATA) {
		/*
		 * When SATA is selected we need to disable the first PCIe
		 * node in the device tree, so that Linux doesn't initialize
		 * it.
		 */
		fdt_find_and_setprop(blob, "/plb/pciex@d00000000", "status",
				     "disabled", sizeof("disabled"), 1);
	}

	if (gd->board_type == BOARD_CANYONLANDS_PCIE) {
		/*
		 * When PCIe is selected we need to disable the SATA
		 * node in the device tree, so that Linux doesn't initialize
		 * it.
		 */
		fdt_find_and_setprop(blob, "/plb/sata@bffd1000", "status",
				     "disabled", sizeof("disabled"), 1);
	}

	return 0;
}
#endif /* CONFIG_OF_BOARD_SETUP */
Commit	Line	Data
8e1a3fe5 SR	1	/*
	2	* (C) Copyright 2008
	3	* Stefan Roese, DENX Software Engineering, sr@denx.de.
	4	*
1a459660	5	* SPDX-License-Identifier: GPL-2.0+
8e1a3fe5 SR	6	*/
	7
	8	#include <common.h>
b36df561	9	#include <asm/ppc440.h>
8e1a3fe5 SR	10	#include <libfdt.h>
8e1a3fe5 SR	11	#include <fdt_support.h>
212ed906	12	#include <i2c.h>
8e1a3fe5 SR	13	#include <asm/processor.h>
	14	#include <asm/io.h>
	15	#include <asm/mmu.h>
	16	#include <asm/4xx_pcie.h>
09887762	17	#include <asm/ppc4xx-gpio.h>
1221ce45	18	#include <linux/errno.h>
16297cfb	19	#include <usb.h>
8e1a3fe5	20
6d0f6bcf	21	extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
8e1a3fe5 SR	22
	23	DECLARE_GLOBAL_DATA_PTR;
	24
98303292 SR	25	struct board_bcsr {
	26	u8 board_id;
	27	u8 cpld_rev;
	28	u8 led_user;
	29	u8 board_status;
	30	u8 reset_ctrl;
	31	u8 flash_ctrl;
	32	u8 eth_ctrl;
	33	u8 usb_ctrl;
	34	u8 irq_ctrl;
17a68444	35	};
cc8e839a SR	36
	37	#define BOARD_CANYONLANDS_PCIE 1
	38	#define BOARD_CANYONLANDS_SATA 2
	39	#define BOARD_GLACIER 3
f09f09d3 AG	40	#define BOARD_ARCHES 4
f09f09d3 AG	41
f3ed3c9b	42	/*
a47a12be	43	* Override the default functions in arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c with
f3ed3c9b SR	44	* board specific values.
	45	*/
	46	#if defined(CONFIG_ARCHES)
	47	u32 ddr_wrdtr(u32 default_val) {
	48	return (SDRAM_WRDTR_LLWP_1_CYC \| SDRAM_WRDTR_WTR_0_DEG \| 0x823);
	49	}
	50	#else
	51	u32 ddr_wrdtr(u32 default_val) {
	52	return (SDRAM_WRDTR_LLWP_1_CYC \| SDRAM_WRDTR_WTR_180_DEG_ADV \| 0x823);
	53	}
	54
	55	u32 ddr_clktr(u32 default_val) {
	56	return (SDRAM_CLKTR_CLKP_90_DEG_ADV);
	57	}
	58	#endif
	59
f09f09d3 AG	60	#if defined(CONFIG_ARCHES)
	61	/*
	62	* FPGA read/write helper macros
	63	*/
	64	static inline int board_fpga_read(int offset)
	65	{
63a7578e	66	return in_8((void *)(CONFIG_SYS_FPGA_BASE + offset));
f09f09d3 AG	67	}
	68
	69	static inline void board_fpga_write(int offset, int data)
	70	{
	71	out_8((void *)(CONFIG_SYS_FPGA_BASE + offset), data);
	72	}
	73
	74	/*
	75	* CPLD read/write helper macros
	76	*/
	77	static inline int board_cpld_read(int offset)
	78	{
	79	int data;
	80
	81	out_8((void *)(CONFIG_SYS_CPLD_ADDR), offset);
	82	data = in_8((void *)(CONFIG_SYS_CPLD_DATA));
	83
	84	return data;
	85	}
	86
	87	static inline void board_cpld_write(int offset, int data)
	88	{
	89	out_8((void *)(CONFIG_SYS_CPLD_ADDR), offset);
	90	out_8((void *)(CONFIG_SYS_CPLD_DATA), data);
	91	}
c3fa4f0c SR	92	#else
	93	static int pvr_460ex(void)
	94	{
	95	u32 pvr = get_pvr();
	96
	97	if ((pvr == PVR_460EX_RA) \|\| (pvr == PVR_460EX_SE_RA) \|\|
	98	(pvr == PVR_460EX_RB))
	99	return 1;
	100
	101	return 0;
	102	}
f09f09d3	103	#endif /* defined(CONFIG_ARCHES) */
cc8e839a	104
8e1a3fe5 SR	105	int board_early_init_f(void)
8e1a3fe5 SR	106	{
f09f09d3	107	#if !defined(CONFIG_ARCHES)
8e1a3fe5	108	u32 sdr0_cust0;
17a68444 RS	109	struct board_bcsr *bcsr_data =
	110	(struct board_bcsr *)CONFIG_SYS_BCSR_BASE;
	111
f09f09d3	112	#endif
8e1a3fe5	113
1c2926ab	114	/*
8e1a3fe5	115	* Setup the interrupt controller polarities, triggers, etc.
1c2926ab	116	*/
952e7760 SR	117	mtdcr(UIC0SR, 0xffffffff); /* clear all */
	118	mtdcr(UIC0ER, 0x00000000); /* disable all */
	119	mtdcr(UIC0CR, 0x00000005); /* ATI & UIC1 crit are critical */
	120	mtdcr(UIC0PR, 0xffffffff); /* per ref-board manual */
	121	mtdcr(UIC0TR, 0x00000000); /* per ref-board manual */
	122	mtdcr(UIC0VR, 0x00000000); /* int31 highest, base=0x000 */
	123	mtdcr(UIC0SR, 0xffffffff); /* clear all */
	124
	125	mtdcr(UIC1SR, 0xffffffff); /* clear all */
	126	mtdcr(UIC1ER, 0x00000000); /* disable all */
	127	mtdcr(UIC1CR, 0x00000000); /* all non-critical */
	128	mtdcr(UIC1PR, 0xffffffff); /* per ref-board manual */
	129	mtdcr(UIC1TR, 0x00000000); /* per ref-board manual */
	130	mtdcr(UIC1VR, 0x00000000); /* int31 highest, base=0x000 */
	131	mtdcr(UIC1SR, 0xffffffff); /* clear all */
	132
	133	mtdcr(UIC2SR, 0xffffffff); /* clear all */
	134	mtdcr(UIC2ER, 0x00000000); /* disable all */
	135	mtdcr(UIC2CR, 0x00000000); /* all non-critical */
	136	mtdcr(UIC2PR, 0xffffffff); /* per ref-board manual */
	137	mtdcr(UIC2TR, 0x00000000); /* per ref-board manual */
	138	mtdcr(UIC2VR, 0x00000000); /* int31 highest, base=0x000 */
	139	mtdcr(UIC2SR, 0xffffffff); /* clear all */
	140
	141	mtdcr(UIC3SR, 0xffffffff); /* clear all */
	142	mtdcr(UIC3ER, 0x00000000); /* disable all */
	143	mtdcr(UIC3CR, 0x00000000); /* all non-critical */
	144	mtdcr(UIC3PR, 0xffffffff); /* per ref-board manual */
	145	mtdcr(UIC3TR, 0x00000000); /* per ref-board manual */
	146	mtdcr(UIC3VR, 0x00000000); /* int31 highest, base=0x000 */
	147	mtdcr(UIC3SR, 0xffffffff); /* clear all */
8e1a3fe5	148
f09f09d3	149	#if !defined(CONFIG_ARCHES)
8e1a3fe5 SR	150	/* SDR Setting - enable NDFC */
	151	mfsdr(SDR0_CUST0, sdr0_cust0);
	152	sdr0_cust0 = SDR0_CUST0_MUX_NDFC_SEL \|
	153	SDR0_CUST0_NDFC_ENABLE \|
	154	SDR0_CUST0_NDFC_BW_8_BIT \|
	155	SDR0_CUST0_NDFC_ARE_MASK \|
	156	SDR0_CUST0_NDFC_BAC_ENCODE(3) \|
6d0f6bcf	157	(0x80000000 >> (28 + CONFIG_SYS_NAND_CS));
8e1a3fe5	158	mtsdr(SDR0_CUST0, sdr0_cust0);
f09f09d3	159	#endif
8e1a3fe5 SR	160
	161	/*
	162	* Configure PFC (Pin Function Control) registers
	163	* UART0: 4 pins
	164	*/
	165	mtsdr(SDR0_PFC1, 0x00040000);
	166
	167	/* Enable PCI host functionality in SDR0_PCI0 */
	168	mtsdr(SDR0_PCI0, 0xe0000000);
	169
f09f09d3	170	#if !defined(CONFIG_ARCHES)
8e1a3fe5	171	/* Enable ethernet and take out of reset */
17a68444	172	out_8(&bcsr_data->eth_ctrl, 0) ;
8e1a3fe5 SR	173
8e1a3fe5 SR	174	/* Remove NOR-FLASH, NAND-FLASH & EEPROM hardware write protection */
17a68444	175	out_8(&bcsr_data->flash_ctrl, 0) ;
8e1a3fe5 SR	176	mtsdr(SDR0_SRST1, 0); /* Pull AHB out of reset default=1 */
8e1a3fe5 SR	177
41712b4e SR	178	/* Setup PLB4-AHB bridge based on the system address map */
	179	mtdcr(AHB_TOP, 0x8000004B);
	180	mtdcr(AHB_BOT, 0x8000004B);
	181
f09f09d3	182	#endif
41712b4e	183
8e1a3fe5 SR	184	return 0;
	185	}
	186
17a68444	187	#if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_BOARD_INIT)
bba67914	188	int board_usb_init(int index, enum usb_init_type init)
17a68444 RS	189	{
	190	struct board_bcsr *bcsr_data =
	191	(struct board_bcsr *)CONFIG_SYS_BCSR_BASE;
	192	u8 val;
	193
	194	/* Enable USB host & USB-OTG */
	195	val = in_8(&bcsr_data->usb_ctrl);
	196	val &= ~(BCSR_USBCTRL_OTG_RST \| BCSR_USBCTRL_HOST_RST);
	197	out_8(&bcsr_data->usb_ctrl, val);
	198
709d9481 RS	199	/*
	200	* Configure USB-STP pins as alternate and not GPIO
	201	* It seems to be neccessary to configure the STP pins as GPIO
	202	* input at powerup (perhaps while USB reset is asserted). So
	203	* we configure those pins to their "real" function now.
	204	*/
	205	gpio_config(16, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1);
	206	gpio_config(19, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1);
	207
17a68444 RS	208	return 0;
	209	}
	210
	211	int usb_board_stop(void)
	212	{
	213	struct board_bcsr *bcsr_data =
	214	(struct board_bcsr *)CONFIG_SYS_BCSR_BASE;
	215	u8 val;
	216
	217	/* Disable USB host & USB-OTG */
	218	val = in_8(&bcsr_data->usb_ctrl);
	219	val \|= (BCSR_USBCTRL_OTG_RST \| BCSR_USBCTRL_HOST_RST);
	220	out_8(&bcsr_data->usb_ctrl, val);
	221
709d9481 RS	222	/* Reconfigure USB-STP pins as input */
	223	gpio_config(16, GPIO_IN , GPIO_SEL, GPIO_OUT_0);
	224	gpio_config(19, GPIO_IN , GPIO_SEL, GPIO_OUT_0);
	225
17a68444 RS	226	return 0;
	227	}
	228
bba67914	229	int board_usb_cleanup(int index, enum usb_init_type init)
17a68444 RS	230	{
	231	return usb_board_stop();
	232	}
	233	#endif /* CONFIG_USB_OHCI_NEW && CONFIG_SYS_USB_OHCI_BOARD_INIT */
	234
f09f09d3	235	#if !defined(CONFIG_ARCHES)
1c2926ab SR	236	static void canyonlands_sata_init(int board_type)
	237	{
	238	u32 reg;
	239
	240	if (board_type == BOARD_CANYONLANDS_SATA) {
	241	/* Put SATA in reset */
	242	SDR_WRITE(SDR0_SRST1, 0x00020001);
	243
	244	/* Set the phy for SATA, not PCI-E port 0 */
	245	reg = SDR_READ(PESDR0_PHY_CTL_RST);
	246	SDR_WRITE(PESDR0_PHY_CTL_RST, (reg & 0xeffffffc) \| 0x00000001);
	247	reg = SDR_READ(PESDR0_L0CLK);
	248	SDR_WRITE(PESDR0_L0CLK, (reg & 0xfffffff8) \| 0x00000007);
	249	SDR_WRITE(PESDR0_L0CDRCTL, 0x00003111);
	250	SDR_WRITE(PESDR0_L0DRV, 0x00000104);
	251
	252	/* Bring SATA out of reset */
	253	SDR_WRITE(SDR0_SRST1, 0x00000000);
	254	}
	255	}
f09f09d3 AG	256	#endif /* !defined(CONFIG_ARCHES) */
	257
	258	int get_cpu_num(void)
	259	{
	260	int cpu = NA_OR_UNKNOWN_CPU;
	261
	262	#if defined(CONFIG_ARCHES)
	263	int cpu_num;
	264
	265	cpu_num = board_fpga_read(0x3);
	266
	267	/* sanity check; assume cpu numbering starts and increments from 0 */
	268	if ((cpu_num >= 0) && (cpu_num < CONFIG_BD_NUM_CPUS))
	269	cpu = cpu_num;
	270	#endif
	271
	272	return cpu;
	273	}
1c2926ab	274
f09f09d3	275	#if !defined(CONFIG_ARCHES)
1c2926ab	276	int checkboard(void)
8e1a3fe5	277	{
17a68444 RS	278	struct board_bcsr *bcsr_data =
17a68444 RS	279	(struct board_bcsr *)CONFIG_SYS_BCSR_BASE;
f0c0b3a9 WD	280	char buf[64];
f0c0b3a9 WD	281	int i = getenv_f("serial#", buf, sizeof(buf));
8e1a3fe5	282
c3fa4f0c	283	if (pvr_460ex()) {
8e1a3fe5	284	printf("Board: Canyonlands - AMCC PPC460EX Evaluation Board");
17a68444	285	if (in_8(&bcsr_data->board_status) & BCSR_SELECT_PCIE)
cc8e839a SR	286	gd->board_type = BOARD_CANYONLANDS_PCIE;
	287	else
	288	gd->board_type = BOARD_CANYONLANDS_SATA;
c3fa4f0c SR	289	} else {
	290	printf("Board: Glacier - AMCC PPC460GT Evaluation Board");
	291	gd->board_type = BOARD_GLACIER;
cc8e839a SR	292	}
	293
	294	switch (gd->board_type) {
	295	case BOARD_CANYONLANDS_PCIE:
	296	case BOARD_GLACIER:
	297	puts(", 2*PCIe");
	298	break;
	299
	300	case BOARD_CANYONLANDS_SATA:
	301	puts(", 1PCIe/1SATA");
	302	break;
	303	}
	304
17a68444	305	printf(", Rev. %X", in_8(&bcsr_data->cpld_rev));
8e1a3fe5	306
f0c0b3a9	307	if (i > 0) {
8e1a3fe5	308	puts(", serial# ");
f0c0b3a9	309	puts(buf);
8e1a3fe5 SR	310	}
	311	putc('\n');
	312
1c2926ab SR	313	canyonlands_sata_init(gd->board_type);
1c2926ab SR	314
8e1a3fe5 SR	315	return (0);
	316	}
	317
f09f09d3 AG	318	#else /* defined(CONFIG_ARCHES) */
	319
	320	int checkboard(void)
	321	{
	322	char *s = getenv("serial#");
	323
	324	printf("Board: Arches - AMCC DUAL PPC460GT Reference Design\n");
	325	printf(" Revision %02x.%02x ",
	326	board_fpga_read(0x0), board_fpga_read(0x1));
	327
	328	gd->board_type = BOARD_ARCHES;
	329
	330	/* Only CPU0 has access to CPLD registers */
	331	if (get_cpu_num() == 0) {
	332	u8 cfg_sw = board_cpld_read(0x1);
	333	printf("(FPGA=%02x, CPLD=%02x)\n",
	334	board_fpga_read(0x2), board_cpld_read(0x0));
	335	printf(" Configuration Switch %d%d%d%d\n",
	336	((cfg_sw >> 3) & 0x01),
	337	((cfg_sw >> 2) & 0x01),
	338	((cfg_sw >> 1) & 0x01),
	339	((cfg_sw >> 0) & 0x01));
	340	} else
	341	printf("(FPGA=%02x, CPLD=xx)\n", board_fpga_read(0x2));
	342
	343
	344	if (s != NULL)
	345	printf(" Serial# %s\n", s);
	346
	347	return 0;
	348	}
	349	#endif /* !defined(CONFIG_ARCHES) */
	350
8e1a3fe5	351	#if defined(CONFIG_PCI)
b0b86746	352	int board_pcie_first(void)
8e1a3fe5	353	{
cc8e839a SR	354	/*
	355	* Canyonlands with SATA enabled has only one PCIe slot
	356	* (2nd one).
	357	*/
	358	if (gd->board_type == BOARD_CANYONLANDS_SATA)
b0b86746	359	return 1;
8e1a3fe5	360
b0b86746	361	return 0;
8e1a3fe5 SR	362	}
	363	#endif /* CONFIG_PCI */
	364
	365	int board_early_init_r (void)
	366	{
	367	/*
	368	* Canyonlands has 64MBytes of NOR FLASH (Spansion 29GL512), but the
	369	* boot EBC mapping only supports a maximum of 16MBytes
	370	* (4.ff00.0000 - 4.ffff.ffff).
	371	* To solve this problem, the FLASH has to get remapped to another
	372	* EBC address which accepts bigger regions:
	373	*
	374	* 0xfc00.0000 -> 4.cc00.0000
8e1a3fe5 SR	375	*/
	376
	377	/* Remap the NOR FLASH to 0xcc00.0000 ... 0xcfff.ffff */
d1c3b275	378	mtebc(PB0CR, CONFIG_SYS_FLASH_BASE_PHYS_L \| 0xda000);
8e1a3fe5 SR	379
8e1a3fe5 SR	380	/* Remove TLB entry of boot EBC mapping */
6d0f6bcf	381	remove_tlb(CONFIG_SYS_BOOT_BASE_ADDR, 16 << 20);
8e1a3fe5 SR	382
8e1a3fe5 SR	383	/* Add TLB entry for 0xfc00.0000 -> 0x4.cc00.0000 */
6d0f6bcf	384	program_tlb(CONFIG_SYS_FLASH_BASE_PHYS, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_SIZE,
8e1a3fe5 SR	385	TLB_WORD2_I_ENABLE);
	386
	387	/*
	388	* Now accessing of the whole 64Mbytes of NOR FLASH at virtual address
	389	* 0xfc00.0000 is possible
	390	*/
	391
71665ebf SR	392	/*
	393	* Clear potential errors resulting from auto-calibration.
	394	* If not done, then we could get an interrupt later on when
	395	* exceptions are enabled.
	396	*/
	397	set_mcsr(get_mcsr());
	398
8e1a3fe5 SR	399	return 0;
	400	}
	401
f09f09d3	402	#if !defined(CONFIG_ARCHES)
8e1a3fe5 SR	403	int misc_init_r(void)
	404	{
	405	u32 sdr0_srst1 = 0;
	406	u32 eth_cfg;
212ed906	407	u8 val;
8e1a3fe5 SR	408
	409	/*
	410	* Set EMAC mode/configuration (GMII, SGMII, RGMII...).
	411	* This is board specific, so let's do it here.
	412	*/
	413	mfsdr(SDR0_ETH_CFG, eth_cfg);
	414	/* disable SGMII mode */
	415	eth_cfg &= ~(SDR0_ETH_CFG_SGMII2_ENABLE \|
	416	SDR0_ETH_CFG_SGMII1_ENABLE \|
	417	SDR0_ETH_CFG_SGMII0_ENABLE);
	418	/* Set the for 2 RGMII mode */
	419	/* GMC0 EMAC4_0, GMC0 EMAC4_1, RGMII Bridge 0 */
	420	eth_cfg &= ~SDR0_ETH_CFG_GMC0_BRIDGE_SEL;
c3fa4f0c	421	if (pvr_460ex())
4c9e8557 SR	422	eth_cfg \|= SDR0_ETH_CFG_GMC1_BRIDGE_SEL;
	423	else
	424	eth_cfg &= ~SDR0_ETH_CFG_GMC1_BRIDGE_SEL;
8e1a3fe5 SR	425	mtsdr(SDR0_ETH_CFG, eth_cfg);
	426
	427	/*
	428	* The AHB Bridge core is held in reset after power-on or reset
	429	* so enable it now
	430	*/
	431	mfsdr(SDR0_SRST1, sdr0_srst1);
	432	sdr0_srst1 &= ~SDR0_SRST1_AHB;
	433	mtsdr(SDR0_SRST1, sdr0_srst1);
	434
212ed906 SR	435	/*
	436	* RTC/M41T62:
	437	* Disable square wave output: Batterie will be drained
	438	* quickly, when this output is not disabled
	439	*/
6d0f6bcf	440	val = i2c_reg_read(CONFIG_SYS_I2C_RTC_ADDR, 0xa);
212ed906	441	val &= ~0x40;
6d0f6bcf	442	i2c_reg_write(CONFIG_SYS_I2C_RTC_ADDR, 0xa, val);
212ed906	443
8e1a3fe5 SR	444	return 0;
	445	}
	446
f09f09d3 AG	447	#else /* defined(CONFIG_ARCHES) */
	448
	449	int misc_init_r(void)
	450	{
	451	u32 eth_cfg = 0;
	452	u32 eth_pll;
	453	u32 reg;
	454
	455	/*
	456	* Set EMAC mode/configuration (GMII, SGMII, RGMII...).
	457	* This is board specific, so let's do it here.
	458	*/
	459
	460	/* enable SGMII mode */
	461	eth_cfg \|= (SDR0_ETH_CFG_SGMII0_ENABLE \|
	462	SDR0_ETH_CFG_SGMII1_ENABLE \|
	463	SDR0_ETH_CFG_SGMII2_ENABLE);
	464
	465	/* Set EMAC for MDIO */
	466	eth_cfg \|= SDR0_ETH_CFG_MDIO_SEL_EMAC0;
	467
	468	/* bypass the TAHOE0/TAHOE1 cores for U-Boot */
	469	eth_cfg \|= (SDR0_ETH_CFG_TAHOE0_BYPASS \| SDR0_ETH_CFG_TAHOE1_BYPASS);
	470
	471	mtsdr(SDR0_ETH_CFG, eth_cfg);
	472
	473	/* reset all SGMII interfaces */
	474	mfsdr(SDR0_SRST1, reg);
	475	reg \|= (SDR0_SRST1_SGMII0 \| SDR0_SRST1_SGMII1 \| SDR0_SRST1_SGMII2);
	476	mtsdr(SDR0_SRST1, reg);
	477	mtsdr(SDR0_ETH_STS, 0xFFFFFFFF);
	478	mtsdr(SDR0_SRST1, 0x00000000);
	479
	480	do {
	481	mfsdr(SDR0_ETH_PLL, eth_pll);
	482	} while (!(eth_pll & SDR0_ETH_PLL_PLLLOCK));
	483
	484	return 0;
	485	}
	486	#endif /* !defined(CONFIG_ARCHES) */
	487
7ffe3cd6	488	#ifdef CONFIG_OF_BOARD_SETUP
e895a4b0	489	extern int __ft_board_setup(void blob, bd_t bd);
26d37f00	490
e895a4b0	491	int ft_board_setup(void blob, bd_t bd)
8e1a3fe5	492	{
26d37f00	493	__ft_board_setup(blob, bd);
8e1a3fe5	494
16bedc66 SR	495	if (gd->board_type == BOARD_CANYONLANDS_SATA) {
	496	/*
	497	* When SATA is selected we need to disable the first PCIe
	498	* node in the device tree, so that Linux doesn't initialize
	499	* it.
	500	*/
8fd4166c SR	501	fdt_find_and_setprop(blob, "/plb/pciex@d00000000", "status",
8fd4166c SR	502	"disabled", sizeof("disabled"), 1);
16bedc66 SR	503	}
	504
	505	if (gd->board_type == BOARD_CANYONLANDS_PCIE) {
	506	/*
	507	* When PCIe is selected we need to disable the SATA
	508	* node in the device tree, so that Linux doesn't initialize
	509	* it.
	510	*/
8fd4166c SR	511	fdt_find_and_setprop(blob, "/plb/sata@bffd1000", "status",
8fd4166c SR	512	"disabled", sizeof("disabled"), 1);
16bedc66	513	}
e895a4b0 SG	514
e895a4b0 SG	515	return 0;
8e1a3fe5	516	}
7ffe3cd6	517	#endif /* CONFIG_OF_BOARD_SETUP */