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ppc4xx: Refactor ECC POST for AMCC Denali core
[people/ms/u-boot.git] / board / amcc / sequoia / sequoia.c
CommitLineData
887e2ec9 1/*
5a5958b7 2 * (C) Copyright 2006-2007
887e2ec9
SR		 3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
4 *
5 * (C) Copyright 2006
6 * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
511d0c72 7 * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com
887e2ec9
SR		 8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24
25#include <common.h>
13628884
SR		 26#include <libfdt.h>
27#include <fdt_support.h>
28#include <ppc440.h>
b05e8bf5 29#include <asm/gpio.h>
887e2ec9 30#include <asm/processor.h>
5a5958b7 31#include <asm/io.h>
1f84021a 32#include <asm/ppc4xx-intvec.h>
887e2ec9
SR		 33
34DECLARE_GLOBAL_DATA_PTR;
35
36extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
37
1b3c360c
SR		 38ulong flash_get_size (ulong base, int banknum);
39
887e2ec9
SR		 40int board_early_init_f(void)
41{
a78bc443
SR		 42 u32 sdr0_cust0;
43 u32 sdr0_pfc1, sdr0_pfc2;
44 u32 reg;
887e2ec9
SR		 45
46 mtdcr(ebccfga, xbcfg);
47 mtdcr(ebccfgd, 0xb8400000);
48
887e2ec9
SR		 49 /*--------------------------------------------------------------------
50 * Setup the interrupt controller polarities, triggers, etc.
51 *-------------------------------------------------------------------*/
52 mtdcr(uic0sr, 0xffffffff); /* clear all */
53 mtdcr(uic0er, 0x00000000); /* disable all */
54 mtdcr(uic0cr, 0x00000005); /* ATI & UIC1 crit are critical */
55 mtdcr(uic0pr, 0xfffff7ff); /* per ref-board manual */
56 mtdcr(uic0tr, 0x00000000); /* per ref-board manual */
57 mtdcr(uic0vr, 0x00000000); /* int31 highest, base=0x000 */
58 mtdcr(uic0sr, 0xffffffff); /* clear all */
59
60 mtdcr(uic1sr, 0xffffffff); /* clear all */
61 mtdcr(uic1er, 0x00000000); /* disable all */
62 mtdcr(uic1cr, 0x00000000); /* all non-critical */
63 mtdcr(uic1pr, 0xffffffff); /* per ref-board manual */
64 mtdcr(uic1tr, 0x00000000); /* per ref-board manual */
65 mtdcr(uic1vr, 0x00000000); /* int31 highest, base=0x000 */
66 mtdcr(uic1sr, 0xffffffff); /* clear all */
67
68 mtdcr(uic2sr, 0xffffffff); /* clear all */
69 mtdcr(uic2er, 0x00000000); /* disable all */
70 mtdcr(uic2cr, 0x00000000); /* all non-critical */
71 mtdcr(uic2pr, 0xffffffff); /* per ref-board manual */
72 mtdcr(uic2tr, 0x00000000); /* per ref-board manual */
73 mtdcr(uic2vr, 0x00000000); /* int31 highest, base=0x000 */
74 mtdcr(uic2sr, 0xffffffff); /* clear all */
75
76 /* 50MHz tmrclk */
d3471173 77 out_8((u8 *) CFG_BCSR_BASE + 0x04, 0x00);
887e2ec9
SR		 78
79 /* clear write protects */
d3471173 80 out_8((u8 *) CFG_BCSR_BASE + 0x07, 0x00);
887e2ec9
SR		 81
82 /* enable Ethernet */
d3471173 83 out_8((u8 *) CFG_BCSR_BASE + 0x08, 0x00);
887e2ec9
SR		 84
85 /* enable USB device */
d3471173 86 out_8((u8 *) CFG_BCSR_BASE + 0x09, 0x20);
887e2ec9
SR		 87
88 /* select Ethernet pins */
89 mfsdr(SDR0_PFC1, sdr0_pfc1);
90 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SELECT_MASK) | SDR0_PFC1_SELECT_CONFIG_4;
91 mfsdr(SDR0_PFC2, sdr0_pfc2);
92 sdr0_pfc2 = (sdr0_pfc2 & ~SDR0_PFC2_SELECT_MASK) | SDR0_PFC2_SELECT_CONFIG_4;
93 mtsdr(SDR0_PFC2, sdr0_pfc2);
94 mtsdr(SDR0_PFC1, sdr0_pfc1);
95
96 /* PCI arbiter enabled */
97 mfsdr(sdr_pci0, reg);
98 mtsdr(sdr_pci0, 0x80000000 | reg);
99
100 /* setup NAND FLASH */
101 mfsdr(SDR0_CUST0, sdr0_cust0);
511d0c72 102 sdr0_cust0 = SDR0_CUST0_MUX_NDFC_SEL |
887e2ec9
SR		 103 SDR0_CUST0_NDFC_ENABLE |
104 SDR0_CUST0_NDFC_BW_8_BIT |
105 SDR0_CUST0_NDFC_ARE_MASK |
106 (0x80000000 >> (28 + CFG_NAND_CS));
511d0c72 107 mtsdr(SDR0_CUST0, sdr0_cust0);
887e2ec9
SR		 108
109 return 0;
110}
111
112/*---------------------------------------------------------------------------+
113 | misc_init_r.
114 +---------------------------------------------------------------------------*/
115int misc_init_r(void)
116{
117 uint pbcr;
118 int size_val = 0;
a78bc443 119 u32 reg;
854bc8da 120#ifdef CONFIG_440EPX
887e2ec9
SR		 121 unsigned long usb2d0cr = 0;
122 unsigned long usb2phy0cr, usb2h0cr = 0;
123 unsigned long sdr0_pfc1;
124 char *act = getenv("usbact");
854bc8da 125#endif
887e2ec9
SR		 126
127 /*
128 * FLASH stuff...
129 */
130
131 /* Re-do sizing to get full correct info */
1b3c360c
SR		 132
133 /* adjust flash start and offset */
134 gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
135 gd->bd->bi_flashoffset = 0;
136
887e2ec9
SR		 137#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
138 mtdcr(ebccfga, pb3cr);
139#else
140 mtdcr(ebccfga, pb0cr);
141#endif
142 pbcr = mfdcr(ebccfgd);
143 switch (gd->bd->bi_flashsize) {
144 case 1 << 20:
145 size_val = 0;
146 break;
147 case 2 << 20:
148 size_val = 1;
149 break;
150 case 4 << 20:
151 size_val = 2;
152 break;
153 case 8 << 20:
154 size_val = 3;
155 break;
156 case 16 << 20:
157 size_val = 4;
158 break;
159 case 32 << 20:
160 size_val = 5;
161 break;
162 case 64 << 20:
163 size_val = 6;
164 break;
165 case 128 << 20:
166 size_val = 7;
167 break;
168 }
169 pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
170#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
171 mtdcr(ebccfga, pb3cr);
172#else
173 mtdcr(ebccfga, pb0cr);
174#endif
175 mtdcr(ebccfgd, pbcr);
176
1b3c360c
SR		 177 /*
178 * Re-check to get correct base address
179 */
180 flash_get_size(gd->bd->bi_flashstart, 0);
887e2ec9
SR		 181
182#ifdef CFG_ENV_IS_IN_FLASH
183 /* Monitor protection ON by default */
184 (void)flash_protect(FLAG_PROTECT_SET,
185 -CFG_MONITOR_LEN,
186 0xffffffff,
187 &flash_info[0]);
188
189 /* Env protection ON by default */
190 (void)flash_protect(FLAG_PROTECT_SET,
191 CFG_ENV_ADDR_REDUND,
192 CFG_ENV_ADDR_REDUND + 2*CFG_ENV_SECT_SIZE - 1,
193 &flash_info[0]);
194#endif
195
196 /*
197 * USB suff...
198 */
854bc8da 199#ifdef CONFIG_440EPX
887e2ec9
SR		 200 if (act == NULL || strcmp(act, "hostdev") == 0) {
201 /* SDR Setting */
511d0c72 202 mfsdr(SDR0_PFC1, sdr0_pfc1);
f780b833 203 mfsdr(SDR0_USB2D0CR, usb2d0cr);
511d0c72
WD		 204 mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
205 mfsdr(SDR0_USB2H0CR, usb2h0cr);
887e2ec9
SR		 206
207 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
208 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL; /*0*/
511d0c72
WD		 209 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK;
210 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ; /*1*/
887e2ec9 211 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
511d0c72 212 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS; /*0*/
887e2ec9 213 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
511d0c72 214 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST; /*1*/
887e2ec9 215 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
511d0c72 216 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST; /*1*/
887e2ec9
SR		 217
218 /* An 8-bit/60MHz interface is the only possible alternative
219 when connecting the Device to the PHY */
511d0c72
WD		 220 usb2h0cr = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK;
221 usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ; /*1*/
887e2ec9 222
511d0c72
WD		 223 /* To enable the USB 2.0 Device function through the UTMI interface */
224 usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK;
225 usb2d0cr = usb2d0cr | SDR0_USB2D0CR_USB2DEV_SELECTION; /*1*/
887e2ec9 226
511d0c72
WD		 227 sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK;
228 sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_USB2D_SEL; /*0*/
887e2ec9 229
511d0c72 230 mtsdr(SDR0_PFC1, sdr0_pfc1);
f780b833 231 mtsdr(SDR0_USB2D0CR, usb2d0cr);
511d0c72
WD		 232 mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
233 mtsdr(SDR0_USB2H0CR, usb2h0cr);
887e2ec9
SR		 234
235 /*clear resets*/
236 udelay (1000);
237 mtsdr(SDR0_SRST1, 0x00000000);
238 udelay (1000);
239 mtsdr(SDR0_SRST0, 0x00000000);
240
241 printf("USB: Host(int phy) Device(ext phy)\n");
242
243 } else if (strcmp(act, "dev") == 0) {
244 /*-------------------PATCH-------------------------------*/
245 mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
246
247 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
248 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL; /*0*/
249 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
511d0c72 250 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS; /*0*/
887e2ec9 251 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
511d0c72 252 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST; /*1*/
887e2ec9 253 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
511d0c72 254 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST; /*1*/
887e2ec9
SR		 255 mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
256
257 udelay (1000);
258 mtsdr(SDR0_SRST1, 0x672c6000);
259
260 udelay (1000);
261 mtsdr(SDR0_SRST0, 0x00000080);
262
263 udelay (1000);
264 mtsdr(SDR0_SRST1, 0x60206000);
265
266 *(unsigned int *)(0xe0000350) = 0x00000001;
267
268 udelay (1000);
269 mtsdr(SDR0_SRST1, 0x60306000);
270 /*-------------------PATCH-------------------------------*/
271
272 /* SDR Setting */
511d0c72 273 mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
887e2ec9 274 mfsdr(SDR0_USB2H0CR, usb2h0cr);
f780b833 275 mfsdr(SDR0_USB2D0CR, usb2d0cr);
887e2ec9
SR		 276 mfsdr(SDR0_PFC1, sdr0_pfc1);
277
278 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
279 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL; /*0*/
511d0c72 280 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK;
887e2ec9
SR		 281 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_8BIT_60MHZ; /*0*/
282 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
511d0c72 283 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PUREN; /*1*/
887e2ec9 284 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
511d0c72 285 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_DEV; /*0*/
887e2ec9 286 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
511d0c72 287 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_DEV; /*0*/
887e2ec9
SR		 288
289 usb2h0cr = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK;
511d0c72 290 usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_8BIT_60MHZ; /*0*/
887e2ec9
SR		 291
292 usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK;
511d0c72 293 usb2d0cr = usb2d0cr | SDR0_USB2D0CR_EBC_SELECTION; /*0*/
887e2ec9
SR		 294
295 sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK;
511d0c72 296 sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_EBCHR_SEL; /*1*/
887e2ec9 297
511d0c72
WD		 298 mtsdr(SDR0_USB2H0CR, usb2h0cr);
299 mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
f780b833 300 mtsdr(SDR0_USB2D0CR, usb2d0cr);
887e2ec9
SR		 301 mtsdr(SDR0_PFC1, sdr0_pfc1);
302
303 /*clear resets*/
304 udelay (1000);
305 mtsdr(SDR0_SRST1, 0x00000000);
306 udelay (1000);
307 mtsdr(SDR0_SRST0, 0x00000000);
308
309 printf("USB: Device(int phy)\n");
310 }
854bc8da 311#endif /* CONFIG_440EPX */
887e2ec9 312
8ce16f55
JO		 313 mfsdr(SDR0_SRST1, reg); /* enable security/kasumi engines */
314 reg &= ~(SDR0_SRST1_CRYP0 | SDR0_SRST1_KASU0);
315 mtsdr(SDR0_SRST1, reg);
316
a78bc443
SR		 317 /*
318 * Clear PLB4A0_ACR[WRP]
319 * This fix will make the MAL burst disabling patch for the Linux
320 * EMAC driver obsolete.
321 */
322 reg = mfdcr(plb4_acr) & ~PLB4_ACR_WRP;
323 mtdcr(plb4_acr, reg);
324
887e2ec9
SR		 325 return 0;
326}
327
328int checkboard(void)
329{
330 char *s = getenv("serial#");
e0b9ea8c
SR		 331 u8 rev;
332 u8 val;
887e2ec9 333
854bc8da 334#ifdef CONFIG_440EPX
887e2ec9 335 printf("Board: Sequoia - AMCC PPC440EPx Evaluation Board");
854bc8da
SR		 336#else
337 printf("Board: Rainier - AMCC PPC440GRx Evaluation Board");
338#endif
e0b9ea8c 339
5a5958b7
SR		 340 rev = in_8((void *)(CFG_BCSR_BASE + 0));
341 val = in_8((void *)(CFG_BCSR_BASE + 5)) & CFG_BCSR5_PCI66EN;
e0b9ea8c
SR		 342 printf(", Rev. %X, PCI=%d MHz", rev, val ? 66 : 33);
343
887e2ec9
SR		 344 if (s != NULL) {
345 puts(", serial# ");
346 puts(s);
347 }
348 putc('\n');
349
350 return (0);
351}
352
353#if defined(CFG_DRAM_TEST)
354int testdram(void)
355{
356 unsigned long *mem = (unsigned long *)0;
357 const unsigned long kend = (1024 / sizeof(unsigned long));
358 unsigned long k, n;
359
360 mtmsr(0);
361
362 for (k = 0; k < CFG_MBYTES_SDRAM;
363 ++k, mem += (1024 / sizeof(unsigned long))) {
364 if ((k & 1023) == 0) {
365 printf("%3d MB\r", k / 1024);
366 }
367
368 memset(mem, 0xaaaaaaaa, 1024);
369 for (n = 0; n < kend; ++n) {
370 if (mem[n] != 0xaaaaaaaa) {
371 printf("SDRAM test fails at: %08x\n",
372 (uint) & mem[n]);
373 return 1;
374 }
375 }
376
377 memset(mem, 0x55555555, 1024);
378 for (n = 0; n < kend; ++n) {
379 if (mem[n] != 0x55555555) {
380 printf("SDRAM test fails at: %08x\n",
381 (uint) & mem[n]);
382 return 1;
383 }
384 }
385 }
386 printf("SDRAM test passes\n");
387 return 0;
388}
389#endif
390
1f84021a
MF		 391#if defined(CONFIG_PCI) && defined(CONFIG_PCI_PNP)
392/*
393 * Assign interrupts to PCI devices.
394 */
395void sequoia_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
396{
397 pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, VECNUM_EIR2);
398}
399#endif
400
887e2ec9
SR		 401/*************************************************************************
402 * pci_pre_init
403 *
404 * This routine is called just prior to registering the hose and gives
405 * the board the opportunity to check things. Returning a value of zero
406 * indicates that things are bad & PCI initialization should be aborted.
407 *
408 * Different boards may wish to customize the pci controller structure
409 * (add regions, override default access routines, etc) or perform
410 * certain pre-initialization actions.
411 *
412 ************************************************************************/
466fff1a 413#if defined(CONFIG_PCI)
887e2ec9
SR		 414int pci_pre_init(struct pci_controller *hose)
415{
416 unsigned long addr;
887e2ec9
SR		 417
418 /*-------------------------------------------------------------------------+
419 | Set priority for all PLB3 devices to 0.
420 | Set PLB3 arbiter to fair mode.
421 +-------------------------------------------------------------------------*/
422 mfsdr(sdr_amp1, addr);
423 mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00);
424 addr = mfdcr(plb3_acr);
425 mtdcr(plb3_acr, addr | 0x80000000);
426
427 /*-------------------------------------------------------------------------+
428 | Set priority for all PLB4 devices to 0.
429 +-------------------------------------------------------------------------*/
430 mfsdr(sdr_amp0, addr);
431 mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00);
432 addr = mfdcr(plb4_acr) | 0xa0000000; /* Was 0x8---- */
433 mtdcr(plb4_acr, addr);
434
435 /*-------------------------------------------------------------------------+
436 | Set Nebula PLB4 arbiter to fair mode.
437 +-------------------------------------------------------------------------*/
438 /* Segment0 */
439 addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair;
440 addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled;
441 addr = (addr & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep;
442 addr = (addr & ~plb0_acr_wrp_mask) | plb0_acr_wrp_2deep;
443 mtdcr(plb0_acr, addr);
444
445 /* Segment1 */
446 addr = (mfdcr(plb1_acr) & ~plb1_acr_ppm_mask) | plb1_acr_ppm_fair;
447 addr = (addr & ~plb1_acr_hbu_mask) | plb1_acr_hbu_enabled;
448 addr = (addr & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep;
449 addr = (addr & ~plb1_acr_wrp_mask) | plb1_acr_wrp_2deep;
450 mtdcr(plb1_acr, addr);
451
1f84021a
MF		 452#ifdef CONFIG_PCI_PNP
453 hose->fixup_irq = sequoia_pci_fixup_irq;
454#endif
887e2ec9
SR		 455 return 1;
456}
466fff1a 457#endif /* defined(CONFIG_PCI) */
887e2ec9
SR		 458
459/*************************************************************************
460 * pci_target_init
461 *
462 * The bootstrap configuration provides default settings for the pci
463 * inbound map (PIM). But the bootstrap config choices are limited and
464 * may not be sufficient for a given board.
465 *
466 ************************************************************************/
467#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
468void pci_target_init(struct pci_controller *hose)
469{
470 /*--------------------------------------------------------------------------+
471 * Set up Direct MMIO registers
472 *--------------------------------------------------------------------------*/
473 /*--------------------------------------------------------------------------+
474 | PowerPC440EPX PCI Master configuration.
475 | Map one 1Gig range of PLB/processor addresses to PCI memory space.
476 | PLB address 0xA0000000-0xDFFFFFFF ==> PCI address 0xA0000000-0xDFFFFFFF
477 | Use byte reversed out routines to handle endianess.
478 | Make this region non-prefetchable.
479 +--------------------------------------------------------------------------*/
480 out32r(PCIX0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */
481 out32r(PCIX0_PMM0LA, CFG_PCI_MEMBASE); /* PMM0 Local Address */
482 out32r(PCIX0_PMM0PCILA, CFG_PCI_MEMBASE); /* PMM0 PCI Low Address */
483 out32r(PCIX0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */
484 out32r(PCIX0_PMM0MA, 0xE0000001); /* 512M + No prefetching, and enable region */
485
486 out32r(PCIX0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */
487 out32r(PCIX0_PMM1LA, CFG_PCI_MEMBASE2); /* PMM0 Local Address */
488 out32r(PCIX0_PMM1PCILA, CFG_PCI_MEMBASE2); /* PMM0 PCI Low Address */
489 out32r(PCIX0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */
490 out32r(PCIX0_PMM1MA, 0xE0000001); /* 512M + No prefetching, and enable region */
491
492 out32r(PCIX0_PTM1MS, 0x00000001); /* Memory Size/Attribute */
493 out32r(PCIX0_PTM1LA, 0); /* Local Addr. Reg */
494 out32r(PCIX0_PTM2MS, 0); /* Memory Size/Attribute */
495 out32r(PCIX0_PTM2LA, 0); /* Local Addr. Reg */
496
497 /*--------------------------------------------------------------------------+
498 * Set up Configuration registers
499 *--------------------------------------------------------------------------*/
500
501 /* Program the board's subsystem id/vendor id */
502 pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID,
503 CFG_PCI_SUBSYS_VENDORID);
504 pci_write_config_word(0, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_ID);
505
506 /* Configure command register as bus master */
507 pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER);
508
509 /* 240nS PCI clock */
510 pci_write_config_word(0, PCI_LATENCY_TIMER, 1);
511
512 /* No error reporting */
513 pci_write_config_word(0, PCI_ERREN, 0);
514
515 pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101);
516
517}
518#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
519
520/*************************************************************************
521 * pci_master_init
522 *
523 ************************************************************************/
524#if defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT)
525void pci_master_init(struct pci_controller *hose)
526{
527 unsigned short temp_short;
528
529 /*--------------------------------------------------------------------------+
530 | Write the PowerPC440 EP PCI Configuration regs.
531 | Enable PowerPC440 EP to be a master on the PCI bus (PMM).
532 | Enable PowerPC440 EP to act as a PCI memory target (PTM).
533 +--------------------------------------------------------------------------*/
534 pci_read_config_word(0, PCI_COMMAND, &temp_short);
535 pci_write_config_word(0, PCI_COMMAND,
536 temp_short | PCI_COMMAND_MASTER |
537 PCI_COMMAND_MEMORY);
538}
539#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) */
540
541/*************************************************************************
542 * is_pci_host
543 *
544 * This routine is called to determine if a pci scan should be
545 * performed. With various hardware environments (especially cPCI and
546 * PPMC) it's insufficient to depend on the state of the arbiter enable
547 * bit in the strap register, or generic host/adapter assumptions.
548 *
549 * Rather than hard-code a bad assumption in the general 440 code, the
550 * 440 pci code requires the board to decide at runtime.
551 *
552 * Return 0 for adapter mode, non-zero for host (monarch) mode.
553 *
554 *
555 ************************************************************************/
556#if defined(CONFIG_PCI)
557int is_pci_host(struct pci_controller *hose)
558{
559 /* Cactus is always configured as host. */
560 return (1);
561}
562#endif /* defined(CONFIG_PCI) */
a11e0696
IL		 563#if defined(CONFIG_POST)
564/*
565 * Returns 1 if keys pressed to start the power-on long-running tests
566 * Called from board_init_f().
567 */
568int post_hotkeys_pressed(void)
569{
570 return 0; /* No hotkeys supported */
571}
572#endif /* CONFIG_POST */
13628884
SR		 573
574#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
575void ft_board_setup(void *blob, bd_t *bd)
576{
577 u32 val[4];
578 int rc;
579
580 ft_cpu_setup(blob, bd);
581
582 /* Fixup NOR mapping */
583 val[0] = 0; /* chip select number */
584 val[1] = 0; /* always 0 */
585 val[2] = gd->bd->bi_flashstart;
586 val[3] = gd->bd->bi_flashsize;
587 rc = fdt_find_and_setprop(blob, "/plb/opb/ebc", "ranges",
588 val, sizeof(val), 1);
589 if (rc)
590 printf("Unable to update property NOR mapping, err=%s\n",
591 fdt_strerror(rc));
592}
593#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
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