[people/ms/u-boot.git] / board / freescale / ls1043ardb / ls1043ardb.c

/*
 * Copyright 2015 Freescale Semiconductor, Inc.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <i2c.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/fsl_serdes.h>
#include <asm/arch/soc.h>
#include <hwconfig.h>
#include <ahci.h>
#include <mmc.h>
#include <scsi.h>
#include <fm_eth.h>
#include <fsl_csu.h>
#include <fsl_esdhc.h>
#include <fsl_ifc.h>
#include <environment.h>
#include <fsl_sec.h>
#include "cpld.h"
#ifdef CONFIG_U_QE
#include <fsl_qe.h>
#endif


DECLARE_GLOBAL_DATA_PTR;

int checkboard(void)
{
	static const char *freq[3] = {"100.00MHZ", "156.25MHZ"};
#ifndef CONFIG_SD_BOOT
	u8 cfg_rcw_src1, cfg_rcw_src2;
	u32 cfg_rcw_src;
#endif
	u32 sd1refclk_sel;

	printf("Board: LS1043ARDB, boot from ");

#ifdef CONFIG_SD_BOOT
	puts("SD\n");
#else
	cfg_rcw_src1 = CPLD_READ(cfg_rcw_src1);
	cfg_rcw_src2 = CPLD_READ(cfg_rcw_src2);
	cpld_rev_bit(&cfg_rcw_src1);
	cfg_rcw_src = cfg_rcw_src1;
	cfg_rcw_src = (cfg_rcw_src << 1) | cfg_rcw_src2;

	if (cfg_rcw_src == 0x25)
		printf("vBank %d\n", CPLD_READ(vbank));
	else if (cfg_rcw_src == 0x106)
		puts("NAND\n");
	else
		printf("Invalid setting of SW4\n");
#endif

	printf("CPLD:  V%x.%x\nPCBA:  V%x.0\n", CPLD_READ(cpld_ver),
	       CPLD_READ(cpld_ver_sub), CPLD_READ(pcba_ver));

	puts("SERDES Reference Clocks:\n");
	sd1refclk_sel = CPLD_READ(sd1refclk_sel);
	printf("SD1_CLK1 = %s, SD1_CLK2 = %s\n", freq[sd1refclk_sel], freq[0]);

	return 0;
}

int dram_init(void)
{
	gd->ram_size = initdram(0);

	return 0;
}

int board_early_init_f(void)
{
	fsl_lsch2_early_init_f();

	return 0;
}

int board_init(void)
{
	struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;

	/*
	 * Set CCI-400 control override register to enable barrier
	 * transaction
	 */
	out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);

#ifdef CONFIG_FSL_IFC
	init_final_memctl_regs();
#endif

#ifdef CONFIG_ENV_IS_NOWHERE
	gd->env_addr = (ulong)&default_environment[0];
#endif

#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
	enable_layerscape_ns_access();
#endif

#ifdef CONFIG_U_QE
	u_qe_init();
#endif

	return 0;
}

int config_board_mux(void)
{
	struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
	u32 usb_pwrfault;

#ifdef CONFIG_HAS_FSL_XHCI_USB
	out_be32(&scfg->rcwpmuxcr0, 0x3333);
	out_be32(&scfg->usbdrvvbus_selcr, SCFG_USBDRVVBUS_SELCR_USB1);
	usb_pwrfault = (SCFG_USBPWRFAULT_DEDICATED <<
			SCFG_USBPWRFAULT_USB3_SHIFT) |
			(SCFG_USBPWRFAULT_DEDICATED <<
			SCFG_USBPWRFAULT_USB2_SHIFT) |
			(SCFG_USBPWRFAULT_SHARED <<
			 SCFG_USBPWRFAULT_USB1_SHIFT);
	out_be32(&scfg->usbpwrfault_selcr, usb_pwrfault);
#endif

	return 0;
}

#if defined(CONFIG_MISC_INIT_R)
int misc_init_r(void)
{
	config_board_mux();
#ifdef CONFIG_SECURE_BOOT
	/* In case of Secure Boot, the IBR configures the SMMU
	 * to allow only Secure transactions.
	 * SMMU must be reset in bypass mode.
	 * Set the ClientPD bit and Clear the USFCFG Bit
	 */
	u32 val;
	val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
	out_le32(SMMU_SCR0, val);
	val = (in_le32(SMMU_NSCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
	out_le32(SMMU_NSCR0, val);
#endif
#ifdef CONFIG_FSL_CAAM
	return sec_init();
#endif
	return 0;
}
#endif

int ft_board_setup(void *blob, bd_t *bd)
{
	u64 base[CONFIG_NR_DRAM_BANKS];
	u64 size[CONFIG_NR_DRAM_BANKS];

	/* fixup DT for the two DDR banks */
	base[0] = gd->bd->bi_dram[0].start;
	size[0] = gd->bd->bi_dram[0].size;
	base[1] = gd->bd->bi_dram[1].start;
	size[1] = gd->bd->bi_dram[1].size;

	fdt_fixup_memory_banks(blob, base, size, 2);
	ft_cpu_setup(blob, bd);

#ifdef CONFIG_SYS_DPAA_FMAN
	fdt_fixup_fman_ethernet(blob);
#endif
	return 0;
}

u8 flash_read8(void *addr)
{
	return __raw_readb(addr + 1);
}

void flash_write16(u16 val, void *addr)
{
	u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00));

	__raw_writew(shftval, addr);
}

u16 flash_read16(void *addr)
{
	u16 val = __raw_readw(addr);

	return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);
}
Commit	Line	Data
f3a8e2b7 MH	1	/*
	2	* Copyright 2015 Freescale Semiconductor, Inc.
	3	*
	4	* SPDX-License-Identifier: GPL-2.0+
	5	*/
	6
	7	#include <common.h>
	8	#include <i2c.h>
	9	#include <asm/io.h>
	10	#include <asm/arch/clock.h>
	11	#include <asm/arch/fsl_serdes.h>
	12	#include <asm/arch/soc.h>
	13	#include <hwconfig.h>
	14	#include <ahci.h>
8ef0d5c4	15	#include <mmc.h>
f3a8e2b7	16	#include <scsi.h>
e8297341	17	#include <fm_eth.h>
f3a8e2b7 MH	18	#include <fsl_csu.h>
	19	#include <fsl_esdhc.h>
	20	#include <fsl_ifc.h>
9711f528 AB	21	#include <environment.h>
9711f528 AB	22	#include <fsl_sec.h>
f3a8e2b7	23	#include "cpld.h"
d3e6d30c ZQ	24	#ifdef CONFIG_U_QE
	25	#include <fsl_qe.h>
	26	#endif
	27
f3a8e2b7 MH	28
	29	DECLARE_GLOBAL_DATA_PTR;
	30
	31	int checkboard(void)
	32	{
	33	static const char *freq[3] = {"100.00MHZ", "156.25MHZ"};
c7ca8b07	34	#ifndef CONFIG_SD_BOOT
f3a8e2b7 MH	35	u8 cfg_rcw_src1, cfg_rcw_src2;
f3a8e2b7 MH	36	u32 cfg_rcw_src;
c7ca8b07	37	#endif
f3a8e2b7 MH	38	u32 sd1refclk_sel;
	39
	40	printf("Board: LS1043ARDB, boot from ");
	41
c7ca8b07 GQ	42	#ifdef CONFIG_SD_BOOT
	43	puts("SD\n");
	44	#else
f3a8e2b7 MH	45	cfg_rcw_src1 = CPLD_READ(cfg_rcw_src1);
	46	cfg_rcw_src2 = CPLD_READ(cfg_rcw_src2);
	47	cpld_rev_bit(&cfg_rcw_src1);
	48	cfg_rcw_src = cfg_rcw_src1;
	49	cfg_rcw_src = (cfg_rcw_src << 1) \| cfg_rcw_src2;
	50
	51	if (cfg_rcw_src == 0x25)
	52	printf("vBank %d\n", CPLD_READ(vbank));
	53	else if (cfg_rcw_src == 0x106)
	54	puts("NAND\n");
	55	else
	56	printf("Invalid setting of SW4\n");
c7ca8b07	57	#endif
f3a8e2b7 MH	58
	59	printf("CPLD: V%x.%x\nPCBA: V%x.0\n", CPLD_READ(cpld_ver),
	60	CPLD_READ(cpld_ver_sub), CPLD_READ(pcba_ver));
	61
	62	puts("SERDES Reference Clocks:\n");
	63	sd1refclk_sel = CPLD_READ(sd1refclk_sel);
	64	printf("SD1_CLK1 = %s, SD1_CLK2 = %s\n", freq[sd1refclk_sel], freq[0]);
	65
	66	return 0;
	67	}
	68
	69	int dram_init(void)
	70	{
	71	gd->ram_size = initdram(0);
	72
	73	return 0;
	74	}
	75
	76	int board_early_init_f(void)
	77	{
	78	fsl_lsch2_early_init_f();
70231009	79
f3a8e2b7 MH	80	return 0;
	81	}
	82
	83	int board_init(void)
	84	{
	85	struct ccsr_cci400 cci = (struct ccsr_cci400 )CONFIG_SYS_CCI400_ADDR;
	86
	87	/*
	88	* Set CCI-400 control override register to enable barrier
	89	* transaction
	90	*/
	91	out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
	92
	93	#ifdef CONFIG_FSL_IFC
	94	init_final_memctl_regs();
	95	#endif
	96
	97	#ifdef CONFIG_ENV_IS_NOWHERE
	98	gd->env_addr = (ulong)&default_environment[0];
	99	#endif
	100
	101	#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
	102	enable_layerscape_ns_access();
	103	#endif
	104
d3e6d30c ZQ	105	#ifdef CONFIG_U_QE
	106	u_qe_init();
	107	#endif
	108
f3a8e2b7 MH	109	return 0;
	110	}
	111
	112	int config_board_mux(void)
	113	{
110171dc ZQ	114	struct ccsr_scfg scfg = (struct ccsr_scfg )CONFIG_SYS_FSL_SCFG_ADDR;
	115	u32 usb_pwrfault;
	116
	117	#ifdef CONFIG_HAS_FSL_XHCI_USB
	118	out_be32(&scfg->rcwpmuxcr0, 0x3333);
	119	out_be32(&scfg->usbdrvvbus_selcr, SCFG_USBDRVVBUS_SELCR_USB1);
	120	usb_pwrfault = (SCFG_USBPWRFAULT_DEDICATED <<
	121	SCFG_USBPWRFAULT_USB3_SHIFT) \|
	122	(SCFG_USBPWRFAULT_DEDICATED <<
	123	SCFG_USBPWRFAULT_USB2_SHIFT) \|
	124	(SCFG_USBPWRFAULT_SHARED <<
	125	SCFG_USBPWRFAULT_USB1_SHIFT);
	126	out_be32(&scfg->usbpwrfault_selcr, usb_pwrfault);
	127	#endif
	128
f3a8e2b7 MH	129	return 0;
	130	}
	131
	132	#if defined(CONFIG_MISC_INIT_R)
	133	int misc_init_r(void)
	134	{
	135	config_board_mux();
9711f528 AB	136	#ifdef CONFIG_SECURE_BOOT
	137	/* In case of Secure Boot, the IBR configures the SMMU
	138	* to allow only Secure transactions.
	139	* SMMU must be reset in bypass mode.
	140	* Set the ClientPD bit and Clear the USFCFG Bit
	141	*/
	142	u32 val;
	143	val = (in_le32(SMMU_SCR0) \| SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
	144	out_le32(SMMU_SCR0, val);
	145	val = (in_le32(SMMU_NSCR0) \| SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
	146	out_le32(SMMU_NSCR0, val);
	147	#endif
	148	#ifdef CONFIG_FSL_CAAM
	149	return sec_init();
	150	#endif
f3a8e2b7 MH	151	return 0;
	152	}
	153	#endif
	154
	155	int ft_board_setup(void blob, bd_t bd)
	156	{
e994dddb SX	157	u64 base[CONFIG_NR_DRAM_BANKS];
	158	u64 size[CONFIG_NR_DRAM_BANKS];
	159
	160	/* fixup DT for the two DDR banks */
	161	base[0] = gd->bd->bi_dram[0].start;
	162	size[0] = gd->bd->bi_dram[0].size;
	163	base[1] = gd->bd->bi_dram[1].start;
	164	size[1] = gd->bd->bi_dram[1].size;
	165
	166	fdt_fixup_memory_banks(blob, base, size, 2);
f3a8e2b7 MH	167	ft_cpu_setup(blob, bd);
f3a8e2b7 MH	168
e8297341 SX	169	#ifdef CONFIG_SYS_DPAA_FMAN
	170	fdt_fixup_fman_ethernet(blob);
	171	#endif
f3a8e2b7 MH	172	return 0;
	173	}
	174
	175	u8 flash_read8(void *addr)
	176	{
	177	return __raw_readb(addr + 1);
	178	}
	179
	180	void flash_write16(u16 val, void *addr)
	181	{
	182	u16 shftval = (((val >> 8) & 0xff) \| ((val << 8) & 0xff00));
	183
	184	__raw_writew(shftval, addr);
	185	}
	186
	187	u16 flash_read16(void *addr)
	188	{
	189	u16 val = __raw_readw(addr);
	190
	191	return (((val) >> 8) & 0x00ff) \| (((val) << 8) & 0xff00);
	192	}