[people/ms/u-boot.git] / board / ti / ks2_evm / board_k2g.c

/*
 * K2G EVM : Board initialization
 *
 * (C) Copyright 2015
 *     Texas Instruments Incorporated, <www.ti.com>
 *
 * SPDX-License-Identifier:     GPL-2.0+
 */
#include <common.h>
#include <asm/arch/clock.h>
#include <asm/ti-common/keystone_net.h>
#include <asm/arch/psc_defs.h>
#include <asm/arch/mmc_host_def.h>
#include <fdtdec.h>
#include <i2c.h>
#include <remoteproc.h>
#include "mux-k2g.h"
#include "../common/board_detect.h"

#define K2G_GP_AUDIO_CODEC_ADDRESS	0x1B

const unsigned int sysclk_array[MAX_SYSCLK] = {
	19200000,
	24000000,
	25000000,
	26000000,
};

unsigned int get_external_clk(u32 clk)
{
	unsigned int clk_freq;
	u8 sysclk_index = get_sysclk_index();

	switch (clk) {
	case sys_clk:
		clk_freq = sysclk_array[sysclk_index];
		break;
	case pa_clk:
		clk_freq = sysclk_array[sysclk_index];
		break;
	case tetris_clk:
		clk_freq = sysclk_array[sysclk_index];
		break;
	case ddr3a_clk:
		clk_freq = sysclk_array[sysclk_index];
		break;
	case uart_clk:
		clk_freq = sysclk_array[sysclk_index];
		break;
	default:
		clk_freq = 0;
		break;
	}

	return clk_freq;
}

static int arm_speeds[DEVSPEED_NUMSPDS] = {
	SPD400,
	SPD600,
	SPD800,
	SPD900,
	SPD1000,
	SPD900,
	SPD800,
	SPD600,
	SPD400,
	SPD200,
};

static int dev_speeds[DEVSPEED_NUMSPDS] = {
	SPD600,
	SPD800,
	SPD900,
	SPD1000,
	SPD900,
	SPD800,
	SPD600,
	SPD400,
};

static struct pll_init_data main_pll_config[MAX_SYSCLK][NUM_SPDS] = {
	[SYSCLK_19MHz] = {
		[SPD400]	= {MAIN_PLL, 125, 3, 2},
		[SPD600]	= {MAIN_PLL, 125, 2, 2},
		[SPD800]	= {MAIN_PLL, 250, 3, 2},
		[SPD900]	= {MAIN_PLL, 187, 2, 2},
		[SPD1000]	= {MAIN_PLL, 104, 1, 2},
	},
	[SYSCLK_24MHz] = {
		[SPD400]	= {MAIN_PLL, 100, 3, 2},
		[SPD600]	= {MAIN_PLL, 300, 6, 2},
		[SPD800]	= {MAIN_PLL, 200, 3, 2},
		[SPD900]	= {MAIN_PLL, 75, 1, 2},
		[SPD1000]	= {MAIN_PLL, 250, 3, 2},
	},
	[SYSCLK_25MHz] = {
		[SPD400]	= {MAIN_PLL, 32, 1, 2},
		[SPD600]	= {MAIN_PLL, 48, 1, 2},
		[SPD800]	= {MAIN_PLL, 64, 1, 2},
		[SPD900]	= {MAIN_PLL, 72, 1, 2},
		[SPD1000]	= {MAIN_PLL, 80, 1, 2},
	},
	[SYSCLK_26MHz] = {
		[SPD400]	= {MAIN_PLL, 400, 13, 2},
		[SPD600]	= {MAIN_PLL, 230, 5, 2},
		[SPD800]	= {MAIN_PLL, 123, 2, 2},
		[SPD900]	= {MAIN_PLL, 69, 1, 2},
		[SPD1000]	= {MAIN_PLL, 384, 5, 2},
	},
};

static struct pll_init_data tetris_pll_config[MAX_SYSCLK][NUM_SPDS] = {
	[SYSCLK_19MHz] = {
		[SPD200]	= {TETRIS_PLL, 625, 6, 10},
		[SPD400]	= {TETRIS_PLL, 125, 1, 6},
		[SPD600]	= {TETRIS_PLL, 125, 1, 4},
		[SPD800]	= {TETRIS_PLL, 333, 2, 4},
		[SPD900]	= {TETRIS_PLL, 187, 2, 2},
		[SPD1000]	= {TETRIS_PLL, 104, 1, 2},
	},
	[SYSCLK_24MHz] = {
		[SPD200]	= {TETRIS_PLL, 250, 3, 10},
		[SPD400]	= {TETRIS_PLL, 100, 1, 6},
		[SPD600]	= {TETRIS_PLL, 100, 1, 4},
		[SPD800]	= {TETRIS_PLL, 400, 3, 4},
		[SPD900]	= {TETRIS_PLL, 75, 1, 2},
		[SPD1000]	= {TETRIS_PLL, 250, 3, 2},
	},
	[SYSCLK_25MHz] = {
		[SPD200]	= {TETRIS_PLL, 80, 1, 10},
		[SPD400]	= {TETRIS_PLL, 96, 1, 6},
		[SPD600]	= {TETRIS_PLL, 96, 1, 4},
		[SPD800]	= {TETRIS_PLL, 128, 1, 4},
		[SPD900]	= {TETRIS_PLL, 72, 1, 2},
		[SPD1000]	= {TETRIS_PLL, 80, 1, 2},
	},
	[SYSCLK_26MHz] = {
		[SPD200]	= {TETRIS_PLL, 307, 4, 10},
		[SPD400]	= {TETRIS_PLL, 369, 4, 6},
		[SPD600]	= {TETRIS_PLL, 369, 4, 4},
		[SPD800]	= {TETRIS_PLL, 123, 1, 4},
		[SPD900]	= {TETRIS_PLL, 69, 1, 2},
		[SPD1000]	= {TETRIS_PLL, 384, 5, 2},
	},
};

static struct pll_init_data uart_pll_config[MAX_SYSCLK] = {
	[SYSCLK_19MHz] = {UART_PLL, 160, 1, 8},
	[SYSCLK_24MHz] = {UART_PLL, 128, 1, 8},
	[SYSCLK_25MHz] = {UART_PLL, 768, 5, 10},
	[SYSCLK_26MHz] = {UART_PLL, 384, 13, 2},
};

static struct pll_init_data nss_pll_config[MAX_SYSCLK] = {
	[SYSCLK_19MHz] = {NSS_PLL, 625, 6, 2},
	[SYSCLK_24MHz] = {NSS_PLL, 250, 3, 2},
	[SYSCLK_25MHz] = {NSS_PLL, 80, 1, 2},
	[SYSCLK_26MHz] = {NSS_PLL, 1000, 13, 2},
};

static struct pll_init_data ddr3_pll_config[MAX_SYSCLK] = {
	[SYSCLK_19MHz] = {DDR3A_PLL, 167, 1, 16},
	[SYSCLK_24MHz] = {DDR3A_PLL, 133, 1, 16},
	[SYSCLK_25MHz] = {DDR3A_PLL, 128, 1, 16},
	[SYSCLK_26MHz] = {DDR3A_PLL, 123, 1, 16},
};

struct pll_init_data *get_pll_init_data(int pll)
{
	int speed;
	struct pll_init_data *data = NULL;
	u8 sysclk_index = get_sysclk_index();

	switch (pll) {
	case MAIN_PLL:
		speed = get_max_dev_speed(dev_speeds);
		data = &main_pll_config[sysclk_index][speed];
		break;
	case TETRIS_PLL:
		speed = get_max_arm_speed(arm_speeds);
		data = &tetris_pll_config[sysclk_index][speed];
		break;
	case NSS_PLL:
		data = &nss_pll_config[sysclk_index];
		break;
	case UART_PLL:
		data = &uart_pll_config[sysclk_index];
		break;
	case DDR3_PLL:
		data = &ddr3_pll_config[sysclk_index];
		break;
	default:
		data = NULL;
	}

	return data;
}

s16 divn_val[16] = {
	-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1
};

#if defined(CONFIG_MMC)
int board_mmc_init(bd_t *bis)
{
	if (psc_enable_module(KS2_LPSC_MMC)) {
		printf("%s module enabled failed\n", __func__);
		return -1;
	}

	if (board_is_k2g_gp())
		omap_mmc_init(0, 0, 0, -1, -1);

	omap_mmc_init(1, 0, 0, -1, -1);
	return 0;
}
#endif

#if defined(CONFIG_FIT_EMBED)
int board_fit_config_name_match(const char *name)
{
	bool eeprom_read = board_ti_was_eeprom_read();

	if (!strcmp(name, "keystone-k2g-generic") && !eeprom_read)
		return 0;
	else if (!strcmp(name, "keystone-k2g-evm") && board_ti_is("66AK2GGP"))
		return 0;
	else if (!strcmp(name, "keystone-k2g-ice") && board_ti_is("66AK2GIC"))
		return 0;
	else
		return -1;
}
#endif

#if defined(CONFIG_DTB_RESELECT)
static int k2g_alt_board_detect(void)
{
	int rc;

	rc = i2c_set_bus_num(1);
	if (rc)
		return rc;

	rc = i2c_probe(K2G_GP_AUDIO_CODEC_ADDRESS);
	if (rc)
		return rc;

	ti_i2c_eeprom_am_set("66AK2GGP", "1.0X");

	return 0;
}

static void k2g_reset_mux_config(void)
{
	/* Unlock the reset mux register */
	clrbits_le32(KS2_RSTMUX8, RSTMUX_LOCK8_MASK);

	/* Configure BOOTCFG_RSTMUX8 for WDT event to cause a device reset */
	clrsetbits_le32(KS2_RSTMUX8, RSTMUX_OMODE8_MASK,
			RSTMUX_OMODE8_DEV_RESET << RSTMUX_OMODE8_SHIFT);

	/* lock the reset mux register to prevent any spurious writes. */
	setbits_le32(KS2_RSTMUX8, RSTMUX_LOCK8_MASK);
}

int embedded_dtb_select(void)
{
	int rc;
	rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
			CONFIG_EEPROM_CHIP_ADDRESS);
	if (rc) {
		rc = k2g_alt_board_detect();
		if (rc) {
			printf("Unable to do board detection\n");
			return -1;
		}
	}

	fdtdec_setup();

	k2g_mux_config();

	k2g_reset_mux_config();

	if (board_is_k2g_gp()) {
		/* deassert FLASH_HOLD */
		clrbits_le32(K2G_GPIO1_BANK2_BASE + K2G_GPIO_DIR_OFFSET,
			     BIT(9));
		setbits_le32(K2G_GPIO1_BANK2_BASE + K2G_GPIO_SETDATA_OFFSET,
			     BIT(9));
	}

	return 0;
}
#endif

#ifdef CONFIG_BOARD_LATE_INIT
int board_late_init(void)
{
#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_TI_I2C_BOARD_DETECT)
	int rc;

	rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
			CONFIG_EEPROM_CHIP_ADDRESS);
	if (rc)
		printf("ti_i2c_eeprom_init failed %d\n", rc);

	board_ti_set_ethaddr(1);
#endif

#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
	if (board_is_k2g_gp())
		env_set("board_name", "66AK2GGP\0");
	else if (board_is_k2g_ice())
		env_set("board_name", "66AK2GIC\0");
#endif
	return 0;
}
#endif

#ifdef CONFIG_BOARD_EARLY_INIT_F
int board_early_init_f(void)
{
	init_plls();

	k2g_mux_config();

	return 0;
}
#endif

#ifdef CONFIG_SPL_BUILD
void spl_init_keystone_plls(void)
{
	init_plls();
}
#endif

#ifdef CONFIG_DRIVER_TI_KEYSTONE_NET
struct eth_priv_t eth_priv_cfg[] = {
	{
		.int_name	= "K2G_EMAC",
		.rx_flow	= 0,
		.phy_addr	= 0,
		.slave_port	= 1,
		.sgmii_link_type = SGMII_LINK_MAC_PHY,
		.phy_if          = PHY_INTERFACE_MODE_RGMII,
	},
};

int get_num_eth_ports(void)
{
	return sizeof(eth_priv_cfg) / sizeof(struct eth_priv_t);
}
#endif

#ifdef CONFIG_TI_SECURE_DEVICE
void board_pmmc_image_process(ulong pmmc_image, size_t pmmc_size)
{
	int id = getenv_ulong("dev_pmmc", 10, 0);
	int ret;

	if (!rproc_is_initialized())
		rproc_init();

	ret = rproc_load(id, pmmc_image, pmmc_size);
	printf("Load Remote Processor %d with data@addr=0x%08lx %u bytes:%s\n",
	       id, pmmc_image, pmmc_size, ret ? " Failed!" : " Success!");

	if (!ret)
		rproc_start(id);
}

U_BOOT_FIT_LOADABLE_HANDLER(IH_TYPE_PMMC, board_pmmc_image_process);
#endif
Commit	Line	Data
bda920c6 VA	1	/*
	2	* K2G EVM : Board initialization
	3	*
	4	* (C) Copyright 2015
	5	* Texas Instruments Incorporated, <www.ti.com>
	6	*
	7	* SPDX-License-Identifier: GPL-2.0+
	8	*/
	9	#include <common.h>
	10	#include <asm/arch/clock.h>
91266ccb	11	#include <asm/ti-common/keystone_net.h>
3b68939f RQ	12	#include <asm/arch/psc_defs.h>
3b68939f RQ	13	#include <asm/arch/mmc_host_def.h>
5f48da9a CJF	14	#include <fdtdec.h>
5f48da9a CJF	15	#include <i2c.h>
58fac52d	16	#include <remoteproc.h>
dd78b8cf	17	#include "mux-k2g.h"
752a8311	18	#include "../common/board_detect.h"
bda920c6	19
5f48da9a CJF	20	#define K2G_GP_AUDIO_CODEC_ADDRESS 0x1B
5f48da9a CJF	21
c5f177de LV	22	const unsigned int sysclk_array[MAX_SYSCLK] = {
	23	19200000,
	24	24000000,
	25	25000000,
	26	26000000,
	27	};
	28
ee3c6532 LV	29	unsigned int get_external_clk(u32 clk)
	30	{
	31	unsigned int clk_freq;
	32	u8 sysclk_index = get_sysclk_index();
	33
	34	switch (clk) {
	35	case sys_clk:
	36	clk_freq = sysclk_array[sysclk_index];
	37	break;
	38	case pa_clk:
	39	clk_freq = sysclk_array[sysclk_index];
	40	break;
	41	case tetris_clk:
	42	clk_freq = sysclk_array[sysclk_index];
	43	break;
	44	case ddr3a_clk:
	45	clk_freq = sysclk_array[sysclk_index];
	46	break;
	47	case uart_clk:
	48	clk_freq = sysclk_array[sysclk_index];
	49	break;
	50	default:
	51	clk_freq = 0;
	52	break;
	53	}
	54
	55	return clk_freq;
	56	}
e6d71e1c	57
ef76ebb1 LV	58	static int arm_speeds[DEVSPEED_NUMSPDS] = {
	59	SPD400,
	60	SPD600,
	61	SPD800,
	62	SPD900,
	63	SPD1000,
	64	SPD900,
	65	SPD800,
	66	SPD600,
	67	SPD400,
	68	SPD200,
	69	};
	70
	71	static int dev_speeds[DEVSPEED_NUMSPDS] = {
	72	SPD600,
	73	SPD800,
	74	SPD900,
	75	SPD1000,
	76	SPD900,
	77	SPD800,
	78	SPD600,
	79	SPD400,
	80	};
	81
c5f177de LV	82	static struct pll_init_data main_pll_config[MAX_SYSCLK][NUM_SPDS] = {
	83	[SYSCLK_19MHz] = {
	84	[SPD400] = {MAIN_PLL, 125, 3, 2},
	85	[SPD600] = {MAIN_PLL, 125, 2, 2},
	86	[SPD800] = {MAIN_PLL, 250, 3, 2},
9cb5eaf2 LV	87	[SPD900] = {MAIN_PLL, 187, 2, 2},
9cb5eaf2 LV	88	[SPD1000] = {MAIN_PLL, 104, 1, 2},
c5f177de LV	89	},
	90	[SYSCLK_24MHz] = {
	91	[SPD400] = {MAIN_PLL, 100, 3, 2},
	92	[SPD600] = {MAIN_PLL, 300, 6, 2},
	93	[SPD800] = {MAIN_PLL, 200, 3, 2},
9cb5eaf2 LV	94	[SPD900] = {MAIN_PLL, 75, 1, 2},
9cb5eaf2 LV	95	[SPD1000] = {MAIN_PLL, 250, 3, 2},
c5f177de LV	96	},
	97	[SYSCLK_25MHz] = {
	98	[SPD400] = {MAIN_PLL, 32, 1, 2},
	99	[SPD600] = {MAIN_PLL, 48, 1, 2},
	100	[SPD800] = {MAIN_PLL, 64, 1, 2},
9cb5eaf2 LV	101	[SPD900] = {MAIN_PLL, 72, 1, 2},
9cb5eaf2 LV	102	[SPD1000] = {MAIN_PLL, 80, 1, 2},
c5f177de LV	103	},
	104	[SYSCLK_26MHz] = {
	105	[SPD400] = {MAIN_PLL, 400, 13, 2},
	106	[SPD600] = {MAIN_PLL, 230, 5, 2},
	107	[SPD800] = {MAIN_PLL, 123, 2, 2},
9cb5eaf2 LV	108	[SPD900] = {MAIN_PLL, 69, 1, 2},
9cb5eaf2 LV	109	[SPD1000] = {MAIN_PLL, 384, 5, 2},
c5f177de LV	110	},
	111	};
	112
	113	static struct pll_init_data tetris_pll_config[MAX_SYSCLK][NUM_SPDS] = {
	114	[SYSCLK_19MHz] = {
	115	[SPD200] = {TETRIS_PLL, 625, 6, 10},
	116	[SPD400] = {TETRIS_PLL, 125, 1, 6},
	117	[SPD600] = {TETRIS_PLL, 125, 1, 4},
	118	[SPD800] = {TETRIS_PLL, 333, 2, 4},
	119	[SPD900] = {TETRIS_PLL, 187, 2, 2},
	120	[SPD1000] = {TETRIS_PLL, 104, 1, 2},
	121	},
	122	[SYSCLK_24MHz] = {
	123	[SPD200] = {TETRIS_PLL, 250, 3, 10},
	124	[SPD400] = {TETRIS_PLL, 100, 1, 6},
	125	[SPD600] = {TETRIS_PLL, 100, 1, 4},
	126	[SPD800] = {TETRIS_PLL, 400, 3, 4},
	127	[SPD900] = {TETRIS_PLL, 75, 1, 2},
	128	[SPD1000] = {TETRIS_PLL, 250, 3, 2},
	129	},
	130	[SYSCLK_25MHz] = {
	131	[SPD200] = {TETRIS_PLL, 80, 1, 10},
	132	[SPD400] = {TETRIS_PLL, 96, 1, 6},
	133	[SPD600] = {TETRIS_PLL, 96, 1, 4},
	134	[SPD800] = {TETRIS_PLL, 128, 1, 4},
	135	[SPD900] = {TETRIS_PLL, 72, 1, 2},
	136	[SPD1000] = {TETRIS_PLL, 80, 1, 2},
	137	},
	138	[SYSCLK_26MHz] = {
	139	[SPD200] = {TETRIS_PLL, 307, 4, 10},
	140	[SPD400] = {TETRIS_PLL, 369, 4, 6},
	141	[SPD600] = {TETRIS_PLL, 369, 4, 4},
	142	[SPD800] = {TETRIS_PLL, 123, 1, 4},
	143	[SPD900] = {TETRIS_PLL, 69, 1, 2},
	144	[SPD1000] = {TETRIS_PLL, 384, 5, 2},
	145	},
ef76ebb1 LV	146	};
ef76ebb1 LV	147
c5f177de LV	148	static struct pll_init_data uart_pll_config[MAX_SYSCLK] = {
	149	[SYSCLK_19MHz] = {UART_PLL, 160, 1, 8},
	150	[SYSCLK_24MHz] = {UART_PLL, 128, 1, 8},
	151	[SYSCLK_25MHz] = {UART_PLL, 768, 5, 10},
	152	[SYSCLK_26MHz] = {UART_PLL, 384, 13, 2},
ef76ebb1 LV	153	};
ef76ebb1 LV	154
c5f177de LV	155	static struct pll_init_data nss_pll_config[MAX_SYSCLK] = {
	156	[SYSCLK_19MHz] = {NSS_PLL, 625, 6, 2},
	157	[SYSCLK_24MHz] = {NSS_PLL, 250, 3, 2},
	158	[SYSCLK_25MHz] = {NSS_PLL, 80, 1, 2},
	159	[SYSCLK_26MHz] = {NSS_PLL, 1000, 13, 2},
	160	};
	161
	162	static struct pll_init_data ddr3_pll_config[MAX_SYSCLK] = {
	163	[SYSCLK_19MHz] = {DDR3A_PLL, 167, 1, 16},
	164	[SYSCLK_24MHz] = {DDR3A_PLL, 133, 1, 16},
	165	[SYSCLK_25MHz] = {DDR3A_PLL, 128, 1, 16},
	166	[SYSCLK_26MHz] = {DDR3A_PLL, 123, 1, 16},
	167	};
bda920c6 VA	168
	169	struct pll_init_data *get_pll_init_data(int pll)
	170	{
ef76ebb1	171	int speed;
bda920c6	172	struct pll_init_data *data = NULL;
c5f177de	173	u8 sysclk_index = get_sysclk_index();
bda920c6 VA	174
	175	switch (pll) {
	176	case MAIN_PLL:
ef76ebb1	177	speed = get_max_dev_speed(dev_speeds);
c5f177de	178	data = &main_pll_config[sysclk_index][speed];
bda920c6 VA	179	break;
bda920c6 VA	180	case TETRIS_PLL:
ef76ebb1	181	speed = get_max_arm_speed(arm_speeds);
c5f177de	182	data = &tetris_pll_config[sysclk_index][speed];
bda920c6 VA	183	break;
bda920c6 VA	184	case NSS_PLL:
c5f177de	185	data = &nss_pll_config[sysclk_index];
bda920c6 VA	186	break;
bda920c6 VA	187	case UART_PLL:
c5f177de	188	data = &uart_pll_config[sysclk_index];
bda920c6 VA	189	break;
bda920c6 VA	190	case DDR3_PLL:
c5f177de	191	data = &ddr3_pll_config[sysclk_index];
bda920c6 VA	192	break;
	193	default:
	194	data = NULL;
	195	}
	196
	197	return data;
	198	}
	199
	200	s16 divn_val[16] = {
	201	-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1
	202	};
	203
4aa2ba3a	204	#if defined(CONFIG_MMC)
3b68939f RQ	205	int board_mmc_init(bd_t *bis)
	206	{
	207	if (psc_enable_module(KS2_LPSC_MMC)) {
	208	printf("%s module enabled failed\n", __func__);
	209	return -1;
	210	}
	211
4f490402 CJF	212	if (board_is_k2g_gp())
	213	omap_mmc_init(0, 0, 0, -1, -1);
	214
3b68939f RQ	215	omap_mmc_init(1, 0, 0, -1, -1);
	216	return 0;
	217	}
	218	#endif
	219
7234f215 CJF	220	#if defined(CONFIG_FIT_EMBED)
	221	int board_fit_config_name_match(const char *name)
	222	{
	223	bool eeprom_read = board_ti_was_eeprom_read();
	224
	225	if (!strcmp(name, "keystone-k2g-generic") && !eeprom_read)
	226	return 0;
	227	else if (!strcmp(name, "keystone-k2g-evm") && board_ti_is("66AK2GGP"))
	228	return 0;
bc420967 CJF	229	else if (!strcmp(name, "keystone-k2g-ice") && board_ti_is("66AK2GIC"))
bc420967 CJF	230	return 0;
7234f215 CJF	231	else
	232	return -1;
	233	}
	234	#endif
	235
5f48da9a CJF	236	#if defined(CONFIG_DTB_RESELECT)
	237	static int k2g_alt_board_detect(void)
	238	{
	239	int rc;
	240
	241	rc = i2c_set_bus_num(1);
	242	if (rc)
	243	return rc;
	244
	245	rc = i2c_probe(K2G_GP_AUDIO_CODEC_ADDRESS);
	246	if (rc)
	247	return rc;
	248
	249	ti_i2c_eeprom_am_set("66AK2GGP", "1.0X");
	250
	251	return 0;
	252	}
	253
e2924e59 LV	254	static void k2g_reset_mux_config(void)
	255	{
	256	/* Unlock the reset mux register */
	257	clrbits_le32(KS2_RSTMUX8, RSTMUX_LOCK8_MASK);
	258
	259	/* Configure BOOTCFG_RSTMUX8 for WDT event to cause a device reset */
	260	clrsetbits_le32(KS2_RSTMUX8, RSTMUX_OMODE8_MASK,
	261	RSTMUX_OMODE8_DEV_RESET << RSTMUX_OMODE8_SHIFT);
	262
	263	/* lock the reset mux register to prevent any spurious writes. */
	264	setbits_le32(KS2_RSTMUX8, RSTMUX_LOCK8_MASK);
	265	}
	266
e820f523	267	int embedded_dtb_select(void)
bda920c6	268	{
e820f523 CJF	269	int rc;
	270	rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
	271	CONFIG_EEPROM_CHIP_ADDRESS);
	272	if (rc) {
	273	rc = k2g_alt_board_detect();
	274	if (rc) {
	275	printf("Unable to do board detection\n");
	276	return -1;
	277	}
	278	}
bda920c6	279
e820f523	280	fdtdec_setup();
dd78b8cf	281
b9b342ea CJF	282	k2g_mux_config();
b9b342ea CJF	283
e2924e59 LV	284	k2g_reset_mux_config();
e2924e59 LV	285
4f490402 CJF	286	if (board_is_k2g_gp()) {
	287	/* deassert FLASH_HOLD */
	288	clrbits_le32(K2G_GPIO1_BANK2_BASE + K2G_GPIO_DIR_OFFSET,
	289	BIT(9));
	290	setbits_le32(K2G_GPIO1_BANK2_BASE + K2G_GPIO_SETDATA_OFFSET,
	291	BIT(9));
	292	}
83b9bf11	293
bda920c6 VA	294	return 0;
	295	}
	296	#endif
	297
752a8311 RQ	298	#ifdef CONFIG_BOARD_LATE_INIT
	299	int board_late_init(void)
	300	{
	301	#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_TI_I2C_BOARD_DETECT)
	302	int rc;
	303
	304	rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
	305	CONFIG_EEPROM_CHIP_ADDRESS);
	306	if (rc)
	307	printf("ti_i2c_eeprom_init failed %d\n", rc);
	308
	309	board_ti_set_ethaddr(1);
	310	#endif
	311
92761fcc CJF	312	#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
92761fcc CJF	313	if (board_is_k2g_gp())
382bee57	314	env_set("board_name", "66AK2GGP\0");
92761fcc	315	else if (board_is_k2g_ice())
382bee57	316	env_set("board_name", "66AK2GIC\0");
92761fcc	317	#endif
752a8311 RQ	318	return 0;
	319	}
	320	#endif
	321
e820f523 CJF	322	#ifdef CONFIG_BOARD_EARLY_INIT_F
	323	int board_early_init_f(void)
	324	{
	325	init_plls();
	326
	327	k2g_mux_config();
	328
	329	return 0;
	330	}
	331	#endif
	332
bda920c6 VA	333	#ifdef CONFIG_SPL_BUILD
	334	void spl_init_keystone_plls(void)
	335	{
	336	init_plls();
	337	}
	338	#endif
91266ccb VA	339
	340	#ifdef CONFIG_DRIVER_TI_KEYSTONE_NET
	341	struct eth_priv_t eth_priv_cfg[] = {
	342	{
	343	.int_name = "K2G_EMAC",
	344	.rx_flow = 0,
	345	.phy_addr = 0,
	346	.slave_port = 1,
	347	.sgmii_link_type = SGMII_LINK_MAC_PHY,
	348	.phy_if = PHY_INTERFACE_MODE_RGMII,
	349	},
	350	};
	351
	352	int get_num_eth_ports(void)
	353	{
	354	return sizeof(eth_priv_cfg) / sizeof(struct eth_priv_t);
	355	}
	356	#endif
58fac52d AD	357
	358	#ifdef CONFIG_TI_SECURE_DEVICE
	359	void board_pmmc_image_process(ulong pmmc_image, size_t pmmc_size)
	360	{
	361	int id = getenv_ulong("dev_pmmc", 10, 0);
	362	int ret;
	363
	364	if (!rproc_is_initialized())
	365	rproc_init();
	366
	367	ret = rproc_load(id, pmmc_image, pmmc_size);
	368	printf("Load Remote Processor %d with data@addr=0x%08lx %u bytes:%s\n",
	369	id, pmmc_image, pmmc_size, ret ? " Failed!" : " Success!");
	370
	371	if (!ret)
	372	rproc_start(id);
	373	}
	374
	375	U_BOOT_FIT_LOADABLE_HANDLER(IH_TYPE_PMMC, board_pmmc_image_process);
	376	#endif