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i2c: common changes for multibus/multiadapter support
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CommitLineData
1938f4a5
SG
1/*
2 * Copyright (c) 2011 The Chromium OS Authors.
3 * (C) Copyright 2002-2006
4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 *
6 * (C) Copyright 2002
7 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
8 * Marius Groeger <mgroeger@sysgo.de>
9 *
10 * See file CREDITS for list of people who contributed to this
11 * project.
12 *
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of
16 * the License, or (at your option) any later version.
17 *
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 * MA 02111-1307 USA
27 */
28
29#include <common.h>
30#include <linux/compiler.h>
31#include <version.h>
32#include <environment.h>
33#include <fdtdec.h>
f828bf25 34#include <fs.h>
e4fef6cf
SG
35#if defined(CONFIG_CMD_IDE)
36#include <ide.h>
37#endif
38#include <i2c.h>
1938f4a5
SG
39#include <initcall.h>
40#include <logbuff.h>
e4fef6cf
SG
41
42/* TODO: Can we move these into arch/ headers? */
43#ifdef CONFIG_8xx
44#include <mpc8xx.h>
45#endif
46#ifdef CONFIG_5xx
47#include <mpc5xx.h>
48#endif
49#ifdef CONFIG_MPC5xxx
50#include <mpc5xxx.h>
51#endif
52
a733b06b 53#include <os.h>
1938f4a5 54#include <post.h>
e4fef6cf 55#include <spi.h>
71c52dba 56#include <trace.h>
e4fef6cf 57#include <watchdog.h>
a733b06b 58#include <asm/errno.h>
1938f4a5 59#include <asm/io.h>
e4fef6cf
SG
60#ifdef CONFIG_MP
61#include <asm/mp.h>
62#endif
1938f4a5 63#include <asm/sections.h>
48a33806
SG
64#ifdef CONFIG_X86
65#include <asm/init_helpers.h>
66#include <asm/relocate.h>
67#endif
a733b06b
SG
68#ifdef CONFIG_SANDBOX
69#include <asm/state.h>
70#endif
1938f4a5
SG
71#include <linux/compiler.h>
72
73/*
74 * Pointer to initial global data area
75 *
76 * Here we initialize it if needed.
77 */
78#ifdef XTRN_DECLARE_GLOBAL_DATA_PTR
79#undef XTRN_DECLARE_GLOBAL_DATA_PTR
80#define XTRN_DECLARE_GLOBAL_DATA_PTR /* empty = allocate here */
81DECLARE_GLOBAL_DATA_PTR = (gd_t *) (CONFIG_SYS_INIT_GD_ADDR);
82#else
83DECLARE_GLOBAL_DATA_PTR;
84#endif
85
86/*
87 * sjg: IMO this code should be
88 * refactored to a single function, something like:
89 *
90 * void led_set_state(enum led_colour_t colour, int on);
91 */
92/************************************************************************
93 * Coloured LED functionality
94 ************************************************************************
95 * May be supplied by boards if desired
96 */
97inline void __coloured_LED_init(void) {}
98void coloured_LED_init(void)
99 __attribute__((weak, alias("__coloured_LED_init")));
100inline void __red_led_on(void) {}
101void red_led_on(void) __attribute__((weak, alias("__red_led_on")));
102inline void __red_led_off(void) {}
103void red_led_off(void) __attribute__((weak, alias("__red_led_off")));
104inline void __green_led_on(void) {}
105void green_led_on(void) __attribute__((weak, alias("__green_led_on")));
106inline void __green_led_off(void) {}
107void green_led_off(void) __attribute__((weak, alias("__green_led_off")));
108inline void __yellow_led_on(void) {}
109void yellow_led_on(void) __attribute__((weak, alias("__yellow_led_on")));
110inline void __yellow_led_off(void) {}
111void yellow_led_off(void) __attribute__((weak, alias("__yellow_led_off")));
112inline void __blue_led_on(void) {}
113void blue_led_on(void) __attribute__((weak, alias("__blue_led_on")));
114inline void __blue_led_off(void) {}
115void blue_led_off(void) __attribute__((weak, alias("__blue_led_off")));
116
117/*
118 * Why is gd allocated a register? Prior to reloc it might be better to
119 * just pass it around to each function in this file?
120 *
121 * After reloc one could argue that it is hardly used and doesn't need
122 * to be in a register. Or if it is it should perhaps hold pointers to all
123 * global data for all modules, so that post-reloc we can avoid the massive
124 * literal pool we get on ARM. Or perhaps just encourage each module to use
125 * a structure...
126 */
127
128/*
129 * Could the CONFIG_SPL_BUILD infection become a flag in gd?
130 */
131
e4fef6cf
SG
132#if defined(CONFIG_WATCHDOG)
133static int init_func_watchdog_init(void)
134{
135 puts(" Watchdog enabled\n");
136 WATCHDOG_RESET();
137
138 return 0;
139}
140
141int init_func_watchdog_reset(void)
142{
143 WATCHDOG_RESET();
144
145 return 0;
146}
147#endif /* CONFIG_WATCHDOG */
148
149void __board_add_ram_info(int use_default)
150{
151 /* please define platform specific board_add_ram_info() */
152}
153
154void board_add_ram_info(int)
155 __attribute__ ((weak, alias("__board_add_ram_info")));
156
1938f4a5
SG
157static int init_baud_rate(void)
158{
159 gd->baudrate = getenv_ulong("baudrate", 10, CONFIG_BAUDRATE);
160 return 0;
161}
162
163static int display_text_info(void)
164{
a733b06b 165#ifndef CONFIG_SANDBOX
1938f4a5
SG
166 ulong bss_start, bss_end;
167
632efa74 168#ifdef CONFIG_SYS_SYM_OFFSETS
1938f4a5
SG
169 bss_start = _bss_start_ofs + _TEXT_BASE;
170 bss_end = _bss_end_ofs + _TEXT_BASE;
632efa74
SG
171#else
172 bss_start = (ulong)&__bss_start;
173 bss_end = (ulong)&__bss_end;
174#endif
1938f4a5
SG
175 debug("U-Boot code: %08X -> %08lX BSS: -> %08lX\n",
176 CONFIG_SYS_TEXT_BASE, bss_start, bss_end);
a733b06b 177#endif
1938f4a5
SG
178
179#ifdef CONFIG_MODEM_SUPPORT
180 debug("Modem Support enabled\n");
181#endif
182#ifdef CONFIG_USE_IRQ
183 debug("IRQ Stack: %08lx\n", IRQ_STACK_START);
184 debug("FIQ Stack: %08lx\n", FIQ_STACK_START);
185#endif
186
187 return 0;
188}
189
190static int announce_dram_init(void)
191{
192 puts("DRAM: ");
193 return 0;
194}
195
e4fef6cf
SG
196#ifdef CONFIG_PPC
197static int init_func_ram(void)
198{
199#ifdef CONFIG_BOARD_TYPES
200 int board_type = gd->board_type;
201#else
202 int board_type = 0; /* use dummy arg */
203#endif
204
205 gd->ram_size = initdram(board_type);
206
207 if (gd->ram_size > 0)
208 return 0;
209
210 puts("*** failed ***\n");
211 return 1;
212}
213#endif
214
1938f4a5
SG
215static int show_dram_config(void)
216{
217 ulong size;
218
219#ifdef CONFIG_NR_DRAM_BANKS
220 int i;
221
222 debug("\nRAM Configuration:\n");
223 for (i = size = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
224 size += gd->bd->bi_dram[i].size;
225 debug("Bank #%d: %08lx ", i, gd->bd->bi_dram[i].start);
226#ifdef DEBUG
227 print_size(gd->bd->bi_dram[i].size, "\n");
228#endif
229 }
230 debug("\nDRAM: ");
231#else
232 size = gd->ram_size;
233#endif
234
e4fef6cf
SG
235 print_size(size, "");
236 board_add_ram_info(0);
237 putc('\n');
1938f4a5
SG
238
239 return 0;
240}
241
e4fef6cf
SG
242ulong get_effective_memsize(void)
243{
244#ifndef CONFIG_VERY_BIG_RAM
245 return gd->ram_size;
246#else
247 /* limit stack to what we can reasonable map */
248 return ((gd->ram_size > CONFIG_MAX_MEM_MAPPED) ?
249 CONFIG_MAX_MEM_MAPPED : gd->ram_size);
250#endif
251}
252
1938f4a5
SG
253void __dram_init_banksize(void)
254{
255#if defined(CONFIG_NR_DRAM_BANKS) && defined(CONFIG_SYS_SDRAM_BASE)
256 gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
257 gd->bd->bi_dram[0].size = get_effective_memsize();
258#endif
259}
260
261void dram_init_banksize(void)
262 __attribute__((weak, alias("__dram_init_banksize")));
263
3f4978c7
HS
264#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C) || \
265 defined(CONFIG_SYS_I2C)
e4fef6cf
SG
266static int init_func_i2c(void)
267{
268 puts("I2C: ");
269 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
270 puts("ready\n");
271 return 0;
272}
273#endif
274
275#if defined(CONFIG_HARD_SPI)
276static int init_func_spi(void)
277{
278 puts("SPI: ");
279 spi_init();
280 puts("ready\n");
281 return 0;
282}
283#endif
284
285__maybe_unused
1938f4a5
SG
286static int zero_global_data(void)
287{
288 memset((void *)gd, '\0', sizeof(gd_t));
289
290 return 0;
291}
292
293static int setup_mon_len(void)
294{
632efa74 295#ifdef CONFIG_SYS_SYM_OFFSETS
1938f4a5 296 gd->mon_len = _bss_end_ofs;
a733b06b
SG
297#elif defined(CONFIG_SANDBOX)
298 gd->mon_len = (ulong)&_end - (ulong)_init;
632efa74 299#else
e4fef6cf
SG
300 /* TODO: use (ulong)&__bss_end - (ulong)&__text_start; ? */
301 gd->mon_len = (ulong)&__bss_end - CONFIG_SYS_MONITOR_BASE;
632efa74 302#endif
1938f4a5
SG
303 return 0;
304}
305
306__weak int arch_cpu_init(void)
307{
308 return 0;
309}
310
f828bf25
SG
311#ifdef CONFIG_OF_HOSTFILE
312
313#define CHECK(x) err = (x); if (err) goto failed;
314
315/* Create an empty device tree blob */
316static int make_empty_fdt(void *fdt)
317{
318 int err;
319
320 CHECK(fdt_create(fdt, 256));
321 CHECK(fdt_finish_reservemap(fdt));
322 CHECK(fdt_begin_node(fdt, ""));
323 CHECK(fdt_end_node(fdt));
324 CHECK(fdt_finish(fdt));
325
326 return 0;
327failed:
328 printf("Unable to create empty FDT: %s\n", fdt_strerror(err));
329 return -EACCES;
330}
331
332static int read_fdt_from_file(void)
333{
334 struct sandbox_state *state = state_get_current();
335 void *blob;
336 int size;
337 int err;
338
339 blob = map_sysmem(CONFIG_SYS_FDT_LOAD_ADDR, 0);
340 if (!state->fdt_fname) {
341 err = make_empty_fdt(blob);
342 if (!err)
343 goto done;
344 return err;
345 }
346 err = fs_set_blk_dev("host", NULL, FS_TYPE_SANDBOX);
347 if (err)
348 return err;
349 size = fs_read(state->fdt_fname, CONFIG_SYS_FDT_LOAD_ADDR, 0, 0);
350 if (size < 0)
351 return -EIO;
352
353done:
354 gd->fdt_blob = blob;
355
356 return 0;
357}
358#endif
359
a733b06b
SG
360#ifdef CONFIG_SANDBOX
361static int setup_ram_buf(void)
362{
363 gd->arch.ram_buf = os_malloc(CONFIG_SYS_SDRAM_SIZE);
364 assert(gd->arch.ram_buf);
365 gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
366
367 return 0;
368}
369#endif
370
1938f4a5
SG
371static int setup_fdt(void)
372{
373#ifdef CONFIG_OF_EMBED
374 /* Get a pointer to the FDT */
375 gd->fdt_blob = _binary_dt_dtb_start;
376#elif defined CONFIG_OF_SEPARATE
377 /* FDT is at end of image */
632efa74 378# ifdef CONFIG_SYS_SYM_OFFSETS
1938f4a5 379 gd->fdt_blob = (void *)(_end_ofs + CONFIG_SYS_TEXT_BASE);
632efa74
SG
380# else
381 gd->fdt_blob = (ulong *)&_end;
382# endif
f828bf25
SG
383#elif defined(CONFIG_OF_HOSTFILE)
384 if (read_fdt_from_file()) {
385 puts("Failed to read control FDT\n");
386 return -1;
387 }
1938f4a5
SG
388#endif
389 /* Allow the early environment to override the fdt address */
390 gd->fdt_blob = (void *)getenv_ulong("fdtcontroladdr", 16,
391 (uintptr_t)gd->fdt_blob);
392 return 0;
393}
394
395/* Get the top of usable RAM */
396__weak ulong board_get_usable_ram_top(ulong total_size)
397{
398 return gd->ram_top;
399}
400
401static int setup_dest_addr(void)
402{
403 debug("Monitor len: %08lX\n", gd->mon_len);
404 /*
405 * Ram is setup, size stored in gd !!
406 */
407 debug("Ram size: %08lX\n", (ulong)gd->ram_size);
408#if defined(CONFIG_SYS_MEM_TOP_HIDE)
409 /*
410 * Subtract specified amount of memory to hide so that it won't
411 * get "touched" at all by U-Boot. By fixing up gd->ram_size
412 * the Linux kernel should now get passed the now "corrected"
413 * memory size and won't touch it either. This should work
414 * for arch/ppc and arch/powerpc. Only Linux board ports in
415 * arch/powerpc with bootwrapper support, that recalculate the
416 * memory size from the SDRAM controller setup will have to
417 * get fixed.
418 */
419 gd->ram_size -= CONFIG_SYS_MEM_TOP_HIDE;
420#endif
421#ifdef CONFIG_SYS_SDRAM_BASE
422 gd->ram_top = CONFIG_SYS_SDRAM_BASE;
423#endif
e4fef6cf 424 gd->ram_top += get_effective_memsize();
1938f4a5 425 gd->ram_top = board_get_usable_ram_top(gd->mon_len);
a0ba279a 426 gd->relocaddr = gd->ram_top;
1938f4a5 427 debug("Ram top: %08lX\n", (ulong)gd->ram_top);
e4fef6cf
SG
428#if defined(CONFIG_MP) && (defined(CONFIG_MPC86xx) || defined(CONFIG_E500))
429 /*
430 * We need to make sure the location we intend to put secondary core
431 * boot code is reserved and not used by any part of u-boot
432 */
a0ba279a
MY
433 if (gd->relocaddr > determine_mp_bootpg(NULL)) {
434 gd->relocaddr = determine_mp_bootpg(NULL);
435 debug("Reserving MP boot page to %08lx\n", gd->relocaddr);
e4fef6cf
SG
436 }
437#endif
1938f4a5
SG
438 return 0;
439}
440
441#if defined(CONFIG_LOGBUFFER) && !defined(CONFIG_ALT_LB_ADDR)
442static int reserve_logbuffer(void)
443{
444 /* reserve kernel log buffer */
a0ba279a 445 gd->relocaddr -= LOGBUFF_RESERVE;
1938f4a5 446 debug("Reserving %dk for kernel logbuffer at %08lx\n", LOGBUFF_LEN,
a0ba279a 447 gd->relocaddr);
1938f4a5
SG
448 return 0;
449}
450#endif
451
452#ifdef CONFIG_PRAM
453/* reserve protected RAM */
454static int reserve_pram(void)
455{
456 ulong reg;
457
458 reg = getenv_ulong("pram", 10, CONFIG_PRAM);
a0ba279a 459 gd->relocaddr -= (reg << 10); /* size is in kB */
1938f4a5 460 debug("Reserving %ldk for protected RAM at %08lx\n", reg,
a0ba279a 461 gd->relocaddr);
1938f4a5
SG
462 return 0;
463}
464#endif /* CONFIG_PRAM */
465
466/* Round memory pointer down to next 4 kB limit */
467static int reserve_round_4k(void)
468{
a0ba279a 469 gd->relocaddr &= ~(4096 - 1);
1938f4a5
SG
470 return 0;
471}
472
473#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF)) && \
474 defined(CONFIG_ARM)
475static int reserve_mmu(void)
476{
477 /* reserve TLB table */
478 gd->arch.tlb_size = 4096 * 4;
a0ba279a 479 gd->relocaddr -= gd->arch.tlb_size;
1938f4a5
SG
480
481 /* round down to next 64 kB limit */
a0ba279a 482 gd->relocaddr &= ~(0x10000 - 1);
1938f4a5 483
a0ba279a 484 gd->arch.tlb_addr = gd->relocaddr;
1938f4a5
SG
485 debug("TLB table from %08lx to %08lx\n", gd->arch.tlb_addr,
486 gd->arch.tlb_addr + gd->arch.tlb_size);
487 return 0;
488}
489#endif
490
491#ifdef CONFIG_LCD
492static int reserve_lcd(void)
493{
494#ifdef CONFIG_FB_ADDR
495 gd->fb_base = CONFIG_FB_ADDR;
496#else
497 /* reserve memory for LCD display (always full pages) */
a0ba279a
MY
498 gd->relocaddr = lcd_setmem(gd->relocaddr);
499 gd->fb_base = gd->relocaddr;
1938f4a5
SG
500#endif /* CONFIG_FB_ADDR */
501 return 0;
502}
503#endif /* CONFIG_LCD */
504
71c52dba
SG
505static int reserve_trace(void)
506{
507#ifdef CONFIG_TRACE
508 gd->relocaddr -= CONFIG_TRACE_BUFFER_SIZE;
509 gd->trace_buff = map_sysmem(gd->relocaddr, CONFIG_TRACE_BUFFER_SIZE);
510 debug("Reserving %dk for trace data at: %08lx\n",
511 CONFIG_TRACE_BUFFER_SIZE >> 10, gd->relocaddr);
512#endif
513
514 return 0;
515}
516
e4fef6cf 517#if defined(CONFIG_VIDEO) && (!defined(CONFIG_PPC) || defined(CONFIG_8xx)) \
48a33806 518 && !defined(CONFIG_ARM) && !defined(CONFIG_X86)
e4fef6cf
SG
519static int reserve_video(void)
520{
521 /* reserve memory for video display (always full pages) */
a0ba279a
MY
522 gd->relocaddr = video_setmem(gd->relocaddr);
523 gd->fb_base = gd->relocaddr;
e4fef6cf
SG
524
525 return 0;
526}
527#endif
528
1938f4a5
SG
529static int reserve_uboot(void)
530{
531 /*
532 * reserve memory for U-Boot code, data & bss
533 * round down to next 4 kB limit
534 */
a0ba279a
MY
535 gd->relocaddr -= gd->mon_len;
536 gd->relocaddr &= ~(4096 - 1);
e4fef6cf
SG
537#ifdef CONFIG_E500
538 /* round down to next 64 kB limit so that IVPR stays aligned */
a0ba279a 539 gd->relocaddr &= ~(65536 - 1);
e4fef6cf 540#endif
1938f4a5
SG
541
542 debug("Reserving %ldk for U-Boot at: %08lx\n", gd->mon_len >> 10,
a0ba279a
MY
543 gd->relocaddr);
544
545 gd->start_addr_sp = gd->relocaddr;
546
1938f4a5
SG
547 return 0;
548}
549
8cae8a68 550#ifndef CONFIG_SPL_BUILD
1938f4a5
SG
551/* reserve memory for malloc() area */
552static int reserve_malloc(void)
553{
a0ba279a 554 gd->start_addr_sp = gd->start_addr_sp - TOTAL_MALLOC_LEN;
1938f4a5 555 debug("Reserving %dk for malloc() at: %08lx\n",
a0ba279a 556 TOTAL_MALLOC_LEN >> 10, gd->start_addr_sp);
1938f4a5
SG
557 return 0;
558}
559
560/* (permanently) allocate a Board Info struct */
561static int reserve_board(void)
562{
a0ba279a
MY
563 gd->start_addr_sp -= sizeof(bd_t);
564 gd->bd = (bd_t *)map_sysmem(gd->start_addr_sp, sizeof(bd_t));
1938f4a5
SG
565 memset(gd->bd, '\0', sizeof(bd_t));
566 debug("Reserving %zu Bytes for Board Info at: %08lx\n",
a0ba279a 567 sizeof(bd_t), gd->start_addr_sp);
1938f4a5
SG
568 return 0;
569}
8cae8a68 570#endif
1938f4a5
SG
571
572static int setup_machine(void)
573{
574#ifdef CONFIG_MACH_TYPE
575 gd->bd->bi_arch_number = CONFIG_MACH_TYPE; /* board id for Linux */
576#endif
577 return 0;
578}
579
580static int reserve_global_data(void)
581{
a0ba279a
MY
582 gd->start_addr_sp -= sizeof(gd_t);
583 gd->new_gd = (gd_t *)map_sysmem(gd->start_addr_sp, sizeof(gd_t));
1938f4a5 584 debug("Reserving %zu Bytes for Global Data at: %08lx\n",
a0ba279a 585 sizeof(gd_t), gd->start_addr_sp);
1938f4a5
SG
586 return 0;
587}
588
589static int reserve_fdt(void)
590{
591 /*
592 * If the device tree is sitting immediate above our image then we
593 * must relocate it. If it is embedded in the data section, then it
594 * will be relocated with other data.
595 */
596 if (gd->fdt_blob) {
597 gd->fdt_size = ALIGN(fdt_totalsize(gd->fdt_blob) + 0x1000, 32);
598
a0ba279a
MY
599 gd->start_addr_sp -= gd->fdt_size;
600 gd->new_fdt = map_sysmem(gd->start_addr_sp, gd->fdt_size);
a733b06b 601 debug("Reserving %lu Bytes for FDT at: %08lx\n",
a0ba279a 602 gd->fdt_size, gd->start_addr_sp);
1938f4a5
SG
603 }
604
605 return 0;
606}
607
608static int reserve_stacks(void)
609{
8cae8a68
SG
610#ifdef CONFIG_SPL_BUILD
611# ifdef CONFIG_ARM
a0ba279a
MY
612 gd->start_addr_sp -= 128; /* leave 32 words for abort-stack */
613 gd->irq_sp = gd->start_addr_sp;
8cae8a68
SG
614# endif
615#else
e4fef6cf
SG
616# ifdef CONFIG_PPC
617 ulong *s;
618# endif
8cae8a68 619
1938f4a5 620 /* setup stack pointer for exceptions */
a0ba279a
MY
621 gd->start_addr_sp -= 16;
622 gd->start_addr_sp &= ~0xf;
623 gd->irq_sp = gd->start_addr_sp;
1938f4a5
SG
624
625 /*
626 * Handle architecture-specific things here
627 * TODO(sjg@chromium.org): Perhaps create arch_reserve_stack()
628 * to handle this and put in arch/xxx/lib/stack.c
629 */
630# ifdef CONFIG_ARM
631# ifdef CONFIG_USE_IRQ
a0ba279a 632 gd->start_addr_sp -= (CONFIG_STACKSIZE_IRQ + CONFIG_STACKSIZE_FIQ);
1938f4a5 633 debug("Reserving %zu Bytes for IRQ stack at: %08lx\n",
a0ba279a 634 CONFIG_STACKSIZE_IRQ + CONFIG_STACKSIZE_FIQ, gd->start_addr_sp);
1938f4a5
SG
635
636 /* 8-byte alignment for ARM ABI compliance */
a0ba279a 637 gd->start_addr_sp &= ~0x07;
1938f4a5
SG
638# endif
639 /* leave 3 words for abort-stack, plus 1 for alignment */
a0ba279a 640 gd->start_addr_sp -= 16;
e4fef6cf
SG
641# elif defined(CONFIG_PPC)
642 /* Clear initial stack frame */
a0ba279a 643 s = (ulong *) gd->start_addr_sp;
e4fef6cf
SG
644 *s = 0; /* Terminate back chain */
645 *++s = 0; /* NULL return address */
8cae8a68 646# endif /* Architecture specific code */
1938f4a5
SG
647
648 return 0;
8cae8a68 649#endif
1938f4a5
SG
650}
651
652static int display_new_sp(void)
653{
a0ba279a 654 debug("New Stack Pointer is: %08lx\n", gd->start_addr_sp);
1938f4a5
SG
655
656 return 0;
657}
658
e4fef6cf
SG
659#ifdef CONFIG_PPC
660static int setup_board_part1(void)
661{
662 bd_t *bd = gd->bd;
663
664 /*
665 * Save local variables to board info struct
666 */
667
668 bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; /* start of memory */
669 bd->bi_memsize = gd->ram_size; /* size in bytes */
670
671#ifdef CONFIG_SYS_SRAM_BASE
672 bd->bi_sramstart = CONFIG_SYS_SRAM_BASE; /* start of SRAM */
673 bd->bi_sramsize = CONFIG_SYS_SRAM_SIZE; /* size of SRAM */
674#endif
675
676#if defined(CONFIG_8xx) || defined(CONFIG_8260) || defined(CONFIG_5xx) || \
677 defined(CONFIG_E500) || defined(CONFIG_MPC86xx)
678 bd->bi_immr_base = CONFIG_SYS_IMMR; /* base of IMMR register */
679#endif
680#if defined(CONFIG_MPC5xxx)
681 bd->bi_mbar_base = CONFIG_SYS_MBAR; /* base of internal registers */
682#endif
683#if defined(CONFIG_MPC83xx)
684 bd->bi_immrbar = CONFIG_SYS_IMMR;
685#endif
e4fef6cf
SG
686
687 return 0;
688}
689
690static int setup_board_part2(void)
691{
692 bd_t *bd = gd->bd;
693
694 bd->bi_intfreq = gd->cpu_clk; /* Internal Freq, in Hz */
695 bd->bi_busfreq = gd->bus_clk; /* Bus Freq, in Hz */
696#if defined(CONFIG_CPM2)
697 bd->bi_cpmfreq = gd->arch.cpm_clk;
698 bd->bi_brgfreq = gd->arch.brg_clk;
699 bd->bi_sccfreq = gd->arch.scc_clk;
700 bd->bi_vco = gd->arch.vco_out;
701#endif /* CONFIG_CPM2 */
702#if defined(CONFIG_MPC512X)
703 bd->bi_ipsfreq = gd->arch.ips_clk;
704#endif /* CONFIG_MPC512X */
705#if defined(CONFIG_MPC5xxx)
706 bd->bi_ipbfreq = gd->arch.ipb_clk;
707 bd->bi_pcifreq = gd->pci_clk;
708#endif /* CONFIG_MPC5xxx */
709
710 return 0;
711}
712#endif
713
714#ifdef CONFIG_SYS_EXTBDINFO
715static int setup_board_extra(void)
716{
717 bd_t *bd = gd->bd;
718
719 strncpy((char *) bd->bi_s_version, "1.2", sizeof(bd->bi_s_version));
720 strncpy((char *) bd->bi_r_version, U_BOOT_VERSION,
721 sizeof(bd->bi_r_version));
722
723 bd->bi_procfreq = gd->cpu_clk; /* Processor Speed, In Hz */
724 bd->bi_plb_busfreq = gd->bus_clk;
725#if defined(CONFIG_405GP) || defined(CONFIG_405EP) || \
726 defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
727 defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
728 bd->bi_pci_busfreq = get_PCI_freq();
729 bd->bi_opbfreq = get_OPB_freq();
730#elif defined(CONFIG_XILINX_405)
731 bd->bi_pci_busfreq = get_PCI_freq();
732#endif
733
734 return 0;
735}
736#endif
737
1938f4a5
SG
738#ifdef CONFIG_POST
739static int init_post(void)
740{
741 post_bootmode_init();
742 post_run(NULL, POST_ROM | post_bootmode_get(0));
743
744 return 0;
745}
746#endif
747
748static int setup_baud_rate(void)
749{
750 /* Ick, can we get rid of this line? */
751 gd->bd->bi_baudrate = gd->baudrate;
752
753 return 0;
754}
755
756static int setup_dram_config(void)
757{
758 /* Ram is board specific, so move it to board code ... */
759 dram_init_banksize();
760
761 return 0;
762}
763
764static int reloc_fdt(void)
765{
766 if (gd->new_fdt) {
767 memcpy(gd->new_fdt, gd->fdt_blob, gd->fdt_size);
768 gd->fdt_blob = gd->new_fdt;
769 }
770
771 return 0;
772}
773
774static int setup_reloc(void)
775{
a0ba279a 776 gd->reloc_off = gd->relocaddr - CONFIG_SYS_TEXT_BASE;
1938f4a5
SG
777 memcpy(gd->new_gd, (char *)gd, sizeof(gd_t));
778
779 debug("Relocation Offset is: %08lx\n", gd->reloc_off);
a733b06b 780 debug("Relocating to %08lx, new gd at %08lx, sp at %08lx\n",
a0ba279a
MY
781 gd->relocaddr, (ulong)map_to_sysmem(gd->new_gd),
782 gd->start_addr_sp);
1938f4a5
SG
783
784 return 0;
785}
786
787/* ARM calls relocate_code from its crt0.S */
788#if !defined(CONFIG_ARM)
789
790static int jump_to_copy(void)
791{
48a33806
SG
792 /*
793 * x86 is special, but in a nice way. It uses a trampoline which
794 * enables the dcache if possible.
795 *
796 * For now, other archs use relocate_code(), which is implemented
797 * similarly for all archs. When we do generic relocation, hopefully
798 * we can make all archs enable the dcache prior to relocation.
799 */
800#ifdef CONFIG_X86
801 /*
802 * SDRAM and console are now initialised. The final stack can now
803 * be setup in SDRAM. Code execution will continue in Flash, but
804 * with the stack in SDRAM and Global Data in temporary memory
805 * (CPU cache)
806 */
807 board_init_f_r_trampoline(gd->start_addr_sp);
a733b06b
SG
808#elif defined(CONFIG_SANDBOX)
809 board_init_r(gd->new_gd, 0);
48a33806 810#else
a0ba279a 811 relocate_code(gd->start_addr_sp, gd->new_gd, gd->relocaddr);
48a33806 812#endif
1938f4a5
SG
813
814 return 0;
815}
816#endif
817
818/* Record the board_init_f() bootstage (after arch_cpu_init()) */
819static int mark_bootstage(void)
820{
821 bootstage_mark_name(BOOTSTAGE_ID_START_UBOOT_F, "board_init_f");
822
823 return 0;
824}
825
826static init_fnc_t init_sequence_f[] = {
e4fef6cf
SG
827#if !defined(CONFIG_CPM2) && !defined(CONFIG_MPC512X) && \
828 !defined(CONFIG_MPC83xx) && !defined(CONFIG_MPC85xx) && \
7525c2da 829 !defined(CONFIG_MPC86xx) && !defined(CONFIG_X86)
632efa74 830 zero_global_data,
a733b06b
SG
831#endif
832#ifdef CONFIG_SANDBOX
833 setup_ram_buf,
e4fef6cf 834#endif
1938f4a5 835 setup_mon_len,
71c52dba
SG
836 setup_fdt,
837 trace_early_init,
e4fef6cf
SG
838#if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)
839 /* TODO: can this go into arch_cpu_init()? */
840 probecpu,
841#endif
1938f4a5 842 arch_cpu_init, /* basic arch cpu dependent setup */
48a33806
SG
843#ifdef CONFIG_X86
844 cpu_init_f, /* TODO(sjg@chromium.org): remove */
845# ifdef CONFIG_OF_CONTROL
846 find_fdt, /* TODO(sjg@chromium.org): remove */
847# endif
848#endif
1938f4a5
SG
849 mark_bootstage,
850#ifdef CONFIG_OF_CONTROL
851 fdtdec_check_fdt,
852#endif
853#if defined(CONFIG_BOARD_EARLY_INIT_F)
854 board_early_init_f,
855#endif
e4fef6cf
SG
856 /* TODO: can any of this go into arch_cpu_init()? */
857#if defined(CONFIG_PPC) && !defined(CONFIG_8xx_CPUCLK_DEFAULT)
858 get_clocks, /* get CPU and bus clocks (etc.) */
859#if defined(CONFIG_TQM8xxL) && !defined(CONFIG_TQM866M) \
860 && !defined(CONFIG_TQM885D)
861 adjust_sdram_tbs_8xx,
862#endif
863 /* TODO: can we rename this to timer_init()? */
864 init_timebase,
865#endif
e4fef6cf 866#ifdef CONFIG_ARM
1938f4a5 867 timer_init, /* initialize timer */
e4fef6cf 868#endif
e4fef6cf
SG
869#ifdef CONFIG_SYS_ALLOC_DPRAM
870#if !defined(CONFIG_CPM2)
871 dpram_init,
872#endif
873#endif
874#if defined(CONFIG_BOARD_POSTCLK_INIT)
875 board_postclk_init,
b8521b74
MY
876#endif
877#ifdef CONFIG_FSL_ESDHC
878 get_clocks,
1938f4a5
SG
879#endif
880 env_init, /* initialize environment */
e4fef6cf
SG
881#if defined(CONFIG_8xx_CPUCLK_DEFAULT)
882 /* get CPU and bus clocks according to the environment variable */
883 get_clocks_866,
884 /* adjust sdram refresh rate according to the new clock */
885 sdram_adjust_866,
886 init_timebase,
887#endif
1938f4a5
SG
888 init_baud_rate, /* initialze baudrate settings */
889 serial_init, /* serial communications setup */
890 console_init_f, /* stage 1 init of console */
a733b06b
SG
891#ifdef CONFIG_SANDBOX
892 sandbox_early_getopt_check,
893#endif
894#ifdef CONFIG_OF_CONTROL
895 fdtdec_prepare_fdt,
48a33806 896#endif
1938f4a5
SG
897 display_options, /* say that we are here */
898 display_text_info, /* show debugging info if required */
e4fef6cf
SG
899#if defined(CONFIG_8260)
900 prt_8260_rsr,
901 prt_8260_clks,
902#endif /* CONFIG_8260 */
903#if defined(CONFIG_MPC83xx)
904 prt_83xx_rsr,
905#endif
906#ifdef CONFIG_PPC
907 checkcpu,
908#endif
1938f4a5
SG
909#if defined(CONFIG_DISPLAY_CPUINFO)
910 print_cpuinfo, /* display cpu info (and speed) */
911#endif
e4fef6cf
SG
912#if defined(CONFIG_MPC5xxx)
913 prt_mpc5xxx_clks,
914#endif /* CONFIG_MPC5xxx */
1938f4a5
SG
915#if defined(CONFIG_DISPLAY_BOARDINFO)
916 checkboard, /* display board info */
e4fef6cf
SG
917#endif
918 INIT_FUNC_WATCHDOG_INIT
919#if defined(CONFIG_MISC_INIT_F)
920 misc_init_f,
921#endif
922 INIT_FUNC_WATCHDOG_RESET
3f4978c7
HS
923#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C) || \
924 defined(CONFIG_SYS_I2C)
e4fef6cf
SG
925 init_func_i2c,
926#endif
927#if defined(CONFIG_HARD_SPI)
928 init_func_spi,
929#endif
930#ifdef CONFIG_X86
931 dram_init_f, /* configure available RAM banks */
8b42dfc3 932 calculate_relocation_address,
1938f4a5
SG
933#endif
934 announce_dram_init,
935 /* TODO: unify all these dram functions? */
936#ifdef CONFIG_ARM
937 dram_init, /* configure available RAM banks */
938#endif
e4fef6cf
SG
939#ifdef CONFIG_PPC
940 init_func_ram,
941#endif
942#ifdef CONFIG_POST
943 post_init_f,
944#endif
945 INIT_FUNC_WATCHDOG_RESET
946#if defined(CONFIG_SYS_DRAM_TEST)
947 testdram,
948#endif /* CONFIG_SYS_DRAM_TEST */
949 INIT_FUNC_WATCHDOG_RESET
950
1938f4a5
SG
951#ifdef CONFIG_POST
952 init_post,
953#endif
e4fef6cf 954 INIT_FUNC_WATCHDOG_RESET
1938f4a5
SG
955 /*
956 * Now that we have DRAM mapped and working, we can
957 * relocate the code and continue running from DRAM.
958 *
959 * Reserve memory at end of RAM for (top down in that order):
960 * - area that won't get touched by U-Boot and Linux (optional)
961 * - kernel log buffer
962 * - protected RAM
963 * - LCD framebuffer
964 * - monitor code
965 * - board info struct
966 */
967 setup_dest_addr,
968#if defined(CONFIG_LOGBUFFER) && !defined(CONFIG_ALT_LB_ADDR)
969 reserve_logbuffer,
970#endif
971#ifdef CONFIG_PRAM
972 reserve_pram,
973#endif
974 reserve_round_4k,
975#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF)) && \
976 defined(CONFIG_ARM)
977 reserve_mmu,
978#endif
979#ifdef CONFIG_LCD
980 reserve_lcd,
e4fef6cf 981#endif
71c52dba 982 reserve_trace,
e4fef6cf
SG
983 /* TODO: Why the dependency on CONFIG_8xx? */
984#if defined(CONFIG_VIDEO) && (!defined(CONFIG_PPC) || defined(CONFIG_8xx)) \
48a33806 985 && !defined(CONFIG_ARM) && !defined(CONFIG_X86)
e4fef6cf 986 reserve_video,
1938f4a5
SG
987#endif
988 reserve_uboot,
8cae8a68 989#ifndef CONFIG_SPL_BUILD
1938f4a5
SG
990 reserve_malloc,
991 reserve_board,
8cae8a68 992#endif
1938f4a5
SG
993 setup_machine,
994 reserve_global_data,
995 reserve_fdt,
996 reserve_stacks,
997 setup_dram_config,
998 show_dram_config,
e4fef6cf
SG
999#ifdef CONFIG_PPC
1000 setup_board_part1,
1001 INIT_FUNC_WATCHDOG_RESET
1002 setup_board_part2,
1003#endif
1938f4a5
SG
1004 setup_baud_rate,
1005 display_new_sp,
e4fef6cf
SG
1006#ifdef CONFIG_SYS_EXTBDINFO
1007 setup_board_extra,
1008#endif
1009 INIT_FUNC_WATCHDOG_RESET
1938f4a5
SG
1010 reloc_fdt,
1011 setup_reloc,
1012#ifndef CONFIG_ARM
1013 jump_to_copy,
1014#endif
1015 NULL,
1016};
1017
1018void board_init_f(ulong boot_flags)
1019{
48a33806 1020#ifndef CONFIG_X86
1938f4a5
SG
1021 gd_t data;
1022
1023 gd = &data;
48a33806 1024#endif
1938f4a5
SG
1025
1026 gd->flags = boot_flags;
1027
1028 if (initcall_run_list(init_sequence_f))
1029 hang();
1030
1031#ifndef CONFIG_ARM
1032 /* NOTREACHED - jump_to_copy() does not return */
1033 hang();
1034#endif
1035}
1036
48a33806
SG
1037#ifdef CONFIG_X86
1038/*
1039 * For now this code is only used on x86.
1040 *
1041 * init_sequence_f_r is the list of init functions which are run when
1042 * U-Boot is executing from Flash with a semi-limited 'C' environment.
1043 * The following limitations must be considered when implementing an
1044 * '_f_r' function:
1045 * - 'static' variables are read-only
1046 * - Global Data (gd->xxx) is read/write
1047 *
1048 * The '_f_r' sequence must, as a minimum, copy U-Boot to RAM (if
1049 * supported). It _should_, if possible, copy global data to RAM and
1050 * initialise the CPU caches (to speed up the relocation process)
1051 *
1052 * NOTE: At present only x86 uses this route, but it is intended that
1053 * all archs will move to this when generic relocation is implemented.
1054 */
1055static init_fnc_t init_sequence_f_r[] = {
1056 init_cache_f_r,
1057 copy_uboot_to_ram,
1058 clear_bss,
1059 do_elf_reloc_fixups,
1060
1061 NULL,
1062};
1063
1064void board_init_f_r(void)
1065{
1066 if (initcall_run_list(init_sequence_f_r))
1067 hang();
1068
1069 /*
1070 * U-Boot has been copied into SDRAM, the BSS has been cleared etc.
1071 * Transfer execution from Flash to RAM by calculating the address
1072 * of the in-RAM copy of board_init_r() and calling it
1073 */
1074 (board_init_r + gd->reloc_off)(gd, gd->relocaddr);
1075
1076 /* NOTREACHED - board_init_r() does not return */
1077 hang();
1078}
1079#endif /* CONFIG_X86 */