[people/ms/u-boot.git] / cpu / ppc4xx / cpu_init.c

/*
 * (C) Copyright 2000-2007
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>
#include <watchdog.h>
#include <ppc4xx_enet.h>
#include <asm/processor.h>
#include <asm/gpio.h>
#include <ppc4xx.h>

#if defined(CONFIG_405GP)  || defined(CONFIG_405EP)
DECLARE_GLOBAL_DATA_PTR;
#endif

#ifndef CONFIG_SYS_PLL_RECONFIG
#define CONFIG_SYS_PLL_RECONFIG	0
#endif

void reconfigure_pll(u32 new_cpu_freq)
{
#if defined(CONFIG_440EPX)
	int	reset_needed = 0;
	u32	reg, temp;
	u32	prbdv0, target_prbdv0,				/* CLK_PRIMBD */
		fwdva, target_fwdva, fwdvb, target_fwdvb,	/* CLK_PLLD */
		fbdv, target_fbdv, lfbdv, target_lfbdv,
		perdv0,	target_perdv0,				/* CLK_PERD */
		spcid0,	target_spcid0;				/* CLK_SPCID */

	/* Reconfigure clocks if necessary.
	 * See PPC440EPx User's Manual, sections 8.2 and 14 */
	if (new_cpu_freq == 667) {
		target_prbdv0 = 2;
		target_fwdva = 2;
		target_fwdvb = 4;
		target_fbdv = 20;
		target_lfbdv = 1;
		target_perdv0 = 4;
		target_spcid0 = 4;

		mfcpr(CPR0_PRIMBD0, reg);
		temp = (reg & PRBDV_MASK) >> 24;
		prbdv0 = temp ? temp : 8;
		if (prbdv0 != target_prbdv0) {
			reg &= ~PRBDV_MASK;
			reg |= ((target_prbdv0 == 8 ? 0 : target_prbdv0) << 24);
			mtcpr(CPR0_PRIMBD0, reg);
			reset_needed = 1;
		}

		mfcpr(CPR0_PLLD, reg);

		temp = (reg & PLLD_FWDVA_MASK) >> 16;
		fwdva = temp ? temp : 16;

		temp = (reg & PLLD_FWDVB_MASK) >> 8;
		fwdvb = temp ? temp : 8;

		temp = (reg & PLLD_FBDV_MASK) >> 24;
		fbdv = temp ? temp : 32;

		temp = (reg & PLLD_LFBDV_MASK);
		lfbdv = temp ? temp : 64;

		if (fwdva != target_fwdva || fbdv != target_fbdv || lfbdv != target_lfbdv) {
			reg &= ~(PLLD_FWDVA_MASK | PLLD_FWDVB_MASK |
				 PLLD_FBDV_MASK | PLLD_LFBDV_MASK);
			reg |= ((target_fwdva == 16 ? 0 : target_fwdva) << 16) |
				((target_fwdvb == 8 ? 0 : target_fwdvb) << 8) |
				((target_fbdv == 32 ? 0 : target_fbdv) << 24) |
				(target_lfbdv == 64 ? 0 : target_lfbdv);
			mtcpr(CPR0_PLLD, reg);
			reset_needed = 1;
		}

		mfcpr(CPR0_PERD, reg);
		perdv0 = (reg & CPR0_PERD_PERDV0_MASK) >> 24;
		if (perdv0 != target_perdv0) {
			reg &= ~CPR0_PERD_PERDV0_MASK;
			reg |= (target_perdv0 << 24);
			mtcpr(CPR0_PERD, reg);
			reset_needed = 1;
		}

		mfcpr(CPR0_SPCID, reg);
		temp = (reg & CPR0_SPCID_SPCIDV0_MASK) >> 24;
		spcid0 = temp ? temp : 4;
		if (spcid0 != target_spcid0) {
			reg &= ~CPR0_SPCID_SPCIDV0_MASK;
			reg |= ((target_spcid0 == 4 ? 0 : target_spcid0) << 24);
			mtcpr(CPR0_SPCID, reg);
			reset_needed = 1;
		}

		/* Set reload inhibit so configuration will persist across
		 * processor resets */
		mfcpr(CPR0_ICFG, reg);
		reg &= ~CPR0_ICFG_RLI_MASK;
		reg |= 1 << 31;
		mtcpr(CPR0_ICFG, reg);
	}

	/* Reset processor if configuration changed */
	if (reset_needed) {
		__asm__ __volatile__ ("sync; isync");
		mtspr(SPRN_DBCR0, 0x20000000);
	}
#endif
}

/*
 * Breath some life into the CPU...
 *
 * Reconfigure PLL if necessary,
 * set up the memory map,
 * initialize a bunch of registers
 */
void
cpu_init_f (void)
{
#if defined(CONFIG_WATCHDOG) || defined(CONFIG_440GX) || defined(CONFIG_460EX)
	u32 val;
#endif

	reconfigure_pll(CONFIG_SYS_PLL_RECONFIG);

#if (defined(CONFIG_405EP) || defined (CONFIG_405EX)) && !defined(CONFIG_SYS_4xx_GPIO_TABLE)
	/*
	 * GPIO0 setup (select GPIO or alternate function)
	 */
#if defined(CONFIG_SYS_GPIO0_OR)
	out32(GPIO0_OR, CONFIG_SYS_GPIO0_OR);		/* set initial state of output pins	*/
#endif
#if defined(CONFIG_SYS_GPIO0_ODR)
	out32(GPIO0_ODR, CONFIG_SYS_GPIO0_ODR);	/* open-drain select			*/
#endif
	out32(GPIO0_OSRH, CONFIG_SYS_GPIO0_OSRH);	/* output select			*/
	out32(GPIO0_OSRL, CONFIG_SYS_GPIO0_OSRL);
	out32(GPIO0_ISR1H, CONFIG_SYS_GPIO0_ISR1H);	/* input select				*/
	out32(GPIO0_ISR1L, CONFIG_SYS_GPIO0_ISR1L);
	out32(GPIO0_TSRH, CONFIG_SYS_GPIO0_TSRH);	/* three-state select			*/
	out32(GPIO0_TSRL, CONFIG_SYS_GPIO0_TSRL);
#if defined(CONFIG_SYS_GPIO0_ISR2H)
	out32(GPIO0_ISR2H, CONFIG_SYS_GPIO0_ISR2H);
	out32(GPIO0_ISR2L, CONFIG_SYS_GPIO0_ISR2L);
#endif
#if defined (CONFIG_SYS_GPIO0_TCR)
	out32(GPIO0_TCR, CONFIG_SYS_GPIO0_TCR);	/* enable output driver for outputs	*/
#endif
#endif /* CONFIG_405EP ... && !CONFIG_SYS_4xx_GPIO_TABLE */

#if defined (CONFIG_405EP)
	/*
	 * Set EMAC noise filter bits
	 */
	mtdcr(CPC0_EPCTL, CPC0_EPRCSR_E0NFE | CPC0_EPRCSR_E1NFE);
#endif /* CONFIG_405EP */

#if defined(CONFIG_SYS_4xx_GPIO_TABLE)
	gpio_set_chip_configuration();
#endif /* CONFIG_SYS_4xx_GPIO_TABLE */

	/*
	 * External Bus Controller (EBC) Setup
	 */
#if (defined(CONFIG_SYS_EBC_PB0AP) && defined(CONFIG_SYS_EBC_PB0CR))
#if (defined(CONFIG_405GP) || defined(CONFIG_405CR) || \
     defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \
     defined(CONFIG_405EX) || defined(CONFIG_405))
	/*
	 * Move the next instructions into icache, since these modify the flash
	 * we are running from!
	 */
	asm volatile("	bl	0f"		::: "lr");
	asm volatile("0:	mflr	3"		::: "r3");
	asm volatile("	addi	4, 0, 14"	::: "r4");
	asm volatile("	mtctr	4"		::: "ctr");
	asm volatile("1:	icbt	0, 3");
	asm volatile("	addi	3, 3, 32"	::: "r3");
	asm volatile("	bdnz	1b"		::: "ctr", "cr0");
	asm volatile("	addis	3, 0, 0x0"	::: "r3");
	asm volatile("	ori	3, 3, 0xA000"	::: "r3");
	asm volatile("	mtctr	3"		::: "ctr");
	asm volatile("2:	bdnz	2b"		::: "ctr", "cr0");
#endif

	mtebc(PB0AP, CONFIG_SYS_EBC_PB0AP);
	mtebc(PB0CR, CONFIG_SYS_EBC_PB0CR);
#endif

#if (defined(CONFIG_SYS_EBC_PB1AP) && defined(CONFIG_SYS_EBC_PB1CR) && !(CONFIG_SYS_INIT_DCACHE_CS == 1))
	mtebc(PB1AP, CONFIG_SYS_EBC_PB1AP);
	mtebc(PB1CR, CONFIG_SYS_EBC_PB1CR);
#endif

#if (defined(CONFIG_SYS_EBC_PB2AP) && defined(CONFIG_SYS_EBC_PB2CR) && !(CONFIG_SYS_INIT_DCACHE_CS == 2))
	mtebc(PB2AP, CONFIG_SYS_EBC_PB2AP);
	mtebc(PB2CR, CONFIG_SYS_EBC_PB2CR);
#endif

#if (defined(CONFIG_SYS_EBC_PB3AP) && defined(CONFIG_SYS_EBC_PB3CR) && !(CONFIG_SYS_INIT_DCACHE_CS == 3))
	mtebc(PB3AP, CONFIG_SYS_EBC_PB3AP);
	mtebc(PB3CR, CONFIG_SYS_EBC_PB3CR);
#endif

#if (defined(CONFIG_SYS_EBC_PB4AP) && defined(CONFIG_SYS_EBC_PB4CR) && !(CONFIG_SYS_INIT_DCACHE_CS == 4))
	mtebc(PB4AP, CONFIG_SYS_EBC_PB4AP);
	mtebc(PB4CR, CONFIG_SYS_EBC_PB4CR);
#endif

#if (defined(CONFIG_SYS_EBC_PB5AP) && defined(CONFIG_SYS_EBC_PB5CR) && !(CONFIG_SYS_INIT_DCACHE_CS == 5))
	mtebc(PB5AP, CONFIG_SYS_EBC_PB5AP);
	mtebc(PB5CR, CONFIG_SYS_EBC_PB5CR);
#endif

#if (defined(CONFIG_SYS_EBC_PB6AP) && defined(CONFIG_SYS_EBC_PB6CR) && !(CONFIG_SYS_INIT_DCACHE_CS == 6))
	mtebc(PB6AP, CONFIG_SYS_EBC_PB6AP);
	mtebc(PB6CR, CONFIG_SYS_EBC_PB6CR);
#endif

#if (defined(CONFIG_SYS_EBC_PB7AP) && defined(CONFIG_SYS_EBC_PB7CR) && !(CONFIG_SYS_INIT_DCACHE_CS == 7))
	mtebc(PB7AP, CONFIG_SYS_EBC_PB7AP);
	mtebc(PB7CR, CONFIG_SYS_EBC_PB7CR);
#endif

#if defined (CONFIG_SYS_EBC_CFG)
	mtebc(EBC0_CFG, CONFIG_SYS_EBC_CFG);
#endif

#if defined(CONFIG_WATCHDOG)
	val = mfspr(tcr);
#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
	val |= 0xb8000000;      /* generate system reset after 1.34 seconds */
#elif defined(CONFIG_440EPX)
	val |= 0xb0000000;      /* generate system reset after 1.34 seconds */
#else
	val |= 0xf0000000;      /* generate system reset after 2.684 seconds */
#endif
#if defined(CONFIG_SYS_4xx_RESET_TYPE)
	val &= ~0x30000000;			/* clear WRC bits */
	val |= CONFIG_SYS_4xx_RESET_TYPE << 28;	/* set board specific WRC type */
#endif
	mtspr(tcr, val);

	val = mfspr(tsr);
	val |= 0x80000000;      /* enable watchdog timer */
	mtspr(tsr, val);

	reset_4xx_watchdog();
#endif /* CONFIG_WATCHDOG */

#if defined(CONFIG_440GX)
	/* Take the GX out of compatibility mode
	 * Travis Sawyer, 9 Mar 2004
	 * NOTE: 440gx user manual inconsistency here
	 *       Compatibility mode and Ethernet Clock select are not
	 *       correct in the manual
	 */
	mfsdr(SDR0_MFR, val);
	val &= ~0x10000000;
	mtsdr(SDR0_MFR,val);
#endif /* CONFIG_440GX */

#if defined(CONFIG_460EX)
	/*
	 * Set SDR0_AHB_CFG[A2P_INCR4] (bit 24) and
	 * clear SDR0_AHB_CFG[A2P_PROT2] (bit 25) for a new 460EX errata
	 * regarding concurrent use of AHB USB OTG, USB 2.0 host and SATA
	 */
	mfsdr(SDR0_AHB_CFG, val);
	val |= 0x80;
	val &= ~0x40;
	mtsdr(SDR0_AHB_CFG, val);
	mfsdr(SDR0_USB2HOST_CFG, val);
	val &= ~0xf00;
	val |= 0x400;
	mtsdr(SDR0_USB2HOST_CFG, val);
#endif /* CONFIG_460EX */

#if defined(CONFIG_405EX) || \
    defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
    defined(CONFIG_460EX) || defined(CONFIG_460GT)  || \
    defined(CONFIG_460SX)
	/*
	 * Set PLB4 arbiter (Segment 0 and 1) to 4 deep pipeline read
	 */
	mtdcr(PLB0_ACR, (mfdcr(PLB0_ACR) & ~PLB0_ACR_RDP_MASK) |
	      PLB0_ACR_RDP_4DEEP);
	mtdcr(PLB1_ACR, (mfdcr(PLB1_ACR) & ~PLB1_ACR_RDP_MASK) |
	      PLB1_ACR_RDP_4DEEP);
#endif /* CONFIG_440SP/SPE || CONFIG_460EX/GT || CONFIG_405EX */
}

/*
 * initialize higher level parts of CPU like time base and timers
 */
int cpu_init_r (void)
{
#if defined(CONFIG_405GP)
	uint pvr = get_pvr();

	/*
	 * Set edge conditioning circuitry on PPC405GPr
	 * for compatibility to existing PPC405GP designs.
	 */
	if ((pvr & 0xfffffff0) == (PVR_405GPR_RB & 0xfffffff0)) {
		mtdcr(CPC0_ECR, 0x60606000);
	}
#endif  /* defined(CONFIG_405GP) */

	return 0;
}
Commit	Line	Data
4a9cbbe8	1	/*
dbbd1257	2	* (C) Copyright 2000-2007
4a9cbbe8 WD	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
	24	#include <common.h>
	25	#include <watchdog.h>
d6c61aab	26	#include <ppc4xx_enet.h>
4a9cbbe8	27	#include <asm/processor.h>
0d974d52	28	#include <asm/gpio.h>
4a9cbbe8 WD	29	#include <ppc4xx.h>
4a9cbbe8 WD	30
d87080b7 WD	31	#if defined(CONFIG_405GP) \|\| defined(CONFIG_405EP)
	32	DECLARE_GLOBAL_DATA_PTR;
	33	#endif
	34
6d0f6bcf JCPV	35	#ifndef CONFIG_SYS_PLL_RECONFIG
6d0f6bcf JCPV	36	#define CONFIG_SYS_PLL_RECONFIG 0
f66e2c8b MN	37	#endif
	38
	39	void reconfigure_pll(u32 new_cpu_freq)
	40	{
	41	#if defined(CONFIG_440EPX)
	42	int reset_needed = 0;
	43	u32 reg, temp;
	44	u32 prbdv0, target_prbdv0, /* CLK_PRIMBD */
	45	fwdva, target_fwdva, fwdvb, target_fwdvb, /* CLK_PLLD */
	46	fbdv, target_fbdv, lfbdv, target_lfbdv,
	47	perdv0, target_perdv0, /* CLK_PERD */
	48	spcid0, target_spcid0; /* CLK_SPCID */
	49
	50	/* Reconfigure clocks if necessary.
	51	* See PPC440EPx User's Manual, sections 8.2 and 14 */
	52	if (new_cpu_freq == 667) {
	53	target_prbdv0 = 2;
	54	target_fwdva = 2;
	55	target_fwdvb = 4;
	56	target_fbdv = 20;
	57	target_lfbdv = 1;
	58	target_perdv0 = 4;
	59	target_spcid0 = 4;
	60
ddc922ff	61	mfcpr(CPR0_PRIMBD0, reg);
f66e2c8b MN	62	temp = (reg & PRBDV_MASK) >> 24;
	63	prbdv0 = temp ? temp : 8;
	64	if (prbdv0 != target_prbdv0) {
	65	reg &= ~PRBDV_MASK;
	66	reg \|= ((target_prbdv0 == 8 ? 0 : target_prbdv0) << 24);
ddc922ff	67	mtcpr(CPR0_PRIMBD0, reg);
f66e2c8b MN	68	reset_needed = 1;
	69	}
	70
d1c3b275	71	mfcpr(CPR0_PLLD, reg);
f66e2c8b MN	72
	73	temp = (reg & PLLD_FWDVA_MASK) >> 16;
	74	fwdva = temp ? temp : 16;
	75
	76	temp = (reg & PLLD_FWDVB_MASK) >> 8;
	77	fwdvb = temp ? temp : 8;
	78
	79	temp = (reg & PLLD_FBDV_MASK) >> 24;
	80	fbdv = temp ? temp : 32;
	81
	82	temp = (reg & PLLD_LFBDV_MASK);
	83	lfbdv = temp ? temp : 64;
	84
	85	if (fwdva != target_fwdva \|\| fbdv != target_fbdv \|\| lfbdv != target_lfbdv) {
	86	reg &= ~(PLLD_FWDVA_MASK \| PLLD_FWDVB_MASK \|
	87	PLLD_FBDV_MASK \| PLLD_LFBDV_MASK);
	88	reg \|= ((target_fwdva == 16 ? 0 : target_fwdva) << 16) \|
	89	((target_fwdvb == 8 ? 0 : target_fwdvb) << 8) \|
	90	((target_fbdv == 32 ? 0 : target_fbdv) << 24) \|
	91	(target_lfbdv == 64 ? 0 : target_lfbdv);
d1c3b275	92	mtcpr(CPR0_PLLD, reg);
f66e2c8b MN	93	reset_needed = 1;
	94	}
	95
d1c3b275	96	mfcpr(CPR0_PERD, reg);
f66e2c8b MN	97	perdv0 = (reg & CPR0_PERD_PERDV0_MASK) >> 24;
	98	if (perdv0 != target_perdv0) {
	99	reg &= ~CPR0_PERD_PERDV0_MASK;
	100	reg \|= (target_perdv0 << 24);
d1c3b275	101	mtcpr(CPR0_PERD, reg);
f66e2c8b MN	102	reset_needed = 1;
	103	}
	104
d1c3b275	105	mfcpr(CPR0_SPCID, reg);
f66e2c8b MN	106	temp = (reg & CPR0_SPCID_SPCIDV0_MASK) >> 24;
	107	spcid0 = temp ? temp : 4;
	108	if (spcid0 != target_spcid0) {
	109	reg &= ~CPR0_SPCID_SPCIDV0_MASK;
	110	reg \|= ((target_spcid0 == 4 ? 0 : target_spcid0) << 24);
d1c3b275	111	mtcpr(CPR0_SPCID, reg);
f66e2c8b MN	112	reset_needed = 1;
	113	}
	114
	115	/* Set reload inhibit so configuration will persist across
	116	* processor resets */
d1c3b275	117	mfcpr(CPR0_ICFG, reg);
f66e2c8b MN	118	reg &= ~CPR0_ICFG_RLI_MASK;
f66e2c8b MN	119	reg \|= 1 << 31;
d1c3b275	120	mtcpr(CPR0_ICFG, reg);
f66e2c8b MN	121	}
	122
	123	/* Reset processor if configuration changed */
	124	if (reset_needed) {
	125	__asm__ __volatile__ ("sync; isync");
58ea142f	126	mtspr(SPRN_DBCR0, 0x20000000);
f66e2c8b MN	127	}
	128	#endif
	129	}
	130
4a9cbbe8 WD	131	/*
	132	* Breath some life into the CPU...
	133	*
f66e2c8b MN	134	* Reconfigure PLL if necessary,
f66e2c8b MN	135	* set up the memory map,
4a9cbbe8 WD	136	* initialize a bunch of registers
	137	*/
	138	void
	139	cpu_init_f (void)
	140	{
f5564837	141	#if defined(CONFIG_WATCHDOG) \|\| defined(CONFIG_440GX) \|\| defined(CONFIG_460EX)
745d8a0d	142	u32 val;
f11033e7	143	#endif
5de85140	144
6d0f6bcf	145	reconfigure_pll(CONFIG_SYS_PLL_RECONFIG);
f11033e7	146
6d0f6bcf	147	#if (defined(CONFIG_405EP) \|\| defined (CONFIG_405EX)) && !defined(CONFIG_SYS_4xx_GPIO_TABLE)
b867d705 SR	148	/*
	149	* GPIO0 setup (select GPIO or alternate function)
	150	*/
6d0f6bcf JCPV	151	#if defined(CONFIG_SYS_GPIO0_OR)
6d0f6bcf JCPV	152	out32(GPIO0_OR, CONFIG_SYS_GPIO0_OR); /* set initial state of output pins */
e0a46554	153	#endif
6d0f6bcf JCPV	154	#if defined(CONFIG_SYS_GPIO0_ODR)
6d0f6bcf JCPV	155	out32(GPIO0_ODR, CONFIG_SYS_GPIO0_ODR); /* open-drain select */
e0a46554	156	#endif
6d0f6bcf JCPV	157	out32(GPIO0_OSRH, CONFIG_SYS_GPIO0_OSRH); /* output select */
	158	out32(GPIO0_OSRL, CONFIG_SYS_GPIO0_OSRL);
	159	out32(GPIO0_ISR1H, CONFIG_SYS_GPIO0_ISR1H); /* input select */
	160	out32(GPIO0_ISR1L, CONFIG_SYS_GPIO0_ISR1L);
	161	out32(GPIO0_TSRH, CONFIG_SYS_GPIO0_TSRH); /* three-state select */
	162	out32(GPIO0_TSRL, CONFIG_SYS_GPIO0_TSRL);
	163	#if defined(CONFIG_SYS_GPIO0_ISR2H)
	164	out32(GPIO0_ISR2H, CONFIG_SYS_GPIO0_ISR2H);
	165	out32(GPIO0_ISR2L, CONFIG_SYS_GPIO0_ISR2L);
dbbd1257	166	#endif
6d0f6bcf JCPV	167	#if defined (CONFIG_SYS_GPIO0_TCR)
6d0f6bcf JCPV	168	out32(GPIO0_TCR, CONFIG_SYS_GPIO0_TCR); /* enable output driver for outputs */
dbbd1257	169	#endif
6d0f6bcf	170	#endif /* CONFIG_405EP ... && !CONFIG_SYS_4xx_GPIO_TABLE */
b867d705	171
bec92646	172	#if defined (CONFIG_405EP)
b867d705 SR	173	/*
	174	* Set EMAC noise filter bits
	175	*/
d1c3b275	176	mtdcr(CPC0_EPCTL, CPC0_EPRCSR_E0NFE \| CPC0_EPRCSR_E1NFE);
b867d705 SR	177	#endif /* CONFIG_405EP */
b867d705 SR	178
6d0f6bcf	179	#if defined(CONFIG_SYS_4xx_GPIO_TABLE)
0d974d52	180	gpio_set_chip_configuration();
6d0f6bcf	181	#endif /* CONFIG_SYS_4xx_GPIO_TABLE */
a4c8d138	182
4a9cbbe8 WD	183	/*
	184	* External Bus Controller (EBC) Setup
	185	*/
6d0f6bcf	186	#if (defined(CONFIG_SYS_EBC_PB0AP) && defined(CONFIG_SYS_EBC_PB0CR))
a4c8d138	187	#if (defined(CONFIG_405GP) \|\| defined(CONFIG_405CR) \|\| \
e01bd218	188	defined(CONFIG_405EP) \|\| defined(CONFIG_405EZ) \|\| \
dbbd1257	189	defined(CONFIG_405EX) \|\| defined(CONFIG_405))
4a9cbbe8 WD	190	/*
	191	* Move the next instructions into icache, since these modify the flash
	192	* we are running from!
	193	*/
	194	asm volatile(" bl 0f" ::: "lr");
	195	asm volatile("0: mflr 3" ::: "r3");
1636d1c8	196	asm volatile(" addi 4, 0, 14" ::: "r4");
4a9cbbe8 WD	197	asm volatile(" mtctr 4" ::: "ctr");
	198	asm volatile("1: icbt 0, 3");
	199	asm volatile(" addi 3, 3, 32" ::: "r3");
	200	asm volatile(" bdnz 1b" ::: "ctr", "cr0");
	201	asm volatile(" addis 3, 0, 0x0" ::: "r3");
	202	asm volatile(" ori 3, 3, 0xA000" ::: "r3");
	203	asm volatile(" mtctr 3" ::: "ctr");
	204	asm volatile("2: bdnz 2b" ::: "ctr", "cr0");
a4c8d138	205	#endif
4a9cbbe8	206
d1c3b275 SR	207	mtebc(PB0AP, CONFIG_SYS_EBC_PB0AP);
d1c3b275 SR	208	mtebc(PB0CR, CONFIG_SYS_EBC_PB0CR);
4a9cbbe8 WD	209	#endif
4a9cbbe8 WD	210
6d0f6bcf	211	#if (defined(CONFIG_SYS_EBC_PB1AP) && defined(CONFIG_SYS_EBC_PB1CR) && !(CONFIG_SYS_INIT_DCACHE_CS == 1))
d1c3b275 SR	212	mtebc(PB1AP, CONFIG_SYS_EBC_PB1AP);
d1c3b275 SR	213	mtebc(PB1CR, CONFIG_SYS_EBC_PB1CR);
4a9cbbe8 WD	214	#endif
4a9cbbe8 WD	215
6d0f6bcf	216	#if (defined(CONFIG_SYS_EBC_PB2AP) && defined(CONFIG_SYS_EBC_PB2CR) && !(CONFIG_SYS_INIT_DCACHE_CS == 2))
d1c3b275 SR	217	mtebc(PB2AP, CONFIG_SYS_EBC_PB2AP);
d1c3b275 SR	218	mtebc(PB2CR, CONFIG_SYS_EBC_PB2CR);
4a9cbbe8 WD	219	#endif
4a9cbbe8 WD	220
6d0f6bcf	221	#if (defined(CONFIG_SYS_EBC_PB3AP) && defined(CONFIG_SYS_EBC_PB3CR) && !(CONFIG_SYS_INIT_DCACHE_CS == 3))
d1c3b275 SR	222	mtebc(PB3AP, CONFIG_SYS_EBC_PB3AP);
d1c3b275 SR	223	mtebc(PB3CR, CONFIG_SYS_EBC_PB3CR);
4a9cbbe8 WD	224	#endif
4a9cbbe8 WD	225
6d0f6bcf	226	#if (defined(CONFIG_SYS_EBC_PB4AP) && defined(CONFIG_SYS_EBC_PB4CR) && !(CONFIG_SYS_INIT_DCACHE_CS == 4))
d1c3b275 SR	227	mtebc(PB4AP, CONFIG_SYS_EBC_PB4AP);
d1c3b275 SR	228	mtebc(PB4CR, CONFIG_SYS_EBC_PB4CR);
4a9cbbe8 WD	229	#endif
4a9cbbe8 WD	230
6d0f6bcf	231	#if (defined(CONFIG_SYS_EBC_PB5AP) && defined(CONFIG_SYS_EBC_PB5CR) && !(CONFIG_SYS_INIT_DCACHE_CS == 5))
d1c3b275 SR	232	mtebc(PB5AP, CONFIG_SYS_EBC_PB5AP);
d1c3b275 SR	233	mtebc(PB5CR, CONFIG_SYS_EBC_PB5CR);
4a9cbbe8 WD	234	#endif
4a9cbbe8 WD	235
6d0f6bcf	236	#if (defined(CONFIG_SYS_EBC_PB6AP) && defined(CONFIG_SYS_EBC_PB6CR) && !(CONFIG_SYS_INIT_DCACHE_CS == 6))
d1c3b275 SR	237	mtebc(PB6AP, CONFIG_SYS_EBC_PB6AP);
d1c3b275 SR	238	mtebc(PB6CR, CONFIG_SYS_EBC_PB6CR);
4a9cbbe8 WD	239	#endif
4a9cbbe8 WD	240
6d0f6bcf	241	#if (defined(CONFIG_SYS_EBC_PB7AP) && defined(CONFIG_SYS_EBC_PB7CR) && !(CONFIG_SYS_INIT_DCACHE_CS == 7))
d1c3b275 SR	242	mtebc(PB7AP, CONFIG_SYS_EBC_PB7AP);
d1c3b275 SR	243	mtebc(PB7CR, CONFIG_SYS_EBC_PB7CR);
4a9cbbe8 WD	244	#endif
4a9cbbe8 WD	245
6d0f6bcf JCPV	246	#if defined (CONFIG_SYS_EBC_CFG)
6d0f6bcf JCPV	247	mtebc(EBC0_CFG, CONFIG_SYS_EBC_CFG);
ca43ba18	248	#endif
4a9cbbe8	249
f11033e7	250	#if defined(CONFIG_WATCHDOG)
4a9cbbe8	251	val = mfspr(tcr);
846b0dd2	252	#if defined(CONFIG_440EP) \|\| defined(CONFIG_440GR)
c157d8e2	253	val \|= 0xb8000000; /* generate system reset after 1.34 seconds */
a11e0696 IL	254	#elif defined(CONFIG_440EPX)
a11e0696 IL	255	val \|= 0xb0000000; /* generate system reset after 1.34 seconds */
c157d8e2	256	#else
4a9cbbe8	257	val \|= 0xf0000000; /* generate system reset after 2.684 seconds */
1c2ce226	258	#endif
6d0f6bcf	259	#if defined(CONFIG_SYS_4xx_RESET_TYPE)
1c2ce226	260	val &= ~0x30000000; /* clear WRC bits */
6d0f6bcf	261	val \|= CONFIG_SYS_4xx_RESET_TYPE << 28; /* set board specific WRC type */
c157d8e2	262	#endif
4a9cbbe8 WD	263	mtspr(tcr, val);
	264
	265	val = mfspr(tsr);
	266	val \|= 0x80000000; /* enable watchdog timer */
	267	mtspr(tsr, val);
	268
	269	reset_4xx_watchdog();
	270	#endif /* CONFIG_WATCHDOG */
745d8a0d	271
5de85140 SR	272	#if defined(CONFIG_440GX)
	273	/* Take the GX out of compatibility mode
	274	* Travis Sawyer, 9 Mar 2004
	275	* NOTE: 440gx user manual inconsistency here
	276	* Compatibility mode and Ethernet Clock select are not
	277	* correct in the manual
	278	*/
d1c3b275	279	mfsdr(SDR0_MFR, val);
5de85140	280	val &= ~0x10000000;
d1c3b275	281	mtsdr(SDR0_MFR,val);
5de85140 SR	282	#endif /* CONFIG_440GX */
5de85140 SR	283
745d8a0d SR	284	#if defined(CONFIG_460EX)
	285	/*
	286	* Set SDR0_AHB_CFG[A2P_INCR4] (bit 24) and
	287	* clear SDR0_AHB_CFG[A2P_PROT2] (bit 25) for a new 460EX errata
	288	* regarding concurrent use of AHB USB OTG, USB 2.0 host and SATA
	289	*/
	290	mfsdr(SDR0_AHB_CFG, val);
	291	val \|= 0x80;
	292	val &= ~0x40;
	293	mtsdr(SDR0_AHB_CFG, val);
	294	mfsdr(SDR0_USB2HOST_CFG, val);
	295	val &= ~0xf00;
	296	val \|= 0x400;
	297	mtsdr(SDR0_USB2HOST_CFG, val);
	298	#endif /* CONFIG_460EX */
079589bc	299
f5564837 SR	300	#if defined(CONFIG_405EX) \|\| \
f5564837 SR	301	defined(CONFIG_440SP) \|\| defined(CONFIG_440SPE) \|\| \
079589bc	302	defined(CONFIG_460EX) \|\| defined(CONFIG_460GT) \|\| \
f5564837	303	defined(CONFIG_460SX)
079589bc PH	304	/*
	305	* Set PLB4 arbiter (Segment 0 and 1) to 4 deep pipeline read
	306	*/
d1c3b275 SR	307	mtdcr(PLB0_ACR, (mfdcr(PLB0_ACR) & ~PLB0_ACR_RDP_MASK) \|
	308	PLB0_ACR_RDP_4DEEP);
	309	mtdcr(PLB1_ACR, (mfdcr(PLB1_ACR) & ~PLB1_ACR_RDP_MASK) \|
	310	PLB1_ACR_RDP_4DEEP);
079589bc	311	#endif /* CONFIG_440SP/SPE \|\| CONFIG_460EX/GT \|\| CONFIG_405EX */
4a9cbbe8 WD	312	}
	313
	314	/*
	315	* initialize higher level parts of CPU like time base and timers
	316	*/
	317	int cpu_init_r (void)
	318	{
b867d705	319	#if defined(CONFIG_405GP)
38daa27d	320	uint pvr = get_pvr();
38daa27d SR	321
	322	/*
	323	* Set edge conditioning circuitry on PPC405GPr
	324	* for compatibility to existing PPC405GP designs.
	325	*/
baa3d528	326	if ((pvr & 0xfffffff0) == (PVR_405GPR_RB & 0xfffffff0)) {
d1c3b275	327	mtdcr(CPC0_ECR, 0x60606000);
38daa27d	328	}
b867d705	329	#endif /* defined(CONFIG_405GP) */
2801b2d2	330
9cd69016	331	return 0;
4a9cbbe8	332	}