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de941241 SG |
1 | /* |
2 | * (C) Copyright 2008 | |
3 | * Texas Instruments, <www.ti.com> | |
4 | * Sukumar Ghorai <s-ghorai@ti.com> | |
5 | * | |
6 | * See file CREDITS for list of people who contributed to this | |
7 | * project. | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or | |
10 | * modify it under the terms of the GNU General Public License as | |
11 | * published by the Free Software Foundation's version 2 of | |
12 | * the License. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
22 | * MA 02111-1307 USA | |
23 | */ | |
24 | ||
25 | #include <config.h> | |
26 | #include <common.h> | |
93bfd616 | 27 | #include <malloc.h> |
de941241 SG |
28 | #include <mmc.h> |
29 | #include <part.h> | |
30 | #include <i2c.h> | |
31 | #include <twl4030.h> | |
14fa2dd0 | 32 | #include <twl6030.h> |
cb199102 | 33 | #include <palmas.h> |
e874d5b0 | 34 | #include <asm/gpio.h> |
de941241 SG |
35 | #include <asm/io.h> |
36 | #include <asm/arch/mmc_host_def.h> | |
96e0e7b3 | 37 | #include <asm/arch/sys_proto.h> |
de941241 | 38 | |
ab769f22 PA |
39 | /* simplify defines to OMAP_HSMMC_USE_GPIO */ |
40 | #if (defined(CONFIG_OMAP_GPIO) && !defined(CONFIG_SPL_BUILD)) || \ | |
41 | (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_GPIO_SUPPORT)) | |
42 | #define OMAP_HSMMC_USE_GPIO | |
43 | #else | |
44 | #undef OMAP_HSMMC_USE_GPIO | |
45 | #endif | |
46 | ||
25c719e2 GI |
47 | /* common definitions for all OMAPs */ |
48 | #define SYSCTL_SRC (1 << 25) | |
49 | #define SYSCTL_SRD (1 << 26) | |
50 | ||
cc22b0c0 NK |
51 | struct omap_hsmmc_data { |
52 | struct hsmmc *base_addr; | |
93bfd616 | 53 | struct mmc_config cfg; |
ab769f22 | 54 | #ifdef OMAP_HSMMC_USE_GPIO |
e874d5b0 | 55 | int cd_gpio; |
e3913f56 | 56 | int wp_gpio; |
ab769f22 | 57 | #endif |
cc22b0c0 NK |
58 | }; |
59 | ||
eb9a28f6 NM |
60 | /* If we fail after 1 second wait, something is really bad */ |
61 | #define MAX_RETRY_MS 1000 | |
62 | ||
933efe64 S |
63 | static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size); |
64 | static int mmc_write_data(struct hsmmc *mmc_base, const char *buf, | |
65 | unsigned int siz); | |
14fa2dd0 | 66 | |
ab769f22 | 67 | #ifdef OMAP_HSMMC_USE_GPIO |
e874d5b0 NK |
68 | static int omap_mmc_setup_gpio_in(int gpio, const char *label) |
69 | { | |
70 | if (!gpio_is_valid(gpio)) | |
71 | return -1; | |
72 | ||
73 | if (gpio_request(gpio, label) < 0) | |
74 | return -1; | |
75 | ||
76 | if (gpio_direction_input(gpio) < 0) | |
77 | return -1; | |
78 | ||
79 | return gpio; | |
80 | } | |
e874d5b0 NK |
81 | #endif |
82 | ||
14fa2dd0 B |
83 | #if defined(CONFIG_OMAP44XX) && defined(CONFIG_TWL6030_POWER) |
84 | static void omap4_vmmc_pbias_config(struct mmc *mmc) | |
85 | { | |
86 | u32 value = 0; | |
14fa2dd0 | 87 | |
c43c8339 | 88 | value = readl((*ctrl)->control_pbiaslite); |
14fa2dd0 | 89 | value &= ~(MMC1_PBIASLITE_PWRDNZ | MMC1_PWRDNZ); |
c43c8339 | 90 | writel(value, (*ctrl)->control_pbiaslite); |
14fa2dd0 B |
91 | /* set VMMC to 3V */ |
92 | twl6030_power_mmc_init(); | |
c43c8339 | 93 | value = readl((*ctrl)->control_pbiaslite); |
14fa2dd0 | 94 | value |= MMC1_PBIASLITE_VMODE | MMC1_PBIASLITE_PWRDNZ | MMC1_PWRDNZ; |
c43c8339 | 95 | writel(value, (*ctrl)->control_pbiaslite); |
14fa2dd0 B |
96 | } |
97 | #endif | |
98 | ||
cb199102 | 99 | #if defined(CONFIG_OMAP54XX) && defined(CONFIG_PALMAS_POWER) |
dd23e59d B |
100 | static void omap5_pbias_config(struct mmc *mmc) |
101 | { | |
102 | u32 value = 0; | |
dd23e59d | 103 | |
c43c8339 | 104 | value = readl((*ctrl)->control_pbias); |
a5d439c2 B |
105 | value &= ~SDCARD_PWRDNZ; |
106 | writel(value, (*ctrl)->control_pbias); | |
107 | udelay(10); /* wait 10 us */ | |
108 | value &= ~SDCARD_BIAS_PWRDNZ; | |
c43c8339 | 109 | writel(value, (*ctrl)->control_pbias); |
dd23e59d | 110 | |
384bcae0 | 111 | palmas_mmc1_poweron_ldo(); |
dd23e59d | 112 | |
c43c8339 | 113 | value = readl((*ctrl)->control_pbias); |
a5d439c2 | 114 | value |= SDCARD_BIAS_PWRDNZ; |
c43c8339 | 115 | writel(value, (*ctrl)->control_pbias); |
a5d439c2 B |
116 | udelay(150); /* wait 150 us */ |
117 | value |= SDCARD_PWRDNZ; | |
118 | writel(value, (*ctrl)->control_pbias); | |
119 | udelay(150); /* wait 150 us */ | |
dd23e59d B |
120 | } |
121 | #endif | |
122 | ||
14fa2dd0 | 123 | unsigned char mmc_board_init(struct mmc *mmc) |
de941241 | 124 | { |
de941241 SG |
125 | #if defined(CONFIG_OMAP34XX) |
126 | t2_t *t2_base = (t2_t *)T2_BASE; | |
127 | struct prcm *prcm_base = (struct prcm *)PRCM_BASE; | |
b1e725f2 | 128 | u32 pbias_lite; |
de941241 | 129 | |
b1e725f2 GI |
130 | pbias_lite = readl(&t2_base->pbias_lite); |
131 | pbias_lite &= ~(PBIASLITEPWRDNZ1 | PBIASLITEPWRDNZ0); | |
132 | writel(pbias_lite, &t2_base->pbias_lite); | |
133 | #endif | |
134 | #if defined(CONFIG_TWL4030_POWER) | |
135 | twl4030_power_mmc_init(); | |
136 | mdelay(100); /* ramp-up delay from Linux code */ | |
137 | #endif | |
138 | #if defined(CONFIG_OMAP34XX) | |
139 | writel(pbias_lite | PBIASLITEPWRDNZ1 | | |
de941241 SG |
140 | PBIASSPEEDCTRL0 | PBIASLITEPWRDNZ0, |
141 | &t2_base->pbias_lite); | |
142 | ||
143 | writel(readl(&t2_base->devconf0) | MMCSDIO1ADPCLKISEL, | |
144 | &t2_base->devconf0); | |
145 | ||
146 | writel(readl(&t2_base->devconf1) | MMCSDIO2ADPCLKISEL, | |
147 | &t2_base->devconf1); | |
148 | ||
bbbc1ae9 | 149 | /* Change from default of 52MHz to 26MHz if necessary */ |
93bfd616 | 150 | if (!(mmc->cfg->host_caps & MMC_MODE_HS_52MHz)) |
bbbc1ae9 JS |
151 | writel(readl(&t2_base->ctl_prog_io1) & ~CTLPROGIO1SPEEDCTRL, |
152 | &t2_base->ctl_prog_io1); | |
153 | ||
de941241 SG |
154 | writel(readl(&prcm_base->fclken1_core) | |
155 | EN_MMC1 | EN_MMC2 | EN_MMC3, | |
156 | &prcm_base->fclken1_core); | |
157 | ||
158 | writel(readl(&prcm_base->iclken1_core) | | |
159 | EN_MMC1 | EN_MMC2 | EN_MMC3, | |
160 | &prcm_base->iclken1_core); | |
161 | #endif | |
162 | ||
14fa2dd0 B |
163 | #if defined(CONFIG_OMAP44XX) && defined(CONFIG_TWL6030_POWER) |
164 | /* PBIAS config needed for MMC1 only */ | |
165 | if (mmc->block_dev.dev == 0) | |
166 | omap4_vmmc_pbias_config(mmc); | |
167 | #endif | |
cb199102 | 168 | #if defined(CONFIG_OMAP54XX) && defined(CONFIG_PALMAS_POWER) |
dd23e59d B |
169 | if (mmc->block_dev.dev == 0) |
170 | omap5_pbias_config(mmc); | |
171 | #endif | |
de941241 SG |
172 | |
173 | return 0; | |
174 | } | |
175 | ||
933efe64 | 176 | void mmc_init_stream(struct hsmmc *mmc_base) |
de941241 | 177 | { |
eb9a28f6 | 178 | ulong start; |
de941241 SG |
179 | |
180 | writel(readl(&mmc_base->con) | INIT_INITSTREAM, &mmc_base->con); | |
181 | ||
182 | writel(MMC_CMD0, &mmc_base->cmd); | |
eb9a28f6 NM |
183 | start = get_timer(0); |
184 | while (!(readl(&mmc_base->stat) & CC_MASK)) { | |
185 | if (get_timer(0) - start > MAX_RETRY_MS) { | |
186 | printf("%s: timedout waiting for cc!\n", __func__); | |
187 | return; | |
188 | } | |
189 | } | |
de941241 SG |
190 | writel(CC_MASK, &mmc_base->stat) |
191 | ; | |
192 | writel(MMC_CMD0, &mmc_base->cmd) | |
193 | ; | |
eb9a28f6 NM |
194 | start = get_timer(0); |
195 | while (!(readl(&mmc_base->stat) & CC_MASK)) { | |
196 | if (get_timer(0) - start > MAX_RETRY_MS) { | |
197 | printf("%s: timedout waiting for cc2!\n", __func__); | |
198 | return; | |
199 | } | |
200 | } | |
de941241 SG |
201 | writel(readl(&mmc_base->con) & ~INIT_INITSTREAM, &mmc_base->con); |
202 | } | |
203 | ||
204 | ||
ab769f22 | 205 | static int omap_hsmmc_init_setup(struct mmc *mmc) |
de941241 | 206 | { |
cc22b0c0 | 207 | struct hsmmc *mmc_base; |
de941241 SG |
208 | unsigned int reg_val; |
209 | unsigned int dsor; | |
eb9a28f6 | 210 | ulong start; |
de941241 | 211 | |
cc22b0c0 | 212 | mmc_base = ((struct omap_hsmmc_data *)mmc->priv)->base_addr; |
14fa2dd0 | 213 | mmc_board_init(mmc); |
de941241 SG |
214 | |
215 | writel(readl(&mmc_base->sysconfig) | MMC_SOFTRESET, | |
216 | &mmc_base->sysconfig); | |
eb9a28f6 NM |
217 | start = get_timer(0); |
218 | while ((readl(&mmc_base->sysstatus) & RESETDONE) == 0) { | |
219 | if (get_timer(0) - start > MAX_RETRY_MS) { | |
220 | printf("%s: timedout waiting for cc2!\n", __func__); | |
221 | return TIMEOUT; | |
222 | } | |
223 | } | |
de941241 | 224 | writel(readl(&mmc_base->sysctl) | SOFTRESETALL, &mmc_base->sysctl); |
eb9a28f6 NM |
225 | start = get_timer(0); |
226 | while ((readl(&mmc_base->sysctl) & SOFTRESETALL) != 0x0) { | |
227 | if (get_timer(0) - start > MAX_RETRY_MS) { | |
228 | printf("%s: timedout waiting for softresetall!\n", | |
229 | __func__); | |
230 | return TIMEOUT; | |
231 | } | |
232 | } | |
de941241 SG |
233 | writel(DTW_1_BITMODE | SDBP_PWROFF | SDVS_3V0, &mmc_base->hctl); |
234 | writel(readl(&mmc_base->capa) | VS30_3V0SUP | VS18_1V8SUP, | |
235 | &mmc_base->capa); | |
236 | ||
237 | reg_val = readl(&mmc_base->con) & RESERVED_MASK; | |
238 | ||
239 | writel(CTPL_MMC_SD | reg_val | WPP_ACTIVEHIGH | CDP_ACTIVEHIGH | | |
240 | MIT_CTO | DW8_1_4BITMODE | MODE_FUNC | STR_BLOCK | | |
241 | HR_NOHOSTRESP | INIT_NOINIT | NOOPENDRAIN, &mmc_base->con); | |
242 | ||
243 | dsor = 240; | |
244 | mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK | CEN_MASK), | |
245 | (ICE_STOP | DTO_15THDTO | CEN_DISABLE)); | |
246 | mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK, | |
247 | (dsor << CLKD_OFFSET) | ICE_OSCILLATE); | |
eb9a28f6 NM |
248 | start = get_timer(0); |
249 | while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) { | |
250 | if (get_timer(0) - start > MAX_RETRY_MS) { | |
251 | printf("%s: timedout waiting for ics!\n", __func__); | |
252 | return TIMEOUT; | |
253 | } | |
254 | } | |
de941241 SG |
255 | writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl); |
256 | ||
257 | writel(readl(&mmc_base->hctl) | SDBP_PWRON, &mmc_base->hctl); | |
258 | ||
259 | writel(IE_BADA | IE_CERR | IE_DEB | IE_DCRC | IE_DTO | IE_CIE | | |
260 | IE_CEB | IE_CCRC | IE_CTO | IE_BRR | IE_BWR | IE_TC | IE_CC, | |
261 | &mmc_base->ie); | |
262 | ||
263 | mmc_init_stream(mmc_base); | |
264 | ||
265 | return 0; | |
266 | } | |
267 | ||
25c719e2 GI |
268 | /* |
269 | * MMC controller internal finite state machine reset | |
270 | * | |
271 | * Used to reset command or data internal state machines, using respectively | |
272 | * SRC or SRD bit of SYSCTL register | |
273 | */ | |
274 | static void mmc_reset_controller_fsm(struct hsmmc *mmc_base, u32 bit) | |
275 | { | |
276 | ulong start; | |
277 | ||
278 | mmc_reg_out(&mmc_base->sysctl, bit, bit); | |
279 | ||
61a6cc27 OT |
280 | /* |
281 | * CMD(DAT) lines reset procedures are slightly different | |
282 | * for OMAP3 and OMAP4(AM335x,OMAP5,DRA7xx). | |
283 | * According to OMAP3 TRM: | |
284 | * Set SRC(SRD) bit in MMCHS_SYSCTL register to 0x1 and wait until it | |
285 | * returns to 0x0. | |
286 | * According to OMAP4(AM335x,OMAP5,DRA7xx) TRMs, CMD(DATA) lines reset | |
287 | * procedure steps must be as follows: | |
288 | * 1. Initiate CMD(DAT) line reset by writing 0x1 to SRC(SRD) bit in | |
289 | * MMCHS_SYSCTL register (SD_SYSCTL for AM335x). | |
290 | * 2. Poll the SRC(SRD) bit until it is set to 0x1. | |
291 | * 3. Wait until the SRC (SRD) bit returns to 0x0 | |
292 | * (reset procedure is completed). | |
293 | */ | |
294 | #if defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) || \ | |
295 | defined(CONFIG_AM33XX) | |
296 | if (!(readl(&mmc_base->sysctl) & bit)) { | |
297 | start = get_timer(0); | |
298 | while (!(readl(&mmc_base->sysctl) & bit)) { | |
299 | if (get_timer(0) - start > MAX_RETRY_MS) | |
300 | return; | |
301 | } | |
302 | } | |
303 | #endif | |
25c719e2 GI |
304 | start = get_timer(0); |
305 | while ((readl(&mmc_base->sysctl) & bit) != 0) { | |
306 | if (get_timer(0) - start > MAX_RETRY_MS) { | |
307 | printf("%s: timedout waiting for sysctl %x to clear\n", | |
308 | __func__, bit); | |
309 | return; | |
310 | } | |
311 | } | |
312 | } | |
de941241 | 313 | |
ab769f22 | 314 | static int omap_hsmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, |
de941241 SG |
315 | struct mmc_data *data) |
316 | { | |
cc22b0c0 | 317 | struct hsmmc *mmc_base; |
de941241 | 318 | unsigned int flags, mmc_stat; |
eb9a28f6 | 319 | ulong start; |
de941241 | 320 | |
cc22b0c0 | 321 | mmc_base = ((struct omap_hsmmc_data *)mmc->priv)->base_addr; |
eb9a28f6 | 322 | start = get_timer(0); |
a7778f8f | 323 | while ((readl(&mmc_base->pstate) & (DATI_MASK | CMDI_MASK)) != 0) { |
eb9a28f6 | 324 | if (get_timer(0) - start > MAX_RETRY_MS) { |
a7778f8f TR |
325 | printf("%s: timedout waiting on cmd inhibit to clear\n", |
326 | __func__); | |
eb9a28f6 NM |
327 | return TIMEOUT; |
328 | } | |
329 | } | |
de941241 | 330 | writel(0xFFFFFFFF, &mmc_base->stat); |
eb9a28f6 NM |
331 | start = get_timer(0); |
332 | while (readl(&mmc_base->stat)) { | |
333 | if (get_timer(0) - start > MAX_RETRY_MS) { | |
15ceb1de GI |
334 | printf("%s: timedout waiting for STAT (%x) to clear\n", |
335 | __func__, readl(&mmc_base->stat)); | |
eb9a28f6 NM |
336 | return TIMEOUT; |
337 | } | |
338 | } | |
de941241 SG |
339 | /* |
340 | * CMDREG | |
341 | * CMDIDX[13:8] : Command index | |
342 | * DATAPRNT[5] : Data Present Select | |
343 | * ENCMDIDX[4] : Command Index Check Enable | |
344 | * ENCMDCRC[3] : Command CRC Check Enable | |
345 | * RSPTYP[1:0] | |
346 | * 00 = No Response | |
347 | * 01 = Length 136 | |
348 | * 10 = Length 48 | |
349 | * 11 = Length 48 Check busy after response | |
350 | */ | |
351 | /* Delay added before checking the status of frq change | |
352 | * retry not supported by mmc.c(core file) | |
353 | */ | |
354 | if (cmd->cmdidx == SD_CMD_APP_SEND_SCR) | |
355 | udelay(50000); /* wait 50 ms */ | |
356 | ||
357 | if (!(cmd->resp_type & MMC_RSP_PRESENT)) | |
358 | flags = 0; | |
359 | else if (cmd->resp_type & MMC_RSP_136) | |
360 | flags = RSP_TYPE_LGHT136 | CICE_NOCHECK; | |
361 | else if (cmd->resp_type & MMC_RSP_BUSY) | |
362 | flags = RSP_TYPE_LGHT48B; | |
363 | else | |
364 | flags = RSP_TYPE_LGHT48; | |
365 | ||
366 | /* enable default flags */ | |
367 | flags = flags | (CMD_TYPE_NORMAL | CICE_NOCHECK | CCCE_NOCHECK | | |
368 | MSBS_SGLEBLK | ACEN_DISABLE | BCE_DISABLE | DE_DISABLE); | |
369 | ||
370 | if (cmd->resp_type & MMC_RSP_CRC) | |
371 | flags |= CCCE_CHECK; | |
372 | if (cmd->resp_type & MMC_RSP_OPCODE) | |
373 | flags |= CICE_CHECK; | |
374 | ||
375 | if (data) { | |
376 | if ((cmd->cmdidx == MMC_CMD_READ_MULTIPLE_BLOCK) || | |
377 | (cmd->cmdidx == MMC_CMD_WRITE_MULTIPLE_BLOCK)) { | |
378 | flags |= (MSBS_MULTIBLK | BCE_ENABLE); | |
379 | data->blocksize = 512; | |
380 | writel(data->blocksize | (data->blocks << 16), | |
381 | &mmc_base->blk); | |
382 | } else | |
383 | writel(data->blocksize | NBLK_STPCNT, &mmc_base->blk); | |
384 | ||
385 | if (data->flags & MMC_DATA_READ) | |
386 | flags |= (DP_DATA | DDIR_READ); | |
387 | else | |
388 | flags |= (DP_DATA | DDIR_WRITE); | |
389 | } | |
390 | ||
391 | writel(cmd->cmdarg, &mmc_base->arg); | |
152ba363 | 392 | udelay(20); /* To fix "No status update" error on eMMC */ |
de941241 SG |
393 | writel((cmd->cmdidx << 24) | flags, &mmc_base->cmd); |
394 | ||
eb9a28f6 | 395 | start = get_timer(0); |
de941241 SG |
396 | do { |
397 | mmc_stat = readl(&mmc_base->stat); | |
eb9a28f6 NM |
398 | if (get_timer(0) - start > MAX_RETRY_MS) { |
399 | printf("%s : timeout: No status update\n", __func__); | |
400 | return TIMEOUT; | |
401 | } | |
402 | } while (!mmc_stat); | |
de941241 | 403 | |
25c719e2 GI |
404 | if ((mmc_stat & IE_CTO) != 0) { |
405 | mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC); | |
de941241 | 406 | return TIMEOUT; |
25c719e2 | 407 | } else if ((mmc_stat & ERRI_MASK) != 0) |
de941241 SG |
408 | return -1; |
409 | ||
410 | if (mmc_stat & CC_MASK) { | |
411 | writel(CC_MASK, &mmc_base->stat); | |
412 | if (cmd->resp_type & MMC_RSP_PRESENT) { | |
413 | if (cmd->resp_type & MMC_RSP_136) { | |
414 | /* response type 2 */ | |
415 | cmd->response[3] = readl(&mmc_base->rsp10); | |
416 | cmd->response[2] = readl(&mmc_base->rsp32); | |
417 | cmd->response[1] = readl(&mmc_base->rsp54); | |
418 | cmd->response[0] = readl(&mmc_base->rsp76); | |
419 | } else | |
420 | /* response types 1, 1b, 3, 4, 5, 6 */ | |
421 | cmd->response[0] = readl(&mmc_base->rsp10); | |
422 | } | |
423 | } | |
424 | ||
425 | if (data && (data->flags & MMC_DATA_READ)) { | |
426 | mmc_read_data(mmc_base, data->dest, | |
427 | data->blocksize * data->blocks); | |
428 | } else if (data && (data->flags & MMC_DATA_WRITE)) { | |
429 | mmc_write_data(mmc_base, data->src, | |
430 | data->blocksize * data->blocks); | |
431 | } | |
432 | return 0; | |
433 | } | |
434 | ||
933efe64 | 435 | static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size) |
de941241 SG |
436 | { |
437 | unsigned int *output_buf = (unsigned int *)buf; | |
438 | unsigned int mmc_stat; | |
439 | unsigned int count; | |
440 | ||
441 | /* | |
442 | * Start Polled Read | |
443 | */ | |
444 | count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size; | |
445 | count /= 4; | |
446 | ||
447 | while (size) { | |
eb9a28f6 | 448 | ulong start = get_timer(0); |
de941241 SG |
449 | do { |
450 | mmc_stat = readl(&mmc_base->stat); | |
eb9a28f6 NM |
451 | if (get_timer(0) - start > MAX_RETRY_MS) { |
452 | printf("%s: timedout waiting for status!\n", | |
453 | __func__); | |
454 | return TIMEOUT; | |
455 | } | |
de941241 SG |
456 | } while (mmc_stat == 0); |
457 | ||
25c719e2 GI |
458 | if ((mmc_stat & (IE_DTO | IE_DCRC | IE_DEB)) != 0) |
459 | mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD); | |
460 | ||
de941241 SG |
461 | if ((mmc_stat & ERRI_MASK) != 0) |
462 | return 1; | |
463 | ||
464 | if (mmc_stat & BRR_MASK) { | |
465 | unsigned int k; | |
466 | ||
467 | writel(readl(&mmc_base->stat) | BRR_MASK, | |
468 | &mmc_base->stat); | |
469 | for (k = 0; k < count; k++) { | |
470 | *output_buf = readl(&mmc_base->data); | |
471 | output_buf++; | |
472 | } | |
473 | size -= (count*4); | |
474 | } | |
475 | ||
476 | if (mmc_stat & BWR_MASK) | |
477 | writel(readl(&mmc_base->stat) | BWR_MASK, | |
478 | &mmc_base->stat); | |
479 | ||
480 | if (mmc_stat & TC_MASK) { | |
481 | writel(readl(&mmc_base->stat) | TC_MASK, | |
482 | &mmc_base->stat); | |
483 | break; | |
484 | } | |
485 | } | |
486 | return 0; | |
487 | } | |
488 | ||
933efe64 S |
489 | static int mmc_write_data(struct hsmmc *mmc_base, const char *buf, |
490 | unsigned int size) | |
de941241 SG |
491 | { |
492 | unsigned int *input_buf = (unsigned int *)buf; | |
493 | unsigned int mmc_stat; | |
494 | unsigned int count; | |
495 | ||
496 | /* | |
152ba363 | 497 | * Start Polled Write |
de941241 SG |
498 | */ |
499 | count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size; | |
500 | count /= 4; | |
501 | ||
502 | while (size) { | |
eb9a28f6 | 503 | ulong start = get_timer(0); |
de941241 SG |
504 | do { |
505 | mmc_stat = readl(&mmc_base->stat); | |
eb9a28f6 NM |
506 | if (get_timer(0) - start > MAX_RETRY_MS) { |
507 | printf("%s: timedout waiting for status!\n", | |
508 | __func__); | |
509 | return TIMEOUT; | |
510 | } | |
de941241 SG |
511 | } while (mmc_stat == 0); |
512 | ||
25c719e2 GI |
513 | if ((mmc_stat & (IE_DTO | IE_DCRC | IE_DEB)) != 0) |
514 | mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD); | |
515 | ||
de941241 SG |
516 | if ((mmc_stat & ERRI_MASK) != 0) |
517 | return 1; | |
518 | ||
519 | if (mmc_stat & BWR_MASK) { | |
520 | unsigned int k; | |
521 | ||
522 | writel(readl(&mmc_base->stat) | BWR_MASK, | |
523 | &mmc_base->stat); | |
524 | for (k = 0; k < count; k++) { | |
525 | writel(*input_buf, &mmc_base->data); | |
526 | input_buf++; | |
527 | } | |
528 | size -= (count*4); | |
529 | } | |
530 | ||
531 | if (mmc_stat & BRR_MASK) | |
532 | writel(readl(&mmc_base->stat) | BRR_MASK, | |
533 | &mmc_base->stat); | |
534 | ||
535 | if (mmc_stat & TC_MASK) { | |
536 | writel(readl(&mmc_base->stat) | TC_MASK, | |
537 | &mmc_base->stat); | |
538 | break; | |
539 | } | |
540 | } | |
541 | return 0; | |
542 | } | |
543 | ||
ab769f22 | 544 | static void omap_hsmmc_set_ios(struct mmc *mmc) |
de941241 | 545 | { |
cc22b0c0 | 546 | struct hsmmc *mmc_base; |
de941241 | 547 | unsigned int dsor = 0; |
eb9a28f6 | 548 | ulong start; |
de941241 | 549 | |
cc22b0c0 | 550 | mmc_base = ((struct omap_hsmmc_data *)mmc->priv)->base_addr; |
de941241 SG |
551 | /* configue bus width */ |
552 | switch (mmc->bus_width) { | |
553 | case 8: | |
554 | writel(readl(&mmc_base->con) | DTW_8_BITMODE, | |
555 | &mmc_base->con); | |
556 | break; | |
557 | ||
558 | case 4: | |
559 | writel(readl(&mmc_base->con) & ~DTW_8_BITMODE, | |
560 | &mmc_base->con); | |
561 | writel(readl(&mmc_base->hctl) | DTW_4_BITMODE, | |
562 | &mmc_base->hctl); | |
563 | break; | |
564 | ||
565 | case 1: | |
566 | default: | |
567 | writel(readl(&mmc_base->con) & ~DTW_8_BITMODE, | |
568 | &mmc_base->con); | |
569 | writel(readl(&mmc_base->hctl) & ~DTW_4_BITMODE, | |
570 | &mmc_base->hctl); | |
571 | break; | |
572 | } | |
573 | ||
574 | /* configure clock with 96Mhz system clock. | |
575 | */ | |
576 | if (mmc->clock != 0) { | |
577 | dsor = (MMC_CLOCK_REFERENCE * 1000000 / mmc->clock); | |
578 | if ((MMC_CLOCK_REFERENCE * 1000000) / dsor > mmc->clock) | |
579 | dsor++; | |
580 | } | |
581 | ||
582 | mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK | CEN_MASK), | |
583 | (ICE_STOP | DTO_15THDTO | CEN_DISABLE)); | |
584 | ||
585 | mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK, | |
586 | (dsor << CLKD_OFFSET) | ICE_OSCILLATE); | |
587 | ||
eb9a28f6 NM |
588 | start = get_timer(0); |
589 | while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) { | |
590 | if (get_timer(0) - start > MAX_RETRY_MS) { | |
591 | printf("%s: timedout waiting for ics!\n", __func__); | |
592 | return; | |
593 | } | |
594 | } | |
de941241 SG |
595 | writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl); |
596 | } | |
597 | ||
ab769f22 PA |
598 | #ifdef OMAP_HSMMC_USE_GPIO |
599 | static int omap_hsmmc_getcd(struct mmc *mmc) | |
600 | { | |
601 | struct omap_hsmmc_data *priv_data = mmc->priv; | |
602 | int cd_gpio; | |
603 | ||
604 | /* if no CD return as 1 */ | |
605 | cd_gpio = priv_data->cd_gpio; | |
606 | if (cd_gpio < 0) | |
607 | return 1; | |
608 | ||
609 | return gpio_get_value(cd_gpio); | |
610 | } | |
611 | ||
612 | static int omap_hsmmc_getwp(struct mmc *mmc) | |
613 | { | |
614 | struct omap_hsmmc_data *priv_data = mmc->priv; | |
615 | int wp_gpio; | |
616 | ||
617 | /* if no WP return as 0 */ | |
618 | wp_gpio = priv_data->wp_gpio; | |
619 | if (wp_gpio < 0) | |
620 | return 0; | |
621 | ||
622 | return gpio_get_value(wp_gpio); | |
623 | } | |
624 | #endif | |
625 | ||
626 | static const struct mmc_ops omap_hsmmc_ops = { | |
627 | .send_cmd = omap_hsmmc_send_cmd, | |
628 | .set_ios = omap_hsmmc_set_ios, | |
629 | .init = omap_hsmmc_init_setup, | |
630 | #ifdef OMAP_HSMMC_USE_GPIO | |
631 | .getcd = omap_hsmmc_getcd, | |
632 | .getwp = omap_hsmmc_getwp, | |
633 | #endif | |
634 | }; | |
635 | ||
e3913f56 NK |
636 | int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max, int cd_gpio, |
637 | int wp_gpio) | |
de941241 | 638 | { |
93bfd616 PA |
639 | struct mmc *mmc; |
640 | struct omap_hsmmc_data *priv_data; | |
641 | struct mmc_config *cfg; | |
642 | uint host_caps_val; | |
643 | ||
644 | priv_data = malloc(sizeof(*priv_data)); | |
645 | if (priv_data == NULL) | |
646 | return -1; | |
de941241 | 647 | |
93bfd616 PA |
648 | host_caps_val = MMC_MODE_4BIT | MMC_MODE_HS_52MHz | MMC_MODE_HS | |
649 | MMC_MODE_HC; | |
de941241 SG |
650 | |
651 | switch (dev_index) { | |
652 | case 0: | |
cc22b0c0 | 653 | priv_data->base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE; |
de941241 | 654 | break; |
1037d585 | 655 | #ifdef OMAP_HSMMC2_BASE |
de941241 | 656 | case 1: |
cc22b0c0 | 657 | priv_data->base_addr = (struct hsmmc *)OMAP_HSMMC2_BASE; |
152ba363 LP |
658 | #if (defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) || \ |
659 | defined(CONFIG_DRA7XX)) && defined(CONFIG_HSMMC2_8BIT) | |
660 | /* Enable 8-bit interface for eMMC on OMAP4/5 or DRA7XX */ | |
661 | host_caps_val |= MMC_MODE_8BIT; | |
662 | #endif | |
de941241 | 663 | break; |
1037d585 TR |
664 | #endif |
665 | #ifdef OMAP_HSMMC3_BASE | |
de941241 | 666 | case 2: |
cc22b0c0 | 667 | priv_data->base_addr = (struct hsmmc *)OMAP_HSMMC3_BASE; |
152ba363 LP |
668 | #if defined(CONFIG_DRA7XX) && defined(CONFIG_HSMMC3_8BIT) |
669 | /* Enable 8-bit interface for eMMC on DRA7XX */ | |
670 | host_caps_val |= MMC_MODE_8BIT; | |
671 | #endif | |
de941241 | 672 | break; |
1037d585 | 673 | #endif |
de941241 | 674 | default: |
cc22b0c0 | 675 | priv_data->base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE; |
de941241 SG |
676 | return 1; |
677 | } | |
ab769f22 PA |
678 | #ifdef OMAP_HSMMC_USE_GPIO |
679 | /* on error gpio values are set to -1, which is what we want */ | |
e874d5b0 | 680 | priv_data->cd_gpio = omap_mmc_setup_gpio_in(cd_gpio, "mmc_cd"); |
e3913f56 | 681 | priv_data->wp_gpio = omap_mmc_setup_gpio_in(wp_gpio, "mmc_wp"); |
ab769f22 | 682 | #endif |
173ddc5b | 683 | |
93bfd616 | 684 | cfg = &priv_data->cfg; |
de941241 | 685 | |
93bfd616 PA |
686 | cfg->name = "OMAP SD/MMC"; |
687 | cfg->ops = &omap_hsmmc_ops; | |
688 | ||
689 | cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195; | |
690 | cfg->host_caps = host_caps_val & ~host_caps_mask; | |
691 | ||
692 | cfg->f_min = 400000; | |
bbbc1ae9 JS |
693 | |
694 | if (f_max != 0) | |
93bfd616 | 695 | cfg->f_max = f_max; |
bbbc1ae9 | 696 | else { |
93bfd616 PA |
697 | if (cfg->host_caps & MMC_MODE_HS) { |
698 | if (cfg->host_caps & MMC_MODE_HS_52MHz) | |
699 | cfg->f_max = 52000000; | |
bbbc1ae9 | 700 | else |
93bfd616 | 701 | cfg->f_max = 26000000; |
bbbc1ae9 | 702 | } else |
93bfd616 | 703 | cfg->f_max = 20000000; |
bbbc1ae9 | 704 | } |
de941241 | 705 | |
93bfd616 | 706 | cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT; |
8feafcc4 | 707 | |
4ca9244d JR |
708 | #if defined(CONFIG_OMAP34XX) |
709 | /* | |
710 | * Silicon revs 2.1 and older do not support multiblock transfers. | |
711 | */ | |
712 | if ((get_cpu_family() == CPU_OMAP34XX) && (get_cpu_rev() <= CPU_3XX_ES21)) | |
93bfd616 | 713 | cfg->b_max = 1; |
4ca9244d | 714 | #endif |
93bfd616 PA |
715 | mmc = mmc_create(cfg, priv_data); |
716 | if (mmc == NULL) | |
717 | return -1; | |
de941241 SG |
718 | |
719 | return 0; | |
720 | } |