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Commit | Line | Data |
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3e326ece | 1 | /* |
4dae14ce ZW |
2 | * URB OHCI HCD (Host Controller Driver) for USB on the AT91RM9200 and PCI bus. |
3 | * | |
4 | * Interrupt support is added. Now, it has been tested | |
5 | * on ULI1575 chip and works well with USB keyboard. | |
6 | * | |
7 | * (C) Copyright 2007 | |
8 | * Zhang Wei, Freescale Semiconductor, Inc. <wei.zhang@freescale.com> | |
3e326ece MK |
9 | * |
10 | * (C) Copyright 2003 | |
792a09eb | 11 | * Gary Jennejohn, DENX Software Engineering <garyj@denx.de> |
3e326ece MK |
12 | * |
13 | * Note: Much of this code has been derived from Linux 2.4 | |
14 | * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at> | |
15 | * (C) Copyright 2000-2002 David Brownell | |
16 | * | |
17 | * Modified for the MP2USB by (C) Copyright 2005 Eric Benard | |
18 | * ebenard@eukrea.com - based on s3c24x0's driver | |
19 | * | |
1a459660 | 20 | * SPDX-License-Identifier: GPL-2.0+ |
3e326ece MK |
21 | */ |
22 | /* | |
23 | * IMPORTANT NOTES | |
fc43be47 | 24 | * 1 - Read doc/README.generic_usb_ohci |
3e326ece | 25 | * 2 - this driver is intended for use with USB Mass Storage Devices |
4dae14ce | 26 | * (BBB) and USB keyboard. There is NO support for Isochronous pipes! |
fc43be47 | 27 | * 2 - when running on a PQFP208 AT91RM9200, define CONFIG_AT91C_PQFP_UHPBUG |
3e326ece MK |
28 | * to activate workaround for bug #41 or this driver will NOT work! |
29 | */ | |
30 | ||
31 | #include <common.h> | |
fc43be47 MK |
32 | #include <asm/byteorder.h> |
33 | ||
34 | #if defined(CONFIG_PCI_OHCI) | |
4dae14ce | 35 | # include <pci.h> |
477434c6 SP |
36 | #if !defined(CONFIG_PCI_OHCI_DEVNO) |
37 | #define CONFIG_PCI_OHCI_DEVNO 0 | |
38 | #endif | |
ddf83a2f | 39 | #endif |
3e326ece MK |
40 | |
41 | #include <malloc.h> | |
42 | #include <usb.h> | |
2731b9a8 JCPV |
43 | |
44 | #include "ohci.h" | |
3e326ece | 45 | |
e8da58f2 WD |
46 | #ifdef CONFIG_AT91RM9200 |
47 | #include <asm/arch/hardware.h> /* needed for AT91_USB_HOST_BASE */ | |
48 | #endif | |
49 | ||
f2168440 | 50 | #if defined(CONFIG_CPU_ARM920T) || \ |
ac67804f | 51 | defined(CONFIG_S3C24X0) || \ |
ae3b770e | 52 | defined(CONFIG_440EP) || \ |
4dae14ce | 53 | defined(CONFIG_PCI_OHCI) || \ |
2596f5b9 | 54 | defined(CONFIG_MPC5200) || \ |
6d0f6bcf | 55 | defined(CONFIG_SYS_OHCI_USE_NPS) |
24e37645 MK |
56 | # define OHCI_USE_NPS /* force NoPowerSwitching mode */ |
57 | #endif | |
58 | ||
3e326ece | 59 | #undef OHCI_VERBOSE_DEBUG /* not always helpful */ |
ae3b770e MK |
60 | #undef DEBUG |
61 | #undef SHOW_INFO | |
62 | #undef OHCI_FILL_TRACE | |
3e326ece MK |
63 | |
64 | /* For initializing controller (mask in an HCFS mode too) */ | |
65 | #define OHCI_CONTROL_INIT \ | |
66 | (OHCI_CTRL_CBSR & 0x3) | OHCI_CTRL_IE | OHCI_CTRL_PLE | |
67 | ||
4dae14ce ZW |
68 | #ifdef CONFIG_PCI_OHCI |
69 | static struct pci_device_id ohci_pci_ids[] = { | |
70 | {0x10b9, 0x5237}, /* ULI1575 PCI OHCI module ids */ | |
97213f32 | 71 | {0x1033, 0x0035}, /* NEC PCI OHCI module ids */ |
3afac79e | 72 | {0x1131, 0x1561}, /* Philips 1561 PCI OHCI module ids */ |
4dae14ce ZW |
73 | /* Please add supported PCI OHCI controller ids here */ |
74 | {0, 0} | |
75 | }; | |
76 | #endif | |
77 | ||
e90fb6af YT |
78 | #ifdef CONFIG_PCI_EHCI_DEVNO |
79 | static struct pci_device_id ehci_pci_ids[] = { | |
80 | {0x1131, 0x1562}, /* Philips 1562 PCI EHCI module ids */ | |
81 | /* Please add supported PCI EHCI controller ids here */ | |
82 | {0, 0} | |
83 | }; | |
84 | #endif | |
85 | ||
3e326ece MK |
86 | #ifdef DEBUG |
87 | #define dbg(format, arg...) printf("DEBUG: " format "\n", ## arg) | |
88 | #else | |
6f5794a6 | 89 | #define dbg(format, arg...) do {} while (0) |
3e326ece MK |
90 | #endif /* DEBUG */ |
91 | #define err(format, arg...) printf("ERROR: " format "\n", ## arg) | |
3e326ece MK |
92 | #ifdef SHOW_INFO |
93 | #define info(format, arg...) printf("INFO: " format "\n", ## arg) | |
94 | #else | |
6f5794a6 | 95 | #define info(format, arg...) do {} while (0) |
3e326ece MK |
96 | #endif |
97 | ||
6d0f6bcf | 98 | #ifdef CONFIG_SYS_OHCI_BE_CONTROLLER |
fc43be47 MK |
99 | # define m16_swap(x) cpu_to_be16(x) |
100 | # define m32_swap(x) cpu_to_be32(x) | |
ae3b770e | 101 | #else |
fc43be47 MK |
102 | # define m16_swap(x) cpu_to_le16(x) |
103 | # define m32_swap(x) cpu_to_le32(x) | |
6d0f6bcf | 104 | #endif /* CONFIG_SYS_OHCI_BE_CONTROLLER */ |
3e326ece MK |
105 | |
106 | /* global ohci_t */ | |
107 | static ohci_t gohci; | |
108 | /* this must be aligned to a 256 byte boundary */ | |
109 | struct ohci_hcca ghcca[1]; | |
110 | /* a pointer to the aligned storage */ | |
111 | struct ohci_hcca *phcca; | |
112 | /* this allocates EDs for all possible endpoints */ | |
113 | struct ohci_device ohci_dev; | |
3e326ece | 114 | |
6f5794a6 | 115 | static inline u32 roothub_a(struct ohci *hc) |
a5496a18 | 116 | { return ohci_readl(&hc->regs->roothub.a); } |
6f5794a6 | 117 | static inline u32 roothub_b(struct ohci *hc) |
a5496a18 | 118 | { return ohci_readl(&hc->regs->roothub.b); } |
6f5794a6 | 119 | static inline u32 roothub_status(struct ohci *hc) |
a5496a18 | 120 | { return ohci_readl(&hc->regs->roothub.status); } |
6f5794a6 | 121 | static inline u32 roothub_portstatus(struct ohci *hc, int i) |
a5496a18 | 122 | { return ohci_readl(&hc->regs->roothub.portstatus[i]); } |
3e326ece | 123 | |
3e326ece | 124 | /* forward declaration */ |
c5613df5 HG |
125 | static int hc_interrupt(ohci_t *ohci); |
126 | static void td_submit_job(ohci_t *ohci, struct usb_device *dev, | |
127 | unsigned long pipe, void *buffer, int transfer_len, | |
6f5794a6 RB |
128 | struct devrequest *setup, urb_priv_t *urb, |
129 | int interval); | |
3e326ece MK |
130 | |
131 | /*-------------------------------------------------------------------------* | |
132 | * URB support functions | |
133 | *-------------------------------------------------------------------------*/ | |
134 | ||
135 | /* free HCD-private data associated with this URB */ | |
136 | ||
6f5794a6 | 137 | static void urb_free_priv(urb_priv_t *urb) |
3e326ece MK |
138 | { |
139 | int i; | |
140 | int last; | |
6f5794a6 | 141 | struct td *td; |
3e326ece MK |
142 | |
143 | last = urb->length - 1; | |
144 | if (last >= 0) { | |
145 | for (i = 0; i <= last; i++) { | |
146 | td = urb->td[i]; | |
147 | if (td) { | |
148 | td->usb_dev = NULL; | |
149 | urb->td[i] = NULL; | |
150 | } | |
151 | } | |
152 | } | |
4dae14ce | 153 | free(urb); |
3e326ece MK |
154 | } |
155 | ||
156 | /*-------------------------------------------------------------------------*/ | |
157 | ||
158 | #ifdef DEBUG | |
c5613df5 | 159 | static int sohci_get_current_frame_number(ohci_t *ohci); |
3e326ece MK |
160 | |
161 | /* debug| print the main components of an URB | |
162 | * small: 0) header + data packets 1) just header */ | |
163 | ||
c5613df5 | 164 | static void pkt_print(ohci_t *ohci, urb_priv_t *purb, struct usb_device *dev, |
6f5794a6 RB |
165 | unsigned long pipe, void *buffer, int transfer_len, |
166 | struct devrequest *setup, char *str, int small) | |
3e326ece | 167 | { |
6f5794a6 | 168 | dbg("%s URB:[%4x] dev:%2lu,ep:%2lu-%c,type:%s,len:%d/%d stat:%#lx", |
3e326ece | 169 | str, |
c5613df5 | 170 | sohci_get_current_frame_number(ohci), |
6f5794a6 RB |
171 | usb_pipedevice(pipe), |
172 | usb_pipeendpoint(pipe), | |
173 | usb_pipeout(pipe)? 'O': 'I', | |
174 | usb_pipetype(pipe) < 2 ? \ | |
175 | (usb_pipeint(pipe)? "INTR": "ISOC"): \ | |
176 | (usb_pipecontrol(pipe)? "CTRL": "BULK"), | |
4dae14ce | 177 | (purb ? purb->actual_length : 0), |
3e326ece MK |
178 | transfer_len, dev->status); |
179 | #ifdef OHCI_VERBOSE_DEBUG | |
180 | if (!small) { | |
181 | int i, len; | |
182 | ||
6f5794a6 RB |
183 | if (usb_pipecontrol(pipe)) { |
184 | printf(__FILE__ ": cmd(8):"); | |
3e326ece | 185 | for (i = 0; i < 8 ; i++) |
6f5794a6 RB |
186 | printf(" %02x", ((__u8 *) setup) [i]); |
187 | printf("\n"); | |
3e326ece MK |
188 | } |
189 | if (transfer_len > 0 && buffer) { | |
6f5794a6 | 190 | printf(__FILE__ ": data(%d/%d):", |
4dae14ce | 191 | (purb ? purb->actual_length : 0), |
3e326ece | 192 | transfer_len); |
6f5794a6 | 193 | len = usb_pipeout(pipe)? transfer_len: |
4dae14ce | 194 | (purb ? purb->actual_length : 0); |
3e326ece | 195 | for (i = 0; i < 16 && i < len; i++) |
6f5794a6 RB |
196 | printf(" %02x", ((__u8 *) buffer) [i]); |
197 | printf("%s\n", i < len? "...": ""); | |
3e326ece MK |
198 | } |
199 | } | |
200 | #endif | |
201 | } | |
202 | ||
6f5794a6 RB |
203 | /* just for debugging; prints non-empty branches of the int ed tree |
204 | * inclusive iso eds */ | |
205 | void ep_print_int_eds(ohci_t *ohci, char *str) | |
206 | { | |
3e326ece | 207 | int i, j; |
6f5794a6 RB |
208 | __u32 *ed_p; |
209 | for (i = 0; i < 32; i++) { | |
3e326ece MK |
210 | j = 5; |
211 | ed_p = &(ohci->hcca->int_table [i]); | |
212 | if (*ed_p == 0) | |
213 | continue; | |
6f5794a6 | 214 | printf(__FILE__ ": %s branch int %2d(%2x):", str, i, i); |
3e326ece MK |
215 | while (*ed_p != 0 && j--) { |
216 | ed_t *ed = (ed_t *)m32_swap(ed_p); | |
6f5794a6 | 217 | printf(" ed: %4x;", ed->hwINFO); |
3e326ece MK |
218 | ed_p = &ed->hwNextED; |
219 | } | |
6f5794a6 | 220 | printf("\n"); |
3e326ece MK |
221 | } |
222 | } | |
223 | ||
6f5794a6 | 224 | static void ohci_dump_intr_mask(char *label, __u32 mask) |
3e326ece | 225 | { |
6f5794a6 | 226 | dbg("%s: 0x%08x%s%s%s%s%s%s%s%s%s", |
3e326ece MK |
227 | label, |
228 | mask, | |
229 | (mask & OHCI_INTR_MIE) ? " MIE" : "", | |
230 | (mask & OHCI_INTR_OC) ? " OC" : "", | |
231 | (mask & OHCI_INTR_RHSC) ? " RHSC" : "", | |
232 | (mask & OHCI_INTR_FNO) ? " FNO" : "", | |
233 | (mask & OHCI_INTR_UE) ? " UE" : "", | |
234 | (mask & OHCI_INTR_RD) ? " RD" : "", | |
235 | (mask & OHCI_INTR_SF) ? " SF" : "", | |
236 | (mask & OHCI_INTR_WDH) ? " WDH" : "", | |
237 | (mask & OHCI_INTR_SO) ? " SO" : "" | |
238 | ); | |
239 | } | |
240 | ||
6f5794a6 | 241 | static void maybe_print_eds(char *label, __u32 value) |
3e326ece MK |
242 | { |
243 | ed_t *edp = (ed_t *)value; | |
244 | ||
245 | if (value) { | |
6f5794a6 RB |
246 | dbg("%s %08x", label, value); |
247 | dbg("%08x", edp->hwINFO); | |
248 | dbg("%08x", edp->hwTailP); | |
249 | dbg("%08x", edp->hwHeadP); | |
250 | dbg("%08x", edp->hwNextED); | |
3e326ece MK |
251 | } |
252 | } | |
253 | ||
6f5794a6 | 254 | static char *hcfs2string(int state) |
3e326ece MK |
255 | { |
256 | switch (state) { | |
6f5794a6 RB |
257 | case OHCI_USB_RESET: return "reset"; |
258 | case OHCI_USB_RESUME: return "resume"; | |
259 | case OHCI_USB_OPER: return "operational"; | |
260 | case OHCI_USB_SUSPEND: return "suspend"; | |
3e326ece MK |
261 | } |
262 | return "?"; | |
263 | } | |
264 | ||
265 | /* dump control and status registers */ | |
6f5794a6 | 266 | static void ohci_dump_status(ohci_t *controller) |
3e326ece MK |
267 | { |
268 | struct ohci_regs *regs = controller->regs; | |
269 | __u32 temp; | |
270 | ||
a5496a18 | 271 | temp = ohci_readl(®s->revision) & 0xff; |
3e326ece | 272 | if (temp != 0x10) |
6f5794a6 | 273 | dbg("spec %d.%d", (temp >> 4), (temp & 0x0f)); |
3e326ece | 274 | |
a5496a18 | 275 | temp = ohci_readl(®s->control); |
6f5794a6 | 276 | dbg("control: 0x%08x%s%s%s HCFS=%s%s%s%s%s CBSR=%d", temp, |
3e326ece MK |
277 | (temp & OHCI_CTRL_RWE) ? " RWE" : "", |
278 | (temp & OHCI_CTRL_RWC) ? " RWC" : "", | |
279 | (temp & OHCI_CTRL_IR) ? " IR" : "", | |
6f5794a6 | 280 | hcfs2string(temp & OHCI_CTRL_HCFS), |
3e326ece MK |
281 | (temp & OHCI_CTRL_BLE) ? " BLE" : "", |
282 | (temp & OHCI_CTRL_CLE) ? " CLE" : "", | |
283 | (temp & OHCI_CTRL_IE) ? " IE" : "", | |
284 | (temp & OHCI_CTRL_PLE) ? " PLE" : "", | |
285 | temp & OHCI_CTRL_CBSR | |
286 | ); | |
287 | ||
a5496a18 | 288 | temp = ohci_readl(®s->cmdstatus); |
6f5794a6 | 289 | dbg("cmdstatus: 0x%08x SOC=%d%s%s%s%s", temp, |
3e326ece MK |
290 | (temp & OHCI_SOC) >> 16, |
291 | (temp & OHCI_OCR) ? " OCR" : "", | |
292 | (temp & OHCI_BLF) ? " BLF" : "", | |
293 | (temp & OHCI_CLF) ? " CLF" : "", | |
294 | (temp & OHCI_HCR) ? " HCR" : "" | |
295 | ); | |
296 | ||
a5496a18 BB |
297 | ohci_dump_intr_mask("intrstatus", ohci_readl(®s->intrstatus)); |
298 | ohci_dump_intr_mask("intrenable", ohci_readl(®s->intrenable)); | |
3e326ece | 299 | |
a5496a18 BB |
300 | maybe_print_eds("ed_periodcurrent", |
301 | ohci_readl(®s->ed_periodcurrent)); | |
3e326ece | 302 | |
a5496a18 BB |
303 | maybe_print_eds("ed_controlhead", ohci_readl(®s->ed_controlhead)); |
304 | maybe_print_eds("ed_controlcurrent", | |
305 | ohci_readl(®s->ed_controlcurrent)); | |
3e326ece | 306 | |
a5496a18 BB |
307 | maybe_print_eds("ed_bulkhead", ohci_readl(®s->ed_bulkhead)); |
308 | maybe_print_eds("ed_bulkcurrent", ohci_readl(®s->ed_bulkcurrent)); | |
3e326ece | 309 | |
a5496a18 | 310 | maybe_print_eds("donehead", ohci_readl(®s->donehead)); |
3e326ece MK |
311 | } |
312 | ||
6f5794a6 | 313 | static void ohci_dump_roothub(ohci_t *controller, int verbose) |
3e326ece MK |
314 | { |
315 | __u32 temp, ndp, i; | |
316 | ||
6f5794a6 | 317 | temp = roothub_a(controller); |
3e326ece MK |
318 | ndp = (temp & RH_A_NDP); |
319 | #ifdef CONFIG_AT91C_PQFP_UHPBUG | |
320 | ndp = (ndp == 2) ? 1:0; | |
3e326ece MK |
321 | #endif |
322 | if (verbose) { | |
6f5794a6 | 323 | dbg("roothub.a: %08x POTPGT=%d%s%s%s%s%s NDP=%d", temp, |
3e326ece MK |
324 | ((temp & RH_A_POTPGT) >> 24) & 0xff, |
325 | (temp & RH_A_NOCP) ? " NOCP" : "", | |
326 | (temp & RH_A_OCPM) ? " OCPM" : "", | |
327 | (temp & RH_A_DT) ? " DT" : "", | |
328 | (temp & RH_A_NPS) ? " NPS" : "", | |
329 | (temp & RH_A_PSM) ? " PSM" : "", | |
330 | ndp | |
331 | ); | |
6f5794a6 RB |
332 | temp = roothub_b(controller); |
333 | dbg("roothub.b: %08x PPCM=%04x DR=%04x", | |
3e326ece MK |
334 | temp, |
335 | (temp & RH_B_PPCM) >> 16, | |
336 | (temp & RH_B_DR) | |
337 | ); | |
6f5794a6 RB |
338 | temp = roothub_status(controller); |
339 | dbg("roothub.status: %08x%s%s%s%s%s%s", | |
3e326ece MK |
340 | temp, |
341 | (temp & RH_HS_CRWE) ? " CRWE" : "", | |
342 | (temp & RH_HS_OCIC) ? " OCIC" : "", | |
343 | (temp & RH_HS_LPSC) ? " LPSC" : "", | |
344 | (temp & RH_HS_DRWE) ? " DRWE" : "", | |
345 | (temp & RH_HS_OCI) ? " OCI" : "", | |
346 | (temp & RH_HS_LPS) ? " LPS" : "" | |
347 | ); | |
348 | } | |
349 | ||
350 | for (i = 0; i < ndp; i++) { | |
6f5794a6 RB |
351 | temp = roothub_portstatus(controller, i); |
352 | dbg("roothub.portstatus [%d] = 0x%08x%s%s%s%s%s%s%s%s%s%s%s%s", | |
3e326ece MK |
353 | i, |
354 | temp, | |
355 | (temp & RH_PS_PRSC) ? " PRSC" : "", | |
356 | (temp & RH_PS_OCIC) ? " OCIC" : "", | |
357 | (temp & RH_PS_PSSC) ? " PSSC" : "", | |
358 | (temp & RH_PS_PESC) ? " PESC" : "", | |
359 | (temp & RH_PS_CSC) ? " CSC" : "", | |
360 | ||
361 | (temp & RH_PS_LSDA) ? " LSDA" : "", | |
362 | (temp & RH_PS_PPS) ? " PPS" : "", | |
363 | (temp & RH_PS_PRS) ? " PRS" : "", | |
364 | (temp & RH_PS_POCI) ? " POCI" : "", | |
365 | (temp & RH_PS_PSS) ? " PSS" : "", | |
366 | ||
367 | (temp & RH_PS_PES) ? " PES" : "", | |
368 | (temp & RH_PS_CCS) ? " CCS" : "" | |
369 | ); | |
370 | } | |
371 | } | |
372 | ||
6f5794a6 | 373 | static void ohci_dump(ohci_t *controller, int verbose) |
3e326ece | 374 | { |
6f5794a6 | 375 | dbg("OHCI controller usb-%s state", controller->slot_name); |
3e326ece MK |
376 | |
377 | /* dumps some of the state we know about */ | |
6f5794a6 | 378 | ohci_dump_status(controller); |
3e326ece | 379 | if (verbose) |
6f5794a6 RB |
380 | ep_print_int_eds(controller, "hcca"); |
381 | dbg("hcca frame #%04x", controller->hcca->frame_no); | |
382 | ohci_dump_roothub(controller, 1); | |
2596f5b9 | 383 | } |
3e326ece MK |
384 | #endif /* DEBUG */ |
385 | ||
386 | /*-------------------------------------------------------------------------* | |
387 | * Interface functions (URB) | |
388 | *-------------------------------------------------------------------------*/ | |
389 | ||
390 | /* get a transfer request */ | |
391 | ||
c5613df5 | 392 | int sohci_submit_job(ohci_t *ohci, urb_priv_t *urb, struct devrequest *setup) |
3e326ece | 393 | { |
6f5794a6 | 394 | ed_t *ed; |
4dae14ce | 395 | urb_priv_t *purb_priv = urb; |
3e326ece | 396 | int i, size = 0; |
4dae14ce ZW |
397 | struct usb_device *dev = urb->dev; |
398 | unsigned long pipe = urb->pipe; | |
399 | void *buffer = urb->transfer_buffer; | |
400 | int transfer_len = urb->transfer_buffer_length; | |
401 | int interval = urb->interval; | |
3e326ece | 402 | |
3e326ece MK |
403 | /* when controller's hung, permit only roothub cleanup attempts |
404 | * such as powering down ports */ | |
405 | if (ohci->disabled) { | |
406 | err("sohci_submit_job: EPIPE"); | |
407 | return -1; | |
408 | } | |
ae79f606 | 409 | |
6f5794a6 RB |
410 | /* we're about to begin a new transaction here so mark the |
411 | * URB unfinished */ | |
4dae14ce | 412 | urb->finished = 0; |
3e326ece MK |
413 | |
414 | /* every endpoint has a ed, locate and fill it */ | |
6f5794a6 RB |
415 | ed = ep_add_ed(dev, pipe, interval, 1); |
416 | if (!ed) { | |
3e326ece MK |
417 | err("sohci_submit_job: ENOMEM"); |
418 | return -1; | |
419 | } | |
420 | ||
421 | /* for the private part of the URB we need the number of TDs (size) */ | |
6f5794a6 RB |
422 | switch (usb_pipetype(pipe)) { |
423 | case PIPE_BULK: /* one TD for every 4096 Byte */ | |
424 | size = (transfer_len - 1) / 4096 + 1; | |
425 | break; | |
426 | case PIPE_CONTROL:/* 1 TD for setup, 1 for ACK and 1 for every 4096 B */ | |
427 | size = (transfer_len == 0)? 2: | |
428 | (transfer_len - 1) / 4096 + 3; | |
429 | break; | |
430 | case PIPE_INTERRUPT: /* 1 TD */ | |
431 | size = 1; | |
432 | break; | |
3e326ece MK |
433 | } |
434 | ||
4dae14ce ZW |
435 | ed->purb = urb; |
436 | ||
3e326ece MK |
437 | if (size >= (N_URB_TD - 1)) { |
438 | err("need %d TDs, only have %d", size, N_URB_TD); | |
439 | return -1; | |
440 | } | |
3e326ece MK |
441 | purb_priv->pipe = pipe; |
442 | ||
443 | /* fill the private part of the URB */ | |
444 | purb_priv->length = size; | |
445 | purb_priv->ed = ed; | |
446 | purb_priv->actual_length = 0; | |
447 | ||
448 | /* allocate the TDs */ | |
449 | /* note that td[0] was allocated in ep_add_ed */ | |
450 | for (i = 0; i < size; i++) { | |
6f5794a6 | 451 | purb_priv->td[i] = td_alloc(dev); |
3e326ece MK |
452 | if (!purb_priv->td[i]) { |
453 | purb_priv->length = i; | |
6f5794a6 | 454 | urb_free_priv(purb_priv); |
3e326ece MK |
455 | err("sohci_submit_job: ENOMEM"); |
456 | return -1; | |
457 | } | |
458 | } | |
459 | ||
460 | if (ed->state == ED_NEW || (ed->state & ED_DEL)) { | |
6f5794a6 | 461 | urb_free_priv(purb_priv); |
3e326ece MK |
462 | err("sohci_submit_job: EINVAL"); |
463 | return -1; | |
464 | } | |
465 | ||
466 | /* link the ed into a chain if is not already */ | |
467 | if (ed->state != ED_OPER) | |
6f5794a6 | 468 | ep_link(ohci, ed); |
3e326ece MK |
469 | |
470 | /* fill the TDs and link it to the ed */ | |
c5613df5 | 471 | td_submit_job(ohci, dev, pipe, buffer, transfer_len, |
6f5794a6 | 472 | setup, purb_priv, interval); |
3e326ece MK |
473 | |
474 | return 0; | |
475 | } | |
476 | ||
4dae14ce ZW |
477 | static inline int sohci_return_job(struct ohci *hc, urb_priv_t *urb) |
478 | { | |
479 | struct ohci_regs *regs = hc->regs; | |
480 | ||
6f5794a6 | 481 | switch (usb_pipetype(urb->pipe)) { |
4dae14ce ZW |
482 | case PIPE_INTERRUPT: |
483 | /* implicitly requeued */ | |
484 | if (urb->dev->irq_handle && | |
485 | (urb->dev->irq_act_len = urb->actual_length)) { | |
a5496a18 BB |
486 | ohci_writel(OHCI_INTR_WDH, ®s->intrenable); |
487 | ohci_readl(®s->intrenable); /* PCI posting flush */ | |
4dae14ce | 488 | urb->dev->irq_handle(urb->dev); |
a5496a18 BB |
489 | ohci_writel(OHCI_INTR_WDH, ®s->intrdisable); |
490 | ohci_readl(®s->intrdisable); /* PCI posting flush */ | |
4dae14ce ZW |
491 | } |
492 | urb->actual_length = 0; | |
c5613df5 | 493 | td_submit_job( hc, |
4dae14ce ZW |
494 | urb->dev, |
495 | urb->pipe, | |
496 | urb->transfer_buffer, | |
497 | urb->transfer_buffer_length, | |
498 | NULL, | |
499 | urb, | |
500 | urb->interval); | |
501 | break; | |
502 | case PIPE_CONTROL: | |
503 | case PIPE_BULK: | |
504 | break; | |
505 | default: | |
506 | return 0; | |
507 | } | |
508 | return 1; | |
509 | } | |
510 | ||
3e326ece MK |
511 | /*-------------------------------------------------------------------------*/ |
512 | ||
513 | #ifdef DEBUG | |
514 | /* tell us the current USB frame number */ | |
c5613df5 | 515 | static int sohci_get_current_frame_number(ohci_t *ohci) |
3e326ece | 516 | { |
6f5794a6 | 517 | return m16_swap(ohci->hcca->frame_no); |
3e326ece MK |
518 | } |
519 | #endif | |
520 | ||
4dae14ce ZW |
521 | /*-------------------------------------------------------------------------* |
522 | * ED handling functions | |
523 | *-------------------------------------------------------------------------*/ | |
524 | ||
525 | /* search for the right branch to insert an interrupt ed into the int tree | |
526 | * do some load ballancing; | |
527 | * returns the branch and | |
528 | * sets the interval to interval = 2^integer (ld (interval)) */ | |
529 | ||
6f5794a6 | 530 | static int ep_int_ballance(ohci_t *ohci, int interval, int load) |
4dae14ce ZW |
531 | { |
532 | int i, branch = 0; | |
533 | ||
534 | /* search for the least loaded interrupt endpoint | |
535 | * branch of all 32 branches | |
536 | */ | |
537 | for (i = 0; i < 32; i++) | |
538 | if (ohci->ohci_int_load [branch] > ohci->ohci_int_load [i]) | |
539 | branch = i; | |
540 | ||
541 | branch = branch % interval; | |
542 | for (i = branch; i < 32; i += interval) | |
543 | ohci->ohci_int_load [i] += load; | |
544 | ||
545 | return branch; | |
546 | } | |
547 | ||
548 | /*-------------------------------------------------------------------------*/ | |
549 | ||
550 | /* 2^int( ld (inter)) */ | |
551 | ||
6f5794a6 | 552 | static int ep_2_n_interval(int inter) |
4dae14ce ZW |
553 | { |
554 | int i; | |
6f5794a6 | 555 | for (i = 0; ((inter >> i) > 1) && (i < 5); i++); |
4dae14ce ZW |
556 | return 1 << i; |
557 | } | |
558 | ||
559 | /*-------------------------------------------------------------------------*/ | |
560 | ||
561 | /* the int tree is a binary tree | |
6f5794a6 RB |
562 | * in order to process it sequentially the indexes of the branches have to |
563 | * be mapped the mapping reverses the bits of a word of num_bits length */ | |
564 | static int ep_rev(int num_bits, int word) | |
4dae14ce ZW |
565 | { |
566 | int i, wout = 0; | |
567 | ||
568 | for (i = 0; i < num_bits; i++) | |
569 | wout |= (((word >> i) & 1) << (num_bits - i - 1)); | |
570 | return wout; | |
571 | } | |
572 | ||
3e326ece MK |
573 | /*-------------------------------------------------------------------------* |
574 | * ED handling functions | |
575 | *-------------------------------------------------------------------------*/ | |
576 | ||
577 | /* link an ed into one of the HC chains */ | |
578 | ||
6f5794a6 | 579 | static int ep_link(ohci_t *ohci, ed_t *edi) |
3e326ece MK |
580 | { |
581 | volatile ed_t *ed = edi; | |
4dae14ce ZW |
582 | int int_branch; |
583 | int i; | |
584 | int inter; | |
585 | int interval; | |
586 | int load; | |
6f5794a6 | 587 | __u32 *ed_p; |
3e326ece MK |
588 | |
589 | ed->state = ED_OPER; | |
4dae14ce | 590 | ed->int_interval = 0; |
3e326ece MK |
591 | |
592 | switch (ed->type) { | |
593 | case PIPE_CONTROL: | |
594 | ed->hwNextED = 0; | |
6f5794a6 | 595 | if (ohci->ed_controltail == NULL) |
a5496a18 | 596 | ohci_writel(ed, &ohci->regs->ed_controlhead); |
6f5794a6 RB |
597 | else |
598 | ohci->ed_controltail->hwNextED = | |
599 | m32_swap((unsigned long)ed); | |
600 | ||
3e326ece MK |
601 | ed->ed_prev = ohci->ed_controltail; |
602 | if (!ohci->ed_controltail && !ohci->ed_rm_list[0] && | |
603 | !ohci->ed_rm_list[1] && !ohci->sleeping) { | |
604 | ohci->hc_control |= OHCI_CTRL_CLE; | |
a5496a18 | 605 | ohci_writel(ohci->hc_control, &ohci->regs->control); |
3e326ece MK |
606 | } |
607 | ohci->ed_controltail = edi; | |
608 | break; | |
609 | ||
610 | case PIPE_BULK: | |
611 | ed->hwNextED = 0; | |
6f5794a6 | 612 | if (ohci->ed_bulktail == NULL) |
a5496a18 | 613 | ohci_writel(ed, &ohci->regs->ed_bulkhead); |
6f5794a6 RB |
614 | else |
615 | ohci->ed_bulktail->hwNextED = | |
616 | m32_swap((unsigned long)ed); | |
617 | ||
3e326ece MK |
618 | ed->ed_prev = ohci->ed_bulktail; |
619 | if (!ohci->ed_bulktail && !ohci->ed_rm_list[0] && | |
620 | !ohci->ed_rm_list[1] && !ohci->sleeping) { | |
621 | ohci->hc_control |= OHCI_CTRL_BLE; | |
a5496a18 | 622 | ohci_writel(ohci->hc_control, &ohci->regs->control); |
3e326ece MK |
623 | } |
624 | ohci->ed_bulktail = edi; | |
625 | break; | |
4dae14ce ZW |
626 | |
627 | case PIPE_INTERRUPT: | |
628 | load = ed->int_load; | |
6f5794a6 | 629 | interval = ep_2_n_interval(ed->int_period); |
4dae14ce | 630 | ed->int_interval = interval; |
6f5794a6 | 631 | int_branch = ep_int_ballance(ohci, interval, load); |
4dae14ce ZW |
632 | ed->int_branch = int_branch; |
633 | ||
6f5794a6 | 634 | for (i = 0; i < ep_rev(6, interval); i += inter) { |
4dae14ce | 635 | inter = 1; |
6f5794a6 RB |
636 | for (ed_p = &(ohci->hcca->int_table[\ |
637 | ep_rev(5, i) + int_branch]); | |
638 | (*ed_p != 0) && | |
639 | (((ed_t *)ed_p)->int_interval >= interval); | |
4dae14ce | 640 | ed_p = &(((ed_t *)ed_p)->hwNextED)) |
6f5794a6 RB |
641 | inter = ep_rev(6, |
642 | ((ed_t *)ed_p)->int_interval); | |
4dae14ce | 643 | ed->hwNextED = *ed_p; |
4a8527ef | 644 | *ed_p = m32_swap((unsigned long)ed); |
4dae14ce ZW |
645 | } |
646 | break; | |
3e326ece MK |
647 | } |
648 | return 0; | |
649 | } | |
650 | ||
651 | /*-------------------------------------------------------------------------*/ | |
652 | ||
4dae14ce | 653 | /* scan the periodic table to find and unlink this ED */ |
6f5794a6 RB |
654 | static void periodic_unlink(struct ohci *ohci, volatile struct ed *ed, |
655 | unsigned index, unsigned period) | |
4dae14ce ZW |
656 | { |
657 | for (; index < NUM_INTS; index += period) { | |
658 | __u32 *ed_p = &ohci->hcca->int_table [index]; | |
659 | ||
660 | /* ED might have been unlinked through another path */ | |
661 | while (*ed_p != 0) { | |
6f5794a6 RB |
662 | if (((struct ed *) |
663 | m32_swap((unsigned long)ed_p)) == ed) { | |
4dae14ce ZW |
664 | *ed_p = ed->hwNextED; |
665 | break; | |
666 | } | |
6f5794a6 RB |
667 | ed_p = &(((struct ed *) |
668 | m32_swap((unsigned long)ed_p))->hwNextED); | |
4dae14ce ZW |
669 | } |
670 | } | |
671 | } | |
672 | ||
3e326ece MK |
673 | /* unlink an ed from one of the HC chains. |
674 | * just the link to the ed is unlinked. | |
675 | * the link from the ed still points to another operational ed or 0 | |
676 | * so the HC can eventually finish the processing of the unlinked ed */ | |
677 | ||
6f5794a6 | 678 | static int ep_unlink(ohci_t *ohci, ed_t *edi) |
3e326ece | 679 | { |
53e336e9 | 680 | volatile ed_t *ed = edi; |
4dae14ce | 681 | int i; |
53e336e9 | 682 | |
6f5794a6 | 683 | ed->hwINFO |= m32_swap(OHCI_ED_SKIP); |
3e326ece MK |
684 | |
685 | switch (ed->type) { | |
686 | case PIPE_CONTROL: | |
687 | if (ed->ed_prev == NULL) { | |
688 | if (!ed->hwNextED) { | |
689 | ohci->hc_control &= ~OHCI_CTRL_CLE; | |
a5496a18 BB |
690 | ohci_writel(ohci->hc_control, |
691 | &ohci->regs->control); | |
3e326ece | 692 | } |
a5496a18 | 693 | ohci_writel(m32_swap(*((__u32 *)&ed->hwNextED)), |
6f5794a6 | 694 | &ohci->regs->ed_controlhead); |
3e326ece MK |
695 | } else { |
696 | ed->ed_prev->hwNextED = ed->hwNextED; | |
697 | } | |
698 | if (ohci->ed_controltail == ed) { | |
699 | ohci->ed_controltail = ed->ed_prev; | |
700 | } else { | |
6f5794a6 RB |
701 | ((ed_t *)m32_swap( |
702 | *((__u32 *)&ed->hwNextED)))->ed_prev = ed->ed_prev; | |
3e326ece MK |
703 | } |
704 | break; | |
705 | ||
706 | case PIPE_BULK: | |
707 | if (ed->ed_prev == NULL) { | |
708 | if (!ed->hwNextED) { | |
709 | ohci->hc_control &= ~OHCI_CTRL_BLE; | |
a5496a18 BB |
710 | ohci_writel(ohci->hc_control, |
711 | &ohci->regs->control); | |
3e326ece | 712 | } |
a5496a18 | 713 | ohci_writel(m32_swap(*((__u32 *)&ed->hwNextED)), |
6f5794a6 | 714 | &ohci->regs->ed_bulkhead); |
3e326ece MK |
715 | } else { |
716 | ed->ed_prev->hwNextED = ed->hwNextED; | |
717 | } | |
718 | if (ohci->ed_bulktail == ed) { | |
719 | ohci->ed_bulktail = ed->ed_prev; | |
720 | } else { | |
6f5794a6 RB |
721 | ((ed_t *)m32_swap( |
722 | *((__u32 *)&ed->hwNextED)))->ed_prev = ed->ed_prev; | |
3e326ece MK |
723 | } |
724 | break; | |
4dae14ce ZW |
725 | |
726 | case PIPE_INTERRUPT: | |
6f5794a6 | 727 | periodic_unlink(ohci, ed, 0, 1); |
4dae14ce ZW |
728 | for (i = ed->int_branch; i < 32; i += ed->int_interval) |
729 | ohci->ohci_int_load[i] -= ed->int_load; | |
730 | break; | |
3e326ece MK |
731 | } |
732 | ed->state = ED_UNLINK; | |
733 | return 0; | |
734 | } | |
735 | ||
3e326ece MK |
736 | /*-------------------------------------------------------------------------*/ |
737 | ||
ddf83a2f MK |
738 | /* add/reinit an endpoint; this should be done once at the |
739 | * usb_set_configuration command, but the USB stack is a little bit | |
740 | * stateless so we do it at every transaction if the state of the ed | |
741 | * is ED_NEW then a dummy td is added and the state is changed to | |
742 | * ED_UNLINK in all other cases the state is left unchanged the ed | |
743 | * info fields are setted anyway even though most of them should not | |
744 | * change | |
745 | */ | |
6f5794a6 RB |
746 | static ed_t *ep_add_ed(struct usb_device *usb_dev, unsigned long pipe, |
747 | int interval, int load) | |
3e326ece MK |
748 | { |
749 | td_t *td; | |
750 | ed_t *ed_ret; | |
751 | volatile ed_t *ed; | |
752 | ||
6f5794a6 RB |
753 | ed = ed_ret = &ohci_dev.ed[(usb_pipeendpoint(pipe) << 1) | |
754 | (usb_pipecontrol(pipe)? 0: usb_pipeout(pipe))]; | |
3e326ece MK |
755 | |
756 | if ((ed->state & ED_DEL) || (ed->state & ED_URB_DEL)) { | |
757 | err("ep_add_ed: pending delete"); | |
758 | /* pending delete request */ | |
759 | return NULL; | |
760 | } | |
761 | ||
762 | if (ed->state == ED_NEW) { | |
3e326ece | 763 | /* dummy td; end of td list for ed */ |
6f5794a6 RB |
764 | td = td_alloc(usb_dev); |
765 | ed->hwTailP = m32_swap((unsigned long)td); | |
3e326ece MK |
766 | ed->hwHeadP = ed->hwTailP; |
767 | ed->state = ED_UNLINK; | |
6f5794a6 | 768 | ed->type = usb_pipetype(pipe); |
3e326ece MK |
769 | ohci_dev.ed_cnt++; |
770 | } | |
771 | ||
6f5794a6 RB |
772 | ed->hwINFO = m32_swap(usb_pipedevice(pipe) |
773 | | usb_pipeendpoint(pipe) << 7 | |
774 | | (usb_pipeisoc(pipe)? 0x8000: 0) | |
775 | | (usb_pipecontrol(pipe)? 0: \ | |
776 | (usb_pipeout(pipe)? 0x800: 0x1000)) | |
c60795f4 | 777 | | (usb_dev->speed == USB_SPEED_LOW) << 13 |
6f5794a6 | 778 | | usb_maxpacket(usb_dev, pipe) << 16); |
3e326ece | 779 | |
4dae14ce ZW |
780 | if (ed->type == PIPE_INTERRUPT && ed->state == ED_UNLINK) { |
781 | ed->int_period = interval; | |
782 | ed->int_load = load; | |
783 | } | |
784 | ||
3e326ece MK |
785 | return ed_ret; |
786 | } | |
787 | ||
788 | /*-------------------------------------------------------------------------* | |
789 | * TD handling functions | |
790 | *-------------------------------------------------------------------------*/ | |
791 | ||
792 | /* enqueue next TD for this URB (OHCI spec 5.2.8.2) */ | |
793 | ||
6f5794a6 | 794 | static void td_fill(ohci_t *ohci, unsigned int info, |
3e326ece MK |
795 | void *data, int len, |
796 | struct usb_device *dev, int index, urb_priv_t *urb_priv) | |
797 | { | |
798 | volatile td_t *td, *td_pt; | |
799 | #ifdef OHCI_FILL_TRACE | |
800 | int i; | |
801 | #endif | |
802 | ||
803 | if (index > urb_priv->length) { | |
804 | err("index > length"); | |
805 | return; | |
806 | } | |
807 | /* use this td as the next dummy */ | |
808 | td_pt = urb_priv->td [index]; | |
809 | td_pt->hwNextTD = 0; | |
810 | ||
811 | /* fill the old dummy TD */ | |
6f5794a6 RB |
812 | td = urb_priv->td [index] = |
813 | (td_t *)(m32_swap(urb_priv->ed->hwTailP) & ~0xf); | |
3e326ece MK |
814 | |
815 | td->ed = urb_priv->ed; | |
816 | td->next_dl_td = NULL; | |
817 | td->index = index; | |
818 | td->data = (__u32)data; | |
819 | #ifdef OHCI_FILL_TRACE | |
48867208 | 820 | if (usb_pipebulk(urb_priv->pipe) && usb_pipeout(urb_priv->pipe)) { |
3e326ece | 821 | for (i = 0; i < len; i++) |
6f5794a6 | 822 | printf("td->data[%d] %#2x ", i, ((unsigned char *)td->data)[i]); |
3e326ece MK |
823 | printf("\n"); |
824 | } | |
825 | #endif | |
826 | if (!len) | |
827 | data = 0; | |
828 | ||
6f5794a6 RB |
829 | td->hwINFO = m32_swap(info); |
830 | td->hwCBP = m32_swap((unsigned long)data); | |
3e326ece | 831 | if (data) |
6f5794a6 | 832 | td->hwBE = m32_swap((unsigned long)(data + len - 1)); |
3e326ece MK |
833 | else |
834 | td->hwBE = 0; | |
6f5794a6 RB |
835 | |
836 | td->hwNextTD = m32_swap((unsigned long)td_pt); | |
3e326ece MK |
837 | |
838 | /* append to queue */ | |
839 | td->ed->hwTailP = td->hwNextTD; | |
840 | } | |
841 | ||
842 | /*-------------------------------------------------------------------------*/ | |
843 | ||
844 | /* prepare all TDs of a transfer */ | |
845 | ||
c5613df5 HG |
846 | static void td_submit_job(ohci_t *ohci, struct usb_device *dev, |
847 | unsigned long pipe, void *buffer, int transfer_len, | |
6f5794a6 RB |
848 | struct devrequest *setup, urb_priv_t *urb, |
849 | int interval) | |
3e326ece | 850 | { |
3e326ece MK |
851 | int data_len = transfer_len; |
852 | void *data; | |
853 | int cnt = 0; | |
854 | __u32 info = 0; | |
855 | unsigned int toggle = 0; | |
856 | ||
6f5794a6 RB |
857 | /* OHCI handles the DATA-toggles itself, we just use the USB-toggle |
858 | * bits for reseting */ | |
859 | if (usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe))) { | |
3e326ece MK |
860 | toggle = TD_T_TOGGLE; |
861 | } else { | |
862 | toggle = TD_T_DATA0; | |
6f5794a6 RB |
863 | usb_settoggle(dev, usb_pipeendpoint(pipe), |
864 | usb_pipeout(pipe), 1); | |
3e326ece MK |
865 | } |
866 | urb->td_cnt = 0; | |
867 | if (data_len) | |
868 | data = buffer; | |
869 | else | |
870 | data = 0; | |
871 | ||
6f5794a6 | 872 | switch (usb_pipetype(pipe)) { |
3e326ece | 873 | case PIPE_BULK: |
6f5794a6 | 874 | info = usb_pipeout(pipe)? |
3e326ece | 875 | TD_CC | TD_DP_OUT : TD_CC | TD_DP_IN ; |
6f5794a6 RB |
876 | while (data_len > 4096) { |
877 | td_fill(ohci, info | (cnt? TD_T_TOGGLE:toggle), | |
878 | data, 4096, dev, cnt, urb); | |
3e326ece MK |
879 | data += 4096; data_len -= 4096; cnt++; |
880 | } | |
6f5794a6 | 881 | info = usb_pipeout(pipe)? |
3e326ece | 882 | TD_CC | TD_DP_OUT : TD_CC | TD_R | TD_DP_IN ; |
6f5794a6 RB |
883 | td_fill(ohci, info | (cnt? TD_T_TOGGLE:toggle), data, |
884 | data_len, dev, cnt, urb); | |
3e326ece MK |
885 | cnt++; |
886 | ||
6f5794a6 RB |
887 | if (!ohci->sleeping) { |
888 | /* start bulk list */ | |
a5496a18 | 889 | ohci_writel(OHCI_BLF, &ohci->regs->cmdstatus); |
6f5794a6 | 890 | } |
3e326ece MK |
891 | break; |
892 | ||
893 | case PIPE_CONTROL: | |
6f5794a6 | 894 | /* Setup phase */ |
3e326ece | 895 | info = TD_CC | TD_DP_SETUP | TD_T_DATA0; |
6f5794a6 RB |
896 | td_fill(ohci, info, setup, 8, dev, cnt++, urb); |
897 | ||
898 | /* Optional Data phase */ | |
3e326ece | 899 | if (data_len > 0) { |
6f5794a6 RB |
900 | info = usb_pipeout(pipe)? |
901 | TD_CC | TD_R | TD_DP_OUT | TD_T_DATA1 : | |
902 | TD_CC | TD_R | TD_DP_IN | TD_T_DATA1; | |
3e326ece | 903 | /* NOTE: mishandles transfers >8K, some >4K */ |
6f5794a6 RB |
904 | td_fill(ohci, info, data, data_len, dev, cnt++, urb); |
905 | } | |
906 | ||
907 | /* Status phase */ | |
908 | info = usb_pipeout(pipe)? | |
909 | TD_CC | TD_DP_IN | TD_T_DATA1: | |
910 | TD_CC | TD_DP_OUT | TD_T_DATA1; | |
911 | td_fill(ohci, info, data, 0, dev, cnt++, urb); | |
912 | ||
913 | if (!ohci->sleeping) { | |
914 | /* start Control list */ | |
a5496a18 | 915 | ohci_writel(OHCI_CLF, &ohci->regs->cmdstatus); |
3e326ece | 916 | } |
3e326ece | 917 | break; |
4dae14ce ZW |
918 | |
919 | case PIPE_INTERRUPT: | |
6f5794a6 | 920 | info = usb_pipeout(urb->pipe)? |
4dae14ce ZW |
921 | TD_CC | TD_DP_OUT | toggle: |
922 | TD_CC | TD_R | TD_DP_IN | toggle; | |
6f5794a6 | 923 | td_fill(ohci, info, data, data_len, dev, cnt++, urb); |
4dae14ce | 924 | break; |
3e326ece MK |
925 | } |
926 | if (urb->length != cnt) | |
927 | dbg("TD LENGTH %d != CNT %d", urb->length, cnt); | |
928 | } | |
929 | ||
930 | /*-------------------------------------------------------------------------* | |
931 | * Done List handling functions | |
932 | *-------------------------------------------------------------------------*/ | |
933 | ||
3e326ece MK |
934 | /* calculate the transfer length and update the urb */ |
935 | ||
6f5794a6 | 936 | static void dl_transfer_length(td_t *td) |
3e326ece | 937 | { |
6bc52ef3 | 938 | __u32 tdBE, tdCBP; |
4dae14ce | 939 | urb_priv_t *lurb_priv = td->ed->purb; |
3e326ece | 940 | |
6f5794a6 RB |
941 | tdBE = m32_swap(td->hwBE); |
942 | tdCBP = m32_swap(td->hwCBP); | |
3e326ece | 943 | |
48867208 | 944 | if (!(usb_pipecontrol(lurb_priv->pipe) && |
3e326ece MK |
945 | ((td->index == 0) || (td->index == lurb_priv->length - 1)))) { |
946 | if (tdBE != 0) { | |
947 | if (td->hwCBP == 0) | |
948 | lurb_priv->actual_length += tdBE - td->data + 1; | |
949 | else | |
950 | lurb_priv->actual_length += tdCBP - td->data; | |
951 | } | |
952 | } | |
953 | } | |
954 | ||
955 | /*-------------------------------------------------------------------------*/ | |
6f5794a6 RB |
956 | static void check_status(td_t *td_list) |
957 | { | |
958 | urb_priv_t *lurb_priv = td_list->ed->purb; | |
959 | int urb_len = lurb_priv->length; | |
960 | __u32 *phwHeadP = &td_list->ed->hwHeadP; | |
961 | int cc; | |
962 | ||
963 | cc = TD_CC_GET(m32_swap(td_list->hwINFO)); | |
964 | if (cc) { | |
965 | err(" USB-error: %s (%x)", cc_to_string[cc], cc); | |
966 | ||
967 | if (*phwHeadP & m32_swap(0x1)) { | |
968 | if (lurb_priv && | |
969 | ((td_list->index + 1) < urb_len)) { | |
970 | *phwHeadP = | |
971 | (lurb_priv->td[urb_len - 1]->hwNextTD &\ | |
972 | m32_swap(0xfffffff0)) | | |
973 | (*phwHeadP & m32_swap(0x2)); | |
974 | ||
975 | lurb_priv->td_cnt += urb_len - | |
976 | td_list->index - 1; | |
977 | } else | |
978 | *phwHeadP &= m32_swap(0xfffffff2); | |
979 | } | |
980 | #ifdef CONFIG_MPC5200 | |
981 | td_list->hwNextTD = 0; | |
982 | #endif | |
983 | } | |
984 | } | |
3e326ece MK |
985 | |
986 | /* replies to the request have to be on a FIFO basis so | |
987 | * we reverse the reversed done-list */ | |
6f5794a6 | 988 | static td_t *dl_reverse_done_list(ohci_t *ohci) |
3e326ece MK |
989 | { |
990 | __u32 td_list_hc; | |
991 | td_t *td_rev = NULL; | |
992 | td_t *td_list = NULL; | |
3e326ece | 993 | |
6f5794a6 | 994 | td_list_hc = m32_swap(ohci->hcca->done_head) & 0xfffffff0; |
3e326ece MK |
995 | ohci->hcca->done_head = 0; |
996 | ||
997 | while (td_list_hc) { | |
998 | td_list = (td_t *)td_list_hc; | |
6f5794a6 | 999 | check_status(td_list); |
3e326ece MK |
1000 | td_list->next_dl_td = td_rev; |
1001 | td_rev = td_list; | |
6f5794a6 | 1002 | td_list_hc = m32_swap(td_list->hwNextTD) & 0xfffffff0; |
3e326ece MK |
1003 | } |
1004 | return td_list; | |
1005 | } | |
1006 | ||
6f5794a6 | 1007 | /*-------------------------------------------------------------------------*/ |
3e326ece MK |
1008 | /*-------------------------------------------------------------------------*/ |
1009 | ||
6f5794a6 RB |
1010 | static void finish_urb(ohci_t *ohci, urb_priv_t *urb, int status) |
1011 | { | |
1012 | if ((status & (ED_OPER | ED_UNLINK)) && (urb->state != URB_DEL)) | |
1013 | urb->finished = sohci_return_job(ohci, urb); | |
1014 | else | |
1015 | dbg("finish_urb: strange.., ED state %x, \n", status); | |
1016 | } | |
1017 | ||
1018 | /* | |
1019 | * Used to take back a TD from the host controller. This would normally be | |
1020 | * called from within dl_done_list, however it may be called directly if the | |
1021 | * HC no longer sees the TD and it has not appeared on the donelist (after | |
1022 | * two frames). This bug has been observed on ZF Micro systems. | |
1023 | */ | |
1024 | static int takeback_td(ohci_t *ohci, td_t *td_list) | |
3e326ece | 1025 | { |
3e326ece | 1026 | ed_t *ed; |
6f5794a6 | 1027 | int cc; |
3e326ece MK |
1028 | int stat = 0; |
1029 | /* urb_t *urb; */ | |
1030 | urb_priv_t *lurb_priv; | |
1031 | __u32 tdINFO, edHeadP, edTailP; | |
1032 | ||
6f5794a6 | 1033 | tdINFO = m32_swap(td_list->hwINFO); |
3e326ece | 1034 | |
6f5794a6 RB |
1035 | ed = td_list->ed; |
1036 | lurb_priv = ed->purb; | |
3e326ece | 1037 | |
6f5794a6 | 1038 | dl_transfer_length(td_list); |
3e326ece | 1039 | |
6f5794a6 | 1040 | lurb_priv->td_cnt++; |
3e326ece | 1041 | |
6f5794a6 RB |
1042 | /* error code of transfer */ |
1043 | cc = TD_CC_GET(tdINFO); | |
1044 | if (cc) { | |
1045 | err("USB-error: %s (%x)", cc_to_string[cc], cc); | |
1046 | stat = cc_to_error[cc]; | |
1047 | } | |
ae79f606 | 1048 | |
6f5794a6 RB |
1049 | /* see if this done list makes for all TD's of current URB, |
1050 | * and mark the URB finished if so */ | |
1051 | if (lurb_priv->td_cnt == lurb_priv->length) | |
1052 | finish_urb(ohci, lurb_priv, ed->state); | |
1053 | ||
1054 | dbg("dl_done_list: processing TD %x, len %x\n", | |
1055 | lurb_priv->td_cnt, lurb_priv->length); | |
1056 | ||
48867208 | 1057 | if (ed->state != ED_NEW && (!usb_pipeint(lurb_priv->pipe))) { |
6f5794a6 RB |
1058 | edHeadP = m32_swap(ed->hwHeadP) & 0xfffffff0; |
1059 | edTailP = m32_swap(ed->hwTailP); | |
1060 | ||
1061 | /* unlink eds if they are not busy */ | |
1062 | if ((edHeadP == edTailP) && (ed->state == ED_OPER)) | |
1063 | ep_unlink(ohci, ed); | |
1064 | } | |
1065 | return stat; | |
1066 | } | |
3e326ece | 1067 | |
6f5794a6 RB |
1068 | static int dl_done_list(ohci_t *ohci) |
1069 | { | |
1070 | int stat = 0; | |
1071 | td_t *td_list = dl_reverse_done_list(ohci); | |
1072 | ||
1073 | while (td_list) { | |
1074 | td_t *td_next = td_list->next_dl_td; | |
1075 | stat = takeback_td(ohci, td_list); | |
1076 | td_list = td_next; | |
3e326ece MK |
1077 | } |
1078 | return stat; | |
1079 | } | |
1080 | ||
1081 | /*-------------------------------------------------------------------------* | |
1082 | * Virtual Root Hub | |
1083 | *-------------------------------------------------------------------------*/ | |
1084 | ||
eb838e7d | 1085 | #include <usbroothubdes.h> |
3e326ece MK |
1086 | |
1087 | /* Hub class-specific descriptor is constructed dynamically */ | |
1088 | ||
3e326ece MK |
1089 | /*-------------------------------------------------------------------------*/ |
1090 | ||
1091 | #define OK(x) len = (x); break | |
1092 | #ifdef DEBUG | |
a5496a18 | 1093 | #define WR_RH_STAT(x) {info("WR:status %#8x", (x)); ohci_writel((x), \ |
c5613df5 | 1094 | &ohci->regs->roothub.status); } |
6f5794a6 | 1095 | #define WR_RH_PORTSTAT(x) {info("WR:portstatus[%d] %#8x", wIndex-1, \ |
c5613df5 | 1096 | (x)); ohci_writel((x), &ohci->regs->roothub.portstatus[wIndex-1]); } |
3e326ece | 1097 | #else |
c5613df5 | 1098 | #define WR_RH_STAT(x) ohci_writel((x), &ohci->regs->roothub.status) |
a5496a18 | 1099 | #define WR_RH_PORTSTAT(x) ohci_writel((x), \ |
c5613df5 | 1100 | &ohci->regs->roothub.portstatus[wIndex-1]) |
3e326ece | 1101 | #endif |
c5613df5 HG |
1102 | #define RD_RH_STAT roothub_status(ohci) |
1103 | #define RD_RH_PORTSTAT roothub_portstatus(ohci, wIndex-1) | |
3e326ece MK |
1104 | |
1105 | /* request to virtual root hub */ | |
1106 | ||
1107 | int rh_check_port_status(ohci_t *controller) | |
1108 | { | |
1109 | __u32 temp, ndp, i; | |
1110 | int res; | |
1111 | ||
1112 | res = -1; | |
6f5794a6 | 1113 | temp = roothub_a(controller); |
3e326ece MK |
1114 | ndp = (temp & RH_A_NDP); |
1115 | #ifdef CONFIG_AT91C_PQFP_UHPBUG | |
1116 | ndp = (ndp == 2) ? 1:0; | |
1117 | #endif | |
1118 | for (i = 0; i < ndp; i++) { | |
6f5794a6 | 1119 | temp = roothub_portstatus(controller, i); |
3e326ece MK |
1120 | /* check for a device disconnect */ |
1121 | if (((temp & (RH_PS_PESC | RH_PS_CSC)) == | |
1122 | (RH_PS_PESC | RH_PS_CSC)) && | |
1123 | ((temp & RH_PS_CCS) == 0)) { | |
1124 | res = i; | |
1125 | break; | |
1126 | } | |
1127 | } | |
1128 | return res; | |
1129 | } | |
1130 | ||
c5613df5 HG |
1131 | static int ohci_submit_rh_msg(ohci_t *ohci, struct usb_device *dev, |
1132 | unsigned long pipe, void *buffer, int transfer_len, | |
1133 | struct devrequest *cmd) | |
3e326ece | 1134 | { |
6f5794a6 | 1135 | void *data = buffer; |
3e326ece MK |
1136 | int leni = transfer_len; |
1137 | int len = 0; | |
1138 | int stat = 0; | |
3e326ece MK |
1139 | __u16 bmRType_bReq; |
1140 | __u16 wValue; | |
1141 | __u16 wIndex; | |
1142 | __u16 wLength; | |
f1273f11 | 1143 | ALLOC_ALIGN_BUFFER(__u8, databuf, 16, sizeof(u32)); |
5f6aa03f | 1144 | |
3e326ece | 1145 | #ifdef DEBUG |
c5613df5 | 1146 | pkt_print(ohci, NULL, dev, pipe, buffer, transfer_len, |
6f5794a6 | 1147 | cmd, "SUB(rh)", usb_pipein(pipe)); |
3e326ece | 1148 | #else |
5b84dd67 | 1149 | mdelay(1); |
3e326ece | 1150 | #endif |
48867208 | 1151 | if (usb_pipeint(pipe)) { |
3e326ece MK |
1152 | info("Root-Hub submit IRQ: NOT implemented"); |
1153 | return 0; | |
1154 | } | |
1155 | ||
1156 | bmRType_bReq = cmd->requesttype | (cmd->request << 8); | |
6f5794a6 RB |
1157 | wValue = le16_to_cpu(cmd->value); |
1158 | wIndex = le16_to_cpu(cmd->index); | |
1159 | wLength = le16_to_cpu(cmd->length); | |
3e326ece MK |
1160 | |
1161 | info("Root-Hub: adr: %2x cmd(%1x): %08x %04x %04x %04x", | |
1162 | dev->devnum, 8, bmRType_bReq, wValue, wIndex, wLength); | |
1163 | ||
1164 | switch (bmRType_bReq) { | |
1165 | /* Request Destination: | |
1166 | without flags: Device, | |
1167 | RH_INTERFACE: interface, | |
1168 | RH_ENDPOINT: endpoint, | |
1169 | RH_CLASS means HUB here, | |
1170 | RH_OTHER | RH_CLASS almost ever means HUB_PORT here | |
1171 | */ | |
1172 | ||
1173 | case RH_GET_STATUS: | |
f1273f11 | 1174 | *(u16 *)databuf = cpu_to_le16(1); |
6f5794a6 | 1175 | OK(2); |
3e326ece | 1176 | case RH_GET_STATUS | RH_INTERFACE: |
f1273f11 | 1177 | *(u16 *)databuf = cpu_to_le16(0); |
6f5794a6 | 1178 | OK(2); |
3e326ece | 1179 | case RH_GET_STATUS | RH_ENDPOINT: |
f1273f11 | 1180 | *(u16 *)databuf = cpu_to_le16(0); |
6f5794a6 | 1181 | OK(2); |
3e326ece | 1182 | case RH_GET_STATUS | RH_CLASS: |
f1273f11 | 1183 | *(u32 *)databuf = cpu_to_le32( |
3e326ece | 1184 | RD_RH_STAT & ~(RH_HS_CRWE | RH_HS_DRWE)); |
6f5794a6 | 1185 | OK(4); |
3e326ece | 1186 | case RH_GET_STATUS | RH_OTHER | RH_CLASS: |
f1273f11 | 1187 | *(u32 *)databuf = cpu_to_le32(RD_RH_PORTSTAT); |
6f5794a6 | 1188 | OK(4); |
3e326ece MK |
1189 | |
1190 | case RH_CLEAR_FEATURE | RH_ENDPOINT: | |
1191 | switch (wValue) { | |
6f5794a6 RB |
1192 | case (RH_ENDPOINT_STALL): |
1193 | OK(0); | |
3e326ece MK |
1194 | } |
1195 | break; | |
1196 | ||
1197 | case RH_CLEAR_FEATURE | RH_CLASS: | |
1198 | switch (wValue) { | |
6f5794a6 RB |
1199 | case RH_C_HUB_LOCAL_POWER: |
1200 | OK(0); | |
1201 | case (RH_C_HUB_OVER_CURRENT): | |
1202 | WR_RH_STAT(RH_HS_OCIC); | |
1203 | OK(0); | |
3e326ece MK |
1204 | } |
1205 | break; | |
1206 | ||
1207 | case RH_CLEAR_FEATURE | RH_OTHER | RH_CLASS: | |
1208 | switch (wValue) { | |
6f5794a6 RB |
1209 | case (RH_PORT_ENABLE): WR_RH_PORTSTAT(RH_PS_CCS); OK(0); |
1210 | case (RH_PORT_SUSPEND): WR_RH_PORTSTAT(RH_PS_POCI); OK(0); | |
1211 | case (RH_PORT_POWER): WR_RH_PORTSTAT(RH_PS_LSDA); OK(0); | |
1212 | case (RH_C_PORT_CONNECTION): WR_RH_PORTSTAT(RH_PS_CSC); OK(0); | |
1213 | case (RH_C_PORT_ENABLE): WR_RH_PORTSTAT(RH_PS_PESC); OK(0); | |
1214 | case (RH_C_PORT_SUSPEND): WR_RH_PORTSTAT(RH_PS_PSSC); OK(0); | |
1215 | case (RH_C_PORT_OVER_CURRENT):WR_RH_PORTSTAT(RH_PS_OCIC); OK(0); | |
1216 | case (RH_C_PORT_RESET): WR_RH_PORTSTAT(RH_PS_PRSC); OK(0); | |
3e326ece MK |
1217 | } |
1218 | break; | |
1219 | ||
1220 | case RH_SET_FEATURE | RH_OTHER | RH_CLASS: | |
1221 | switch (wValue) { | |
6f5794a6 RB |
1222 | case (RH_PORT_SUSPEND): |
1223 | WR_RH_PORTSTAT(RH_PS_PSS); OK(0); | |
1224 | case (RH_PORT_RESET): /* BUG IN HUP CODE *********/ | |
1225 | if (RD_RH_PORTSTAT & RH_PS_CCS) | |
1226 | WR_RH_PORTSTAT(RH_PS_PRS); | |
1227 | OK(0); | |
1228 | case (RH_PORT_POWER): | |
1229 | WR_RH_PORTSTAT(RH_PS_PPS); | |
5b84dd67 | 1230 | mdelay(100); |
6f5794a6 RB |
1231 | OK(0); |
1232 | case (RH_PORT_ENABLE): /* BUG IN HUP CODE *********/ | |
1233 | if (RD_RH_PORTSTAT & RH_PS_CCS) | |
1234 | WR_RH_PORTSTAT(RH_PS_PES); | |
1235 | OK(0); | |
3e326ece MK |
1236 | } |
1237 | break; | |
1238 | ||
6f5794a6 | 1239 | case RH_SET_ADDRESS: |
c5613df5 | 1240 | ohci->rh.devnum = wValue; |
6f5794a6 | 1241 | OK(0); |
3e326ece MK |
1242 | |
1243 | case RH_GET_DESCRIPTOR: | |
1244 | switch ((wValue & 0xff00) >> 8) { | |
6f5794a6 RB |
1245 | case (0x01): /* device descriptor */ |
1246 | len = min_t(unsigned int, | |
1247 | leni, | |
1248 | min_t(unsigned int, | |
1249 | sizeof(root_hub_dev_des), | |
1250 | wLength)); | |
f1273f11 | 1251 | databuf = root_hub_dev_des; OK(len); |
6f5794a6 RB |
1252 | case (0x02): /* configuration descriptor */ |
1253 | len = min_t(unsigned int, | |
1254 | leni, | |
1255 | min_t(unsigned int, | |
1256 | sizeof(root_hub_config_des), | |
1257 | wLength)); | |
f1273f11 | 1258 | databuf = root_hub_config_des; OK(len); |
6f5794a6 RB |
1259 | case (0x03): /* string descriptors */ |
1260 | if (wValue == 0x0300) { | |
3e326ece | 1261 | len = min_t(unsigned int, |
6f5794a6 RB |
1262 | leni, |
1263 | min_t(unsigned int, | |
1264 | sizeof(root_hub_str_index0), | |
1265 | wLength)); | |
f1273f11 | 1266 | databuf = root_hub_str_index0; |
6f5794a6 | 1267 | OK(len); |
3e326ece | 1268 | } |
6f5794a6 RB |
1269 | if (wValue == 0x0301) { |
1270 | len = min_t(unsigned int, | |
1271 | leni, | |
1272 | min_t(unsigned int, | |
1273 | sizeof(root_hub_str_index1), | |
1274 | wLength)); | |
f1273f11 | 1275 | databuf = root_hub_str_index1; |
6f5794a6 RB |
1276 | OK(len); |
1277 | } | |
1278 | default: | |
1279 | stat = USB_ST_STALLED; | |
3e326ece MK |
1280 | } |
1281 | break; | |
1282 | ||
1283 | case RH_GET_DESCRIPTOR | RH_CLASS: | |
1284 | { | |
c5613df5 | 1285 | __u32 temp = roothub_a(ohci); |
3e326ece | 1286 | |
f1273f11 TK |
1287 | databuf[0] = 9; /* min length; */ |
1288 | databuf[1] = 0x29; | |
1289 | databuf[2] = temp & RH_A_NDP; | |
3e326ece | 1290 | #ifdef CONFIG_AT91C_PQFP_UHPBUG |
f1273f11 | 1291 | databuf[2] = (databuf[2] == 2) ? 1 : 0; |
3e326ece | 1292 | #endif |
f1273f11 | 1293 | databuf[3] = 0; |
3e326ece | 1294 | if (temp & RH_A_PSM) /* per-port power switching? */ |
f1273f11 | 1295 | databuf[3] |= 0x1; |
3e326ece | 1296 | if (temp & RH_A_NOCP) /* no overcurrent reporting? */ |
f1273f11 | 1297 | databuf[3] |= 0x10; |
6f5794a6 | 1298 | else if (temp & RH_A_OCPM)/* per-port overcurrent reporting? */ |
f1273f11 | 1299 | databuf[3] |= 0x8; |
3e326ece | 1300 | |
f1273f11 TK |
1301 | databuf[4] = 0; |
1302 | databuf[5] = (temp & RH_A_POTPGT) >> 24; | |
1303 | databuf[6] = 0; | |
c5613df5 | 1304 | temp = roothub_b(ohci); |
f1273f11 TK |
1305 | databuf[7] = temp & RH_B_DR; |
1306 | if (databuf[2] < 7) { | |
1307 | databuf[8] = 0xff; | |
3e326ece | 1308 | } else { |
f1273f11 TK |
1309 | databuf[0] += 2; |
1310 | databuf[8] = (temp & RH_B_DR) >> 8; | |
1311 | databuf[10] = databuf[9] = 0xff; | |
3e326ece MK |
1312 | } |
1313 | ||
1314 | len = min_t(unsigned int, leni, | |
f1273f11 | 1315 | min_t(unsigned int, databuf[0], wLength)); |
6f5794a6 | 1316 | OK(len); |
3e326ece MK |
1317 | } |
1318 | ||
5f6aa03f | 1319 | case RH_GET_CONFIGURATION: |
f1273f11 | 1320 | databuf[0] = 0x01; |
5f6aa03f | 1321 | OK(1); |
3e326ece | 1322 | |
5f6aa03f MV |
1323 | case RH_SET_CONFIGURATION: |
1324 | WR_RH_STAT(0x10000); | |
1325 | OK(0); | |
3e326ece MK |
1326 | |
1327 | default: | |
6f5794a6 | 1328 | dbg("unsupported root hub command"); |
3e326ece MK |
1329 | stat = USB_ST_STALLED; |
1330 | } | |
1331 | ||
1332 | #ifdef DEBUG | |
c5613df5 | 1333 | ohci_dump_roothub(ohci, 1); |
3e326ece | 1334 | #else |
5b84dd67 | 1335 | mdelay(1); |
3e326ece MK |
1336 | #endif |
1337 | ||
1338 | len = min_t(int, len, leni); | |
f1273f11 TK |
1339 | if (data != databuf) |
1340 | memcpy(data, databuf, len); | |
3e326ece MK |
1341 | dev->act_len = len; |
1342 | dev->status = stat; | |
1343 | ||
1344 | #ifdef DEBUG | |
c5613df5 | 1345 | pkt_print(ohci, NULL, dev, pipe, buffer, |
6f5794a6 | 1346 | transfer_len, cmd, "RET(rh)", 0/*usb_pipein(pipe)*/); |
3e326ece | 1347 | #else |
5b84dd67 | 1348 | mdelay(1); |
3e326ece MK |
1349 | #endif |
1350 | ||
1351 | return stat; | |
1352 | } | |
1353 | ||
1354 | /*-------------------------------------------------------------------------*/ | |
1355 | ||
1356 | /* common code for handling submit messages - used for all but root hub */ | |
1357 | /* accesses. */ | |
c5613df5 HG |
1358 | static int submit_common_msg(ohci_t *ohci, struct usb_device *dev, |
1359 | unsigned long pipe, void *buffer, int transfer_len, | |
1360 | struct devrequest *setup, int interval) | |
3e326ece MK |
1361 | { |
1362 | int stat = 0; | |
1363 | int maxsize = usb_maxpacket(dev, pipe); | |
1364 | int timeout; | |
4dae14ce ZW |
1365 | urb_priv_t *urb; |
1366 | ||
1367 | urb = malloc(sizeof(urb_priv_t)); | |
1368 | memset(urb, 0, sizeof(urb_priv_t)); | |
1369 | ||
1370 | urb->dev = dev; | |
1371 | urb->pipe = pipe; | |
1372 | urb->transfer_buffer = buffer; | |
1373 | urb->transfer_buffer_length = transfer_len; | |
1374 | urb->interval = interval; | |
3e326ece | 1375 | |
3e326ece | 1376 | #ifdef DEBUG |
4dae14ce | 1377 | urb->actual_length = 0; |
c5613df5 | 1378 | pkt_print(ohci, urb, dev, pipe, buffer, transfer_len, |
6f5794a6 | 1379 | setup, "SUB", usb_pipein(pipe)); |
3e326ece | 1380 | #else |
5b84dd67 | 1381 | mdelay(1); |
3e326ece MK |
1382 | #endif |
1383 | if (!maxsize) { | |
1384 | err("submit_common_message: pipesize for pipe %lx is zero", | |
1385 | pipe); | |
1386 | return -1; | |
1387 | } | |
1388 | ||
c5613df5 | 1389 | if (sohci_submit_job(ohci, urb, setup) < 0) { |
3e326ece MK |
1390 | err("sohci_submit_job failed"); |
1391 | return -1; | |
1392 | } | |
1393 | ||
ae3b770e | 1394 | #if 0 |
5b84dd67 | 1395 | mdelay(10); |
c5613df5 | 1396 | /* ohci_dump_status(ohci); */ |
ae3b770e | 1397 | #endif |
3e326ece | 1398 | |
96820a35 | 1399 | timeout = USB_TIMEOUT_MS(pipe); |
3e326ece MK |
1400 | |
1401 | /* wait for it to complete */ | |
1402 | for (;;) { | |
1403 | /* check whether the controller is done */ | |
c5613df5 | 1404 | stat = hc_interrupt(ohci); |
3e326ece MK |
1405 | if (stat < 0) { |
1406 | stat = USB_ST_CRC_ERR; | |
1407 | break; | |
1408 | } | |
ddf83a2f | 1409 | |
ddf83a2f MK |
1410 | /* NOTE: since we are not interrupt driven in U-Boot and always |
1411 | * handle only one URB at a time, we cannot assume the | |
1412 | * transaction finished on the first successful return from | |
1413 | * hc_interrupt().. unless the flag for current URB is set, | |
1414 | * meaning that all TD's to/from device got actually | |
1415 | * transferred and processed. If the current URB is not | |
1416 | * finished we need to re-iterate this loop so as | |
1417 | * hc_interrupt() gets called again as there needs to be some | |
1418 | * more TD's to process still */ | |
4dae14ce | 1419 | if ((stat >= 0) && (stat != 0xff) && (urb->finished)) { |
3e326ece MK |
1420 | /* 0xff is returned for an SF-interrupt */ |
1421 | break; | |
1422 | } | |
ddf83a2f | 1423 | |
3e326ece | 1424 | if (--timeout) { |
5b84dd67 | 1425 | mdelay(1); |
4dae14ce | 1426 | if (!urb->finished) |
6f5794a6 | 1427 | dbg("*"); |
4dae14ce | 1428 | |
3e326ece MK |
1429 | } else { |
1430 | err("CTL:TIMEOUT "); | |
ddf83a2f | 1431 | dbg("submit_common_msg: TO status %x\n", stat); |
4dae14ce | 1432 | urb->finished = 1; |
3e326ece MK |
1433 | stat = USB_ST_CRC_ERR; |
1434 | break; | |
1435 | } | |
1436 | } | |
3e326ece MK |
1437 | |
1438 | dev->status = stat; | |
522c9564 | 1439 | dev->act_len = urb->actual_length; |
3e326ece MK |
1440 | |
1441 | #ifdef DEBUG | |
c5613df5 | 1442 | pkt_print(ohci, urb, dev, pipe, buffer, transfer_len, |
6f5794a6 | 1443 | setup, "RET(ctlr)", usb_pipein(pipe)); |
3e326ece | 1444 | #else |
5b84dd67 | 1445 | mdelay(1); |
3e326ece MK |
1446 | #endif |
1447 | ||
1448 | /* free TDs in urb_priv */ | |
48867208 | 1449 | if (!usb_pipeint(pipe)) |
6f5794a6 | 1450 | urb_free_priv(urb); |
3e326ece MK |
1451 | return 0; |
1452 | } | |
1453 | ||
1454 | /* submit routines called from usb.c */ | |
1455 | int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer, | |
1456 | int transfer_len) | |
1457 | { | |
1458 | info("submit_bulk_msg"); | |
c5613df5 HG |
1459 | return submit_common_msg(&gohci, dev, pipe, buffer, transfer_len, |
1460 | NULL, 0); | |
1461 | } | |
1462 | ||
1463 | int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer, | |
1464 | int transfer_len, int interval) | |
1465 | { | |
1466 | info("submit_int_msg"); | |
1467 | return submit_common_msg(&gohci, dev, pipe, buffer, transfer_len, NULL, | |
1468 | interval); | |
3e326ece MK |
1469 | } |
1470 | ||
c5613df5 HG |
1471 | static int _ohci_submit_control_msg(ohci_t *ohci, struct usb_device *dev, |
1472 | unsigned long pipe, void *buffer, int transfer_len, | |
1473 | struct devrequest *setup) | |
3e326ece MK |
1474 | { |
1475 | int maxsize = usb_maxpacket(dev, pipe); | |
1476 | ||
1477 | info("submit_control_msg"); | |
1478 | #ifdef DEBUG | |
c5613df5 | 1479 | pkt_print(ohci, NULL, dev, pipe, buffer, transfer_len, |
6f5794a6 | 1480 | setup, "SUB", usb_pipein(pipe)); |
3e326ece | 1481 | #else |
5b84dd67 | 1482 | mdelay(1); |
3e326ece MK |
1483 | #endif |
1484 | if (!maxsize) { | |
1485 | err("submit_control_message: pipesize for pipe %lx is zero", | |
1486 | pipe); | |
1487 | return -1; | |
1488 | } | |
c5613df5 HG |
1489 | if (((pipe >> 8) & 0x7f) == ohci->rh.devnum) { |
1490 | ohci->rh.dev = dev; | |
3e326ece | 1491 | /* root hub - redirect */ |
c5613df5 HG |
1492 | return ohci_submit_rh_msg(ohci, dev, pipe, buffer, |
1493 | transfer_len, setup); | |
3e326ece MK |
1494 | } |
1495 | ||
c5613df5 HG |
1496 | return submit_common_msg(ohci, dev, pipe, buffer, transfer_len, |
1497 | setup, 0); | |
3e326ece MK |
1498 | } |
1499 | ||
1500 | /*-------------------------------------------------------------------------* | |
1501 | * HC functions | |
1502 | *-------------------------------------------------------------------------*/ | |
1503 | ||
1504 | /* reset the HC and BUS */ | |
1505 | ||
6f5794a6 | 1506 | static int hc_reset(ohci_t *ohci) |
3e326ece | 1507 | { |
e90fb6af YT |
1508 | #ifdef CONFIG_PCI_EHCI_DEVNO |
1509 | pci_dev_t pdev; | |
1510 | #endif | |
3e326ece MK |
1511 | int timeout = 30; |
1512 | int smm_timeout = 50; /* 0,5 sec */ | |
1513 | ||
1514 | dbg("%s\n", __FUNCTION__); | |
1515 | ||
e90fb6af YT |
1516 | #ifdef CONFIG_PCI_EHCI_DEVNO |
1517 | /* | |
1518 | * Some multi-function controllers (e.g. ISP1562) allow root hub | |
1519 | * resetting via EHCI registers only. | |
1520 | */ | |
1521 | pdev = pci_find_devices(ehci_pci_ids, CONFIG_PCI_EHCI_DEVNO); | |
1522 | if (pdev != -1) { | |
1523 | u32 base; | |
1524 | int timeout = 1000; | |
1525 | ||
1526 | pci_read_config_dword(pdev, PCI_BASE_ADDRESS_0, &base); | |
a5496a18 BB |
1527 | base += EHCI_USBCMD_OFF; |
1528 | ohci_writel(ohci_readl(base) | EHCI_USBCMD_HCRESET, base); | |
e90fb6af | 1529 | |
a5496a18 | 1530 | while (ohci_readl(base) & EHCI_USBCMD_HCRESET) { |
e90fb6af YT |
1531 | if (timeout-- <= 0) { |
1532 | printf("USB RootHub reset timed out!"); | |
1533 | break; | |
1534 | } | |
1535 | udelay(1); | |
1536 | } | |
1537 | } else | |
1538 | printf("No EHCI func at %d index!\n", CONFIG_PCI_EHCI_DEVNO); | |
1539 | #endif | |
a5496a18 BB |
1540 | if (ohci_readl(&ohci->regs->control) & OHCI_CTRL_IR) { |
1541 | /* SMM owns the HC, request ownership */ | |
1542 | ohci_writel(OHCI_OCR, &ohci->regs->cmdstatus); | |
3e326ece | 1543 | info("USB HC TakeOver from SMM"); |
a5496a18 | 1544 | while (ohci_readl(&ohci->regs->control) & OHCI_CTRL_IR) { |
5b84dd67 | 1545 | mdelay(10); |
3e326ece MK |
1546 | if (--smm_timeout == 0) { |
1547 | err("USB HC TakeOver failed!"); | |
1548 | return -1; | |
1549 | } | |
1550 | } | |
1551 | } | |
1552 | ||
1553 | /* Disable HC interrupts */ | |
a5496a18 | 1554 | ohci_writel(OHCI_INTR_MIE, &ohci->regs->intrdisable); |
3e326ece MK |
1555 | |
1556 | dbg("USB HC reset_hc usb-%s: ctrl = 0x%X ;\n", | |
1557 | ohci->slot_name, | |
a5496a18 | 1558 | ohci_readl(&ohci->regs->control)); |
3e326ece MK |
1559 | |
1560 | /* Reset USB (needed by some controllers) */ | |
53e336e9 | 1561 | ohci->hc_control = 0; |
a5496a18 | 1562 | ohci_writel(ohci->hc_control, &ohci->regs->control); |
3e326ece MK |
1563 | |
1564 | /* HC Reset requires max 10 us delay */ | |
a5496a18 BB |
1565 | ohci_writel(OHCI_HCR, &ohci->regs->cmdstatus); |
1566 | while ((ohci_readl(&ohci->regs->cmdstatus) & OHCI_HCR) != 0) { | |
3e326ece MK |
1567 | if (--timeout == 0) { |
1568 | err("USB HC reset timed out!"); | |
1569 | return -1; | |
1570 | } | |
6f5794a6 | 1571 | udelay(1); |
3e326ece MK |
1572 | } |
1573 | return 0; | |
1574 | } | |
1575 | ||
1576 | /*-------------------------------------------------------------------------*/ | |
1577 | ||
1578 | /* Start an OHCI controller, set the BUS operational | |
1579 | * enable interrupts | |
1580 | * connect the virtual root hub */ | |
1581 | ||
6f5794a6 | 1582 | static int hc_start(ohci_t *ohci) |
3e326ece MK |
1583 | { |
1584 | __u32 mask; | |
1585 | unsigned int fminterval; | |
1586 | ||
1587 | ohci->disabled = 1; | |
1588 | ||
1589 | /* Tell the controller where the control and bulk lists are | |
1590 | * The lists are empty now. */ | |
1591 | ||
a5496a18 BB |
1592 | ohci_writel(0, &ohci->regs->ed_controlhead); |
1593 | ohci_writel(0, &ohci->regs->ed_bulkhead); | |
3e326ece | 1594 | |
a5496a18 BB |
1595 | ohci_writel((__u32)ohci->hcca, |
1596 | &ohci->regs->hcca); /* reset clears this */ | |
3e326ece MK |
1597 | |
1598 | fminterval = 0x2edf; | |
a5496a18 | 1599 | ohci_writel((fminterval * 9) / 10, &ohci->regs->periodicstart); |
3e326ece | 1600 | fminterval |= ((((fminterval - 210) * 6) / 7) << 16); |
a5496a18 BB |
1601 | ohci_writel(fminterval, &ohci->regs->fminterval); |
1602 | ohci_writel(0x628, &ohci->regs->lsthresh); | |
3e326ece MK |
1603 | |
1604 | /* start controller operations */ | |
1605 | ohci->hc_control = OHCI_CONTROL_INIT | OHCI_USB_OPER; | |
1606 | ohci->disabled = 0; | |
a5496a18 | 1607 | ohci_writel(ohci->hc_control, &ohci->regs->control); |
3e326ece MK |
1608 | |
1609 | /* disable all interrupts */ | |
1610 | mask = (OHCI_INTR_SO | OHCI_INTR_WDH | OHCI_INTR_SF | OHCI_INTR_RD | | |
1611 | OHCI_INTR_UE | OHCI_INTR_FNO | OHCI_INTR_RHSC | | |
1612 | OHCI_INTR_OC | OHCI_INTR_MIE); | |
a5496a18 | 1613 | ohci_writel(mask, &ohci->regs->intrdisable); |
3e326ece MK |
1614 | /* clear all interrupts */ |
1615 | mask &= ~OHCI_INTR_MIE; | |
a5496a18 | 1616 | ohci_writel(mask, &ohci->regs->intrstatus); |
3e326ece MK |
1617 | /* Choose the interrupts we care about now - but w/o MIE */ |
1618 | mask = OHCI_INTR_RHSC | OHCI_INTR_UE | OHCI_INTR_WDH | OHCI_INTR_SO; | |
a5496a18 | 1619 | ohci_writel(mask, &ohci->regs->intrenable); |
3e326ece MK |
1620 | |
1621 | #ifdef OHCI_USE_NPS | |
1622 | /* required for AMD-756 and some Mac platforms */ | |
a5496a18 | 1623 | ohci_writel((roothub_a(ohci) | RH_A_NPS) & ~RH_A_PSM, |
3e326ece | 1624 | &ohci->regs->roothub.a); |
a5496a18 | 1625 | ohci_writel(RH_HS_LPSC, &ohci->regs->roothub.status); |
3e326ece MK |
1626 | #endif /* OHCI_USE_NPS */ |
1627 | ||
3e326ece | 1628 | /* POTPGT delay is bits 24-31, in 2 ms units. */ |
6f5794a6 | 1629 | mdelay((roothub_a(ohci) >> 23) & 0x1fe); |
3e326ece MK |
1630 | |
1631 | /* connect the virtual root hub */ | |
1632 | ohci->rh.devnum = 0; | |
1633 | ||
1634 | return 0; | |
1635 | } | |
1636 | ||
1637 | /*-------------------------------------------------------------------------*/ | |
1638 | ||
1639 | /* an interrupt happens */ | |
1640 | ||
c5613df5 | 1641 | static int hc_interrupt(ohci_t *ohci) |
3e326ece | 1642 | { |
3e326ece MK |
1643 | struct ohci_regs *regs = ohci->regs; |
1644 | int ints; | |
1645 | int stat = -1; | |
1646 | ||
ddf83a2f | 1647 | if ((ohci->hcca->done_head != 0) && |
6f5794a6 | 1648 | !(m32_swap(ohci->hcca->done_head) & 0x01)) { |
ddf83a2f | 1649 | ints = OHCI_INTR_WDH; |
6f5794a6 | 1650 | } else { |
a5496a18 | 1651 | ints = ohci_readl(®s->intrstatus); |
6f5794a6 RB |
1652 | if (ints == ~(u32)0) { |
1653 | ohci->disabled++; | |
1654 | err("%s device removed!", ohci->slot_name); | |
1655 | return -1; | |
1656 | } else { | |
a5496a18 | 1657 | ints &= ohci_readl(®s->intrenable); |
6f5794a6 RB |
1658 | if (ints == 0) { |
1659 | dbg("hc_interrupt: returning..\n"); | |
1660 | return 0xff; | |
1661 | } | |
1662 | } | |
ddf83a2f | 1663 | } |
ae79f606 | 1664 | |
6f5794a6 RB |
1665 | /* dbg("Interrupt: %x frame: %x", ints, |
1666 | le16_to_cpu(ohci->hcca->frame_no)); */ | |
3e326ece | 1667 | |
6f5794a6 | 1668 | if (ints & OHCI_INTR_RHSC) |
ddf83a2f | 1669 | stat = 0xff; |
3e326ece MK |
1670 | |
1671 | if (ints & OHCI_INTR_UE) { | |
1672 | ohci->disabled++; | |
6f5794a6 | 1673 | err("OHCI Unrecoverable Error, controller usb-%s disabled", |
3e326ece MK |
1674 | ohci->slot_name); |
1675 | /* e.g. due to PCI Master/Target Abort */ | |
1676 | ||
1677 | #ifdef DEBUG | |
6f5794a6 | 1678 | ohci_dump(ohci, 1); |
3e326ece | 1679 | #else |
5b84dd67 | 1680 | mdelay(1); |
3e326ece MK |
1681 | #endif |
1682 | /* FIXME: be optimistic, hope that bug won't repeat often. */ | |
1683 | /* Make some non-interrupt context restart the controller. */ | |
1684 | /* Count and limit the retries though; either hardware or */ | |
1685 | /* software errors can go forever... */ | |
6f5794a6 | 1686 | hc_reset(ohci); |
3e326ece MK |
1687 | return -1; |
1688 | } | |
1689 | ||
1690 | if (ints & OHCI_INTR_WDH) { | |
5b84dd67 | 1691 | mdelay(1); |
a5496a18 BB |
1692 | ohci_writel(OHCI_INTR_WDH, ®s->intrdisable); |
1693 | (void)ohci_readl(®s->intrdisable); /* flush */ | |
c5613df5 | 1694 | stat = dl_done_list(ohci); |
a5496a18 BB |
1695 | ohci_writel(OHCI_INTR_WDH, ®s->intrenable); |
1696 | (void)ohci_readl(®s->intrdisable); /* flush */ | |
3e326ece MK |
1697 | } |
1698 | ||
1699 | if (ints & OHCI_INTR_SO) { | |
1700 | dbg("USB Schedule overrun\n"); | |
a5496a18 | 1701 | ohci_writel(OHCI_INTR_SO, ®s->intrenable); |
3e326ece MK |
1702 | stat = -1; |
1703 | } | |
1704 | ||
1705 | /* FIXME: this assumes SOF (1/ms) interrupts don't get lost... */ | |
1706 | if (ints & OHCI_INTR_SF) { | |
6f5794a6 | 1707 | unsigned int frame = m16_swap(ohci->hcca->frame_no) & 1; |
5b84dd67 | 1708 | mdelay(1); |
a5496a18 | 1709 | ohci_writel(OHCI_INTR_SF, ®s->intrdisable); |
3e326ece | 1710 | if (ohci->ed_rm_list[frame] != NULL) |
a5496a18 | 1711 | ohci_writel(OHCI_INTR_SF, ®s->intrenable); |
3e326ece MK |
1712 | stat = 0xff; |
1713 | } | |
1714 | ||
a5496a18 | 1715 | ohci_writel(ints, ®s->intrstatus); |
3e326ece MK |
1716 | return stat; |
1717 | } | |
1718 | ||
1719 | /*-------------------------------------------------------------------------*/ | |
1720 | ||
1721 | /*-------------------------------------------------------------------------*/ | |
1722 | ||
1723 | /* De-allocate all resources.. */ | |
1724 | ||
6f5794a6 | 1725 | static void hc_release_ohci(ohci_t *ohci) |
3e326ece | 1726 | { |
6f5794a6 | 1727 | dbg("USB HC release ohci usb-%s", ohci->slot_name); |
3e326ece MK |
1728 | |
1729 | if (!ohci->disabled) | |
6f5794a6 | 1730 | hc_reset(ohci); |
3e326ece MK |
1731 | } |
1732 | ||
1733 | /*-------------------------------------------------------------------------*/ | |
1734 | ||
1735 | /* | |
1736 | * low level initalisation routine, called from usb.c | |
1737 | */ | |
1738 | static char ohci_inited = 0; | |
1739 | ||
06d513ec | 1740 | int usb_lowlevel_init(int index, enum usb_init_type init, void **controller) |
3e326ece | 1741 | { |
4dae14ce ZW |
1742 | #ifdef CONFIG_PCI_OHCI |
1743 | pci_dev_t pdev; | |
1744 | #endif | |
24e37645 | 1745 | |
6d0f6bcf | 1746 | #ifdef CONFIG_SYS_USB_OHCI_CPU_INIT |
24e37645 | 1747 | /* cpu dependant init */ |
6f5794a6 | 1748 | if (usb_cpu_init()) |
3e326ece | 1749 | return -1; |
24e37645 | 1750 | #endif |
3e326ece | 1751 | |
6d0f6bcf | 1752 | #ifdef CONFIG_SYS_USB_OHCI_BOARD_INIT |
24e37645 | 1753 | /* board dependant init */ |
16297cfb | 1754 | if (board_usb_init(index, USB_INIT_HOST)) |
24e37645 MK |
1755 | return -1; |
1756 | #endif | |
6f5794a6 | 1757 | memset(&gohci, 0, sizeof(ohci_t)); |
3e326ece MK |
1758 | |
1759 | /* align the storage */ | |
1760 | if ((__u32)&ghcca[0] & 0xff) { | |
1761 | err("HCCA not aligned!!"); | |
1762 | return -1; | |
1763 | } | |
1764 | phcca = &ghcca[0]; | |
1765 | info("aligned ghcca %p", phcca); | |
1766 | memset(&ohci_dev, 0, sizeof(struct ohci_device)); | |
1767 | if ((__u32)&ohci_dev.ed[0] & 0x7) { | |
1768 | err("EDs not aligned!!"); | |
1769 | return -1; | |
1770 | } | |
1771 | memset(gtd, 0, sizeof(td_t) * (NUM_TD + 1)); | |
1772 | if ((__u32)gtd & 0x7) { | |
1773 | err("TDs not aligned!!"); | |
1774 | return -1; | |
1775 | } | |
1776 | ptd = gtd; | |
1777 | gohci.hcca = phcca; | |
6f5794a6 | 1778 | memset(phcca, 0, sizeof(struct ohci_hcca)); |
3e326ece MK |
1779 | |
1780 | gohci.disabled = 1; | |
1781 | gohci.sleeping = 0; | |
1782 | gohci.irq = -1; | |
4dae14ce | 1783 | #ifdef CONFIG_PCI_OHCI |
477434c6 | 1784 | pdev = pci_find_devices(ohci_pci_ids, CONFIG_PCI_OHCI_DEVNO); |
4dae14ce ZW |
1785 | |
1786 | if (pdev != -1) { | |
1787 | u16 vid, did; | |
1788 | u32 base; | |
1789 | pci_read_config_word(pdev, PCI_VENDOR_ID, &vid); | |
1790 | pci_read_config_word(pdev, PCI_DEVICE_ID, &did); | |
1791 | printf("OHCI pci controller (%04x, %04x) found @(%d:%d:%d)\n", | |
1792 | vid, did, (pdev >> 16) & 0xff, | |
1793 | (pdev >> 11) & 0x1f, (pdev >> 8) & 0x7); | |
1794 | pci_read_config_dword(pdev, PCI_BASE_ADDRESS_0, &base); | |
1795 | printf("OHCI regs address 0x%08x\n", base); | |
1796 | gohci.regs = (struct ohci_regs *)base; | |
1797 | } else | |
1798 | return -1; | |
1799 | #else | |
6d0f6bcf | 1800 | gohci.regs = (struct ohci_regs *)CONFIG_SYS_USB_OHCI_REGS_BASE; |
4dae14ce | 1801 | #endif |
3e326ece MK |
1802 | |
1803 | gohci.flags = 0; | |
6d0f6bcf | 1804 | gohci.slot_name = CONFIG_SYS_USB_OHCI_SLOT_NAME; |
3e326ece MK |
1805 | |
1806 | if (hc_reset (&gohci) < 0) { | |
1807 | hc_release_ohci (&gohci); | |
1808 | err ("can't reset usb-%s", gohci.slot_name); | |
6d0f6bcf | 1809 | #ifdef CONFIG_SYS_USB_OHCI_BOARD_INIT |
24e37645 | 1810 | /* board dependant cleanup */ |
16297cfb | 1811 | board_usb_cleanup(index, USB_INIT_HOST); |
24e37645 MK |
1812 | #endif |
1813 | ||
6d0f6bcf | 1814 | #ifdef CONFIG_SYS_USB_OHCI_CPU_INIT |
24e37645 | 1815 | /* cpu dependant cleanup */ |
ddf83a2f | 1816 | usb_cpu_init_fail(); |
24e37645 | 1817 | #endif |
3e326ece MK |
1818 | return -1; |
1819 | } | |
1820 | ||
6f5794a6 RB |
1821 | if (hc_start(&gohci) < 0) { |
1822 | err("can't start usb-%s", gohci.slot_name); | |
1823 | hc_release_ohci(&gohci); | |
3e326ece | 1824 | /* Initialization failed */ |
6d0f6bcf | 1825 | #ifdef CONFIG_SYS_USB_OHCI_BOARD_INIT |
24e37645 MK |
1826 | /* board dependant cleanup */ |
1827 | usb_board_stop(); | |
1828 | #endif | |
1829 | ||
6d0f6bcf | 1830 | #ifdef CONFIG_SYS_USB_OHCI_CPU_INIT |
24e37645 MK |
1831 | /* cpu dependant cleanup */ |
1832 | usb_cpu_stop(); | |
1833 | #endif | |
3e326ece MK |
1834 | return -1; |
1835 | } | |
1836 | ||
1837 | #ifdef DEBUG | |
6f5794a6 | 1838 | ohci_dump(&gohci, 1); |
3e326ece | 1839 | #else |
5b84dd67 | 1840 | mdelay(1); |
3e326ece MK |
1841 | #endif |
1842 | ohci_inited = 1; | |
1843 | return 0; | |
1844 | } | |
1845 | ||
c7e3b2b5 | 1846 | int usb_lowlevel_stop(int index) |
3e326ece MK |
1847 | { |
1848 | /* this gets called really early - before the controller has */ | |
1849 | /* even been initialized! */ | |
1850 | if (!ohci_inited) | |
1851 | return 0; | |
1852 | /* TODO release any interrupts, etc. */ | |
1853 | /* call hc_release_ohci() here ? */ | |
6f5794a6 | 1854 | hc_reset(&gohci); |
3e326ece | 1855 | |
6d0f6bcf | 1856 | #ifdef CONFIG_SYS_USB_OHCI_BOARD_INIT |
3e326ece | 1857 | /* board dependant cleanup */ |
6f5794a6 | 1858 | if (usb_board_stop()) |
3e326ece | 1859 | return -1; |
24e37645 MK |
1860 | #endif |
1861 | ||
6d0f6bcf | 1862 | #ifdef CONFIG_SYS_USB_OHCI_CPU_INIT |
24e37645 | 1863 | /* cpu dependant cleanup */ |
6f5794a6 | 1864 | if (usb_cpu_stop()) |
24e37645 MK |
1865 | return -1; |
1866 | #endif | |
eba1f2fc RB |
1867 | /* This driver is no longer initialised. It needs a new low-level |
1868 | * init (board/cpu) before it can be used again. */ | |
1869 | ohci_inited = 0; | |
3e326ece MK |
1870 | return 0; |
1871 | } | |
c5613df5 HG |
1872 | |
1873 | int submit_control_msg(struct usb_device *dev, unsigned long pipe, | |
1874 | void *buffer, int transfer_len, struct devrequest *setup) | |
1875 | { | |
1876 | return _ohci_submit_control_msg(&gohci, dev, pipe, buffer, | |
1877 | transfer_len, setup); | |
1878 | } |