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96b8a054 | 1 | /* |
e8d3ca8b | 2 | * Copyright (C) Freescale Semiconductor, Inc. 2006, 2010. |
96b8a054 SW |
3 | * |
4 | * See file CREDITS for list of people who contributed to this | |
5 | * project. | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU General Public License as | |
9 | * published by the Free Software Foundation; either version 2 of | |
10 | * the License, or (at your option) any later version. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program; if not, write to the Free Software | |
19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
20 | * MA 02111-1307 USA | |
96b8a054 SW |
21 | */ |
22 | /* | |
23 | * mpc8313epb board configuration file | |
24 | */ | |
25 | ||
26 | #ifndef __CONFIG_H | |
27 | #define __CONFIG_H | |
28 | ||
29 | /* | |
30 | * High Level Configuration Options | |
31 | */ | |
32 | #define CONFIG_E300 1 | |
0f898604 | 33 | #define CONFIG_MPC83xx 1 |
2c7920af | 34 | #define CONFIG_MPC831x 1 |
96b8a054 SW |
35 | #define CONFIG_MPC8313 1 |
36 | #define CONFIG_MPC8313ERDB 1 | |
37 | ||
f1c574d4 SW |
38 | #define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10) |
39 | #define CONFIG_SYS_NAND_U_BOOT_DST 0x00100000 | |
40 | #define CONFIG_SYS_NAND_U_BOOT_START 0x00100100 | |
41 | #define CONFIG_SYS_NAND_U_BOOT_OFFS 16384 | |
42 | #define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000 | |
43 | #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000) | |
44 | ||
45 | #ifdef CONFIG_NAND_U_BOOT | |
46 | #define CONFIG_SYS_TEXT_BASE 0x00100000 /* CONFIG_SYS_NAND_U_BOOT_DST */ | |
47 | #define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000 | |
48 | #ifdef CONFIG_NAND_SPL | |
49 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */ | |
50 | #endif /* CONFIG_NAND_SPL */ | |
51 | #endif /* CONFIG_NAND_U_BOOT */ | |
52 | ||
2ae18241 WD |
53 | #ifndef CONFIG_SYS_TEXT_BASE |
54 | #define CONFIG_SYS_TEXT_BASE 0xFE000000 | |
55 | #endif | |
56 | ||
f1c574d4 SW |
57 | #ifndef CONFIG_SYS_MONITOR_BASE |
58 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ | |
59 | #endif | |
60 | ||
96b8a054 | 61 | #define CONFIG_PCI |
0914f483 | 62 | #define CONFIG_FSL_ELBC 1 |
96b8a054 | 63 | |
89c7784e TT |
64 | #define CONFIG_MISC_INIT_R |
65 | ||
66 | /* | |
67 | * On-board devices | |
4ce1e23b YS |
68 | * |
69 | * TSEC1 is VSC switch | |
70 | * TSEC2 is SoC TSEC | |
89c7784e TT |
71 | */ |
72 | #define CONFIG_VSC7385_ENET | |
4ce1e23b | 73 | #define CONFIG_TSEC2 |
89c7784e | 74 | |
6d0f6bcf | 75 | #ifdef CONFIG_SYS_66MHZ |
5c5d3242 | 76 | #define CONFIG_83XX_CLKIN 66666667 /* in Hz */ |
6d0f6bcf | 77 | #elif defined(CONFIG_SYS_33MHZ) |
5c5d3242 | 78 | #define CONFIG_83XX_CLKIN 33333333 /* in Hz */ |
96b8a054 SW |
79 | #else |
80 | #error Unknown oscillator frequency. | |
81 | #endif | |
82 | ||
83 | #define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN | |
84 | ||
85 | #define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */ | |
86 | ||
6d0f6bcf | 87 | #define CONFIG_SYS_IMMR 0xE0000000 |
96b8a054 | 88 | |
e4c09508 | 89 | #if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) |
6d0f6bcf | 90 | #define CONFIG_DEFAULT_IMMR CONFIG_SYS_IMMR |
e4c09508 SW |
91 | #endif |
92 | ||
6d0f6bcf JCPV |
93 | #define CONFIG_SYS_MEMTEST_START 0x00001000 |
94 | #define CONFIG_SYS_MEMTEST_END 0x07f00000 | |
96b8a054 SW |
95 | |
96 | /* Early revs of this board will lock up hard when attempting | |
97 | * to access the PMC registers, unless a JTAG debugger is | |
98 | * connected, or some resistor modifications are made. | |
99 | */ | |
6d0f6bcf | 100 | #define CONFIG_SYS_8313ERDB_BROKEN_PMC 1 |
96b8a054 | 101 | |
6d0f6bcf JCPV |
102 | #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */ |
103 | #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */ | |
96b8a054 | 104 | |
89c7784e TT |
105 | /* |
106 | * Device configurations | |
107 | */ | |
108 | ||
109 | /* Vitesse 7385 */ | |
110 | ||
111 | #ifdef CONFIG_VSC7385_ENET | |
112 | ||
4ce1e23b | 113 | #define CONFIG_TSEC1 |
89c7784e TT |
114 | |
115 | /* The flash address and size of the VSC7385 firmware image */ | |
116 | #define CONFIG_VSC7385_IMAGE 0xFE7FE000 | |
117 | #define CONFIG_VSC7385_IMAGE_SIZE 8192 | |
118 | ||
119 | #endif | |
120 | ||
96b8a054 SW |
121 | /* |
122 | * DDR Setup | |
123 | */ | |
6d0f6bcf JCPV |
124 | #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/ |
125 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE | |
126 | #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE | |
96b8a054 SW |
127 | |
128 | /* | |
129 | * Manually set up DDR parameters, as this board does not | |
130 | * seem to have the SPD connected to I2C. | |
131 | */ | |
6d0f6bcf JCPV |
132 | #define CONFIG_SYS_DDR_SIZE 128 /* MB */ |
133 | #define CONFIG_SYS_DDR_CONFIG ( CSCONFIG_EN \ | |
e1d8ed2c | 134 | | 0x00010000 /* TODO */ \ |
96b8a054 | 135 | | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10 ) |
e1d8ed2c | 136 | /* 0x80010102 */ |
96b8a054 | 137 | |
6d0f6bcf JCPV |
138 | #define CONFIG_SYS_DDR_TIMING_3 0x00000000 |
139 | #define CONFIG_SYS_DDR_TIMING_0 ( ( 0 << TIMING_CFG0_RWT_SHIFT ) \ | |
96b8a054 SW |
140 | | ( 0 << TIMING_CFG0_WRT_SHIFT ) \ |
141 | | ( 0 << TIMING_CFG0_RRT_SHIFT ) \ | |
142 | | ( 0 << TIMING_CFG0_WWT_SHIFT ) \ | |
143 | | ( 2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT ) \ | |
144 | | ( 2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT ) \ | |
145 | | ( 8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT ) \ | |
146 | | ( 2 << TIMING_CFG0_MRS_CYC_SHIFT ) ) | |
147 | /* 0x00220802 */ | |
6d0f6bcf | 148 | #define CONFIG_SYS_DDR_TIMING_1 ( ( 3 << TIMING_CFG1_PRETOACT_SHIFT ) \ |
e1d8ed2c | 149 | | ( 8 << TIMING_CFG1_ACTTOPRE_SHIFT ) \ |
96b8a054 SW |
150 | | ( 3 << TIMING_CFG1_ACTTORW_SHIFT ) \ |
151 | | ( 5 << TIMING_CFG1_CASLAT_SHIFT ) \ | |
e1d8ed2c | 152 | | (10 << TIMING_CFG1_REFREC_SHIFT ) \ |
96b8a054 SW |
153 | | ( 3 << TIMING_CFG1_WRREC_SHIFT ) \ |
154 | | ( 2 << TIMING_CFG1_ACTTOACT_SHIFT ) \ | |
155 | | ( 2 << TIMING_CFG1_WRTORD_SHIFT ) ) | |
e1d8ed2c | 156 | /* 0x3835a322 */ |
6d0f6bcf | 157 | #define CONFIG_SYS_DDR_TIMING_2 ( ( 1 << TIMING_CFG2_ADD_LAT_SHIFT ) \ |
e1d8ed2c | 158 | | ( 5 << TIMING_CFG2_CPO_SHIFT ) \ |
96b8a054 SW |
159 | | ( 2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT ) \ |
160 | | ( 2 << TIMING_CFG2_RD_TO_PRE_SHIFT ) \ | |
161 | | ( 2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT ) \ | |
162 | | ( 3 << TIMING_CFG2_CKE_PLS_SHIFT ) \ | |
e1d8ed2c PA |
163 | | ( 6 << TIMING_CFG2_FOUR_ACT_SHIFT) ) |
164 | /* 0x129048c6 */ /* P9-45,may need tuning */ | |
6d0f6bcf | 165 | #define CONFIG_SYS_DDR_INTERVAL ( ( 1296 << SDRAM_INTERVAL_REFINT_SHIFT ) \ |
e1d8ed2c PA |
166 | | ( 1280 << SDRAM_INTERVAL_BSTOPRE_SHIFT ) ) |
167 | /* 0x05100500 */ | |
96b8a054 | 168 | #if defined(CONFIG_DDR_2T_TIMING) |
6d0f6bcf | 169 | #define CONFIG_SYS_SDRAM_CFG ( SDRAM_CFG_SREN \ |
bbea46f7 | 170 | | SDRAM_CFG_SDRAM_TYPE_DDR2 \ |
96b8a054 SW |
171 | | SDRAM_CFG_2T_EN \ |
172 | | SDRAM_CFG_DBW_32 ) | |
173 | #else | |
6d0f6bcf | 174 | #define CONFIG_SYS_SDRAM_CFG ( SDRAM_CFG_SREN \ |
bbea46f7 | 175 | | SDRAM_CFG_SDRAM_TYPE_DDR2 \ |
96b8a054 SW |
176 | | SDRAM_CFG_32_BE ) |
177 | /* 0x43080000 */ | |
178 | #endif | |
6d0f6bcf | 179 | #define CONFIG_SYS_SDRAM_CFG2 0x00401000 |
96b8a054 | 180 | /* set burst length to 8 for 32-bit data path */ |
6d0f6bcf | 181 | #define CONFIG_SYS_DDR_MODE ( ( 0x4448 << SDRAM_MODE_ESD_SHIFT ) \ |
e1d8ed2c PA |
182 | | ( 0x0632 << SDRAM_MODE_SD_SHIFT ) ) |
183 | /* 0x44480632 */ | |
6d0f6bcf | 184 | #define CONFIG_SYS_DDR_MODE_2 0x8000C000 |
96b8a054 | 185 | |
6d0f6bcf | 186 | #define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 |
96b8a054 | 187 | /*0x02000000*/ |
6d0f6bcf | 188 | #define CONFIG_SYS_DDRCDR_VALUE ( DDRCDR_EN \ |
96b8a054 SW |
189 | | DDRCDR_PZ_NOMZ \ |
190 | | DDRCDR_NZ_NOMZ \ | |
191 | | DDRCDR_M_ODR ) | |
192 | ||
193 | /* | |
194 | * FLASH on the Local Bus | |
195 | */ | |
6d0f6bcf | 196 | #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ |
00b1883a | 197 | #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ |
6d0f6bcf JCPV |
198 | #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */ |
199 | #define CONFIG_SYS_FLASH_SIZE 8 /* flash size in MB */ | |
200 | #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */ | |
201 | #define CONFIG_SYS_FLASH_EMPTY_INFO /* display empty sectors */ | |
202 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* buffer up multiple bytes */ | |
96b8a054 | 203 | |
6d0f6bcf | 204 | #define CONFIG_SYS_NOR_BR_PRELIM (CONFIG_SYS_FLASH_BASE | /* flash Base address */ \ |
a7676ea7 WD |
205 | (2 << BR_PS_SHIFT) | /* 16 bit port size */ \ |
206 | BR_V) /* valid */ | |
6d0f6bcf | 207 | #define CONFIG_SYS_NOR_OR_PRELIM ( 0xFF800000 /* 8 MByte */ \ |
96b8a054 SW |
208 | | OR_GPCM_XACS \ |
209 | | OR_GPCM_SCY_9 \ | |
210 | | OR_GPCM_EHTR \ | |
211 | | OR_GPCM_EAD ) | |
212 | /* 0xFF006FF7 TODO SLOW 16 MB flash size */ | |
6d0f6bcf JCPV |
213 | #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE /* window base at flash base */ |
214 | #define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000017 /* 16 MB window size */ | |
96b8a054 | 215 | |
6d0f6bcf JCPV |
216 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ |
217 | #define CONFIG_SYS_MAX_FLASH_SECT 135 /* sectors per device */ | |
96b8a054 | 218 | |
6d0f6bcf JCPV |
219 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ |
220 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ | |
96b8a054 | 221 | |
6d0f6bcf JCPV |
222 | #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) && !defined(CONFIG_NAND_SPL) |
223 | #define CONFIG_SYS_RAMBOOT | |
96b8a054 SW |
224 | #endif |
225 | ||
6d0f6bcf JCPV |
226 | #define CONFIG_SYS_INIT_RAM_LOCK 1 |
227 | #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */ | |
553f0982 | 228 | #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/ |
96b8a054 | 229 | |
25ddd1fb | 230 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
6d0f6bcf | 231 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
96b8a054 | 232 | |
6d0f6bcf | 233 | /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */ |
4a9932a4 | 234 | #define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ |
6d0f6bcf | 235 | #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ |
96b8a054 SW |
236 | |
237 | /* | |
238 | * Local Bus LCRR and LBCR regs | |
239 | */ | |
c7190f02 KP |
240 | #define CONFIG_SYS_LCRR_EADC LCRR_EADC_1 |
241 | #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4 | |
6d0f6bcf | 242 | #define CONFIG_SYS_LBC_LBCR ( 0x00040000 /* TODO */ \ |
96b8a054 SW |
243 | | (0xFF << LBCR_BMT_SHIFT) \ |
244 | | 0xF ) /* 0x0004ff0f */ | |
245 | ||
6d0f6bcf | 246 | #define CONFIG_SYS_LBC_MRTPR 0x20000000 /*TODO */ /* LB refresh timer prescal, 266MHz/32 */ |
96b8a054 | 247 | |
7817cb20 | 248 | /* drivers/mtd/nand/nand.c */ |
e4c09508 | 249 | #ifdef CONFIG_NAND_SPL |
6d0f6bcf | 250 | #define CONFIG_SYS_NAND_BASE 0xFFF00000 |
e4c09508 | 251 | #else |
6d0f6bcf | 252 | #define CONFIG_SYS_NAND_BASE 0xE2800000 |
e4c09508 SW |
253 | #endif |
254 | ||
e8d3ca8b SW |
255 | #define CONFIG_MTD_DEVICE |
256 | #define CONFIG_MTD_PARTITION | |
257 | #define CONFIG_CMD_MTDPARTS | |
258 | #define MTDIDS_DEFAULT "nand0=e2800000.flash" | |
259 | #define MTDPARTS_DEFAULT \ | |
260 | "mtdparts=e0600000.flash:512k(uboot),128k(env),3m@1m(kernel),-(fs)" | |
261 | ||
6d0f6bcf | 262 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 |
96b8a054 | 263 | #define CONFIG_MTD_NAND_VERIFY_WRITE |
acdab5c3 SW |
264 | #define CONFIG_CMD_NAND 1 |
265 | #define CONFIG_NAND_FSL_ELBC 1 | |
6d0f6bcf | 266 | #define CONFIG_SYS_NAND_BLOCK_SIZE 16384 |
e4c09508 | 267 | |
96b8a054 | 268 | |
6d0f6bcf | 269 | #define CONFIG_SYS_NAND_BR_PRELIM ( CONFIG_SYS_NAND_BASE \ |
a7676ea7 WD |
270 | | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ |
271 | | BR_PS_8 /* Port Size = 8 bit */ \ | |
272 | | BR_MS_FCM /* MSEL = FCM */ \ | |
273 | | BR_V ) /* valid */ | |
6d0f6bcf | 274 | #define CONFIG_SYS_NAND_OR_PRELIM ( 0xFFFF8000 /* length 32K */ \ |
96b8a054 SW |
275 | | OR_FCM_CSCT \ |
276 | | OR_FCM_CST \ | |
277 | | OR_FCM_CHT \ | |
278 | | OR_FCM_SCY_1 \ | |
279 | | OR_FCM_TRLX \ | |
280 | | OR_FCM_EHTR ) | |
281 | /* 0xFFFF8396 */ | |
e4c09508 SW |
282 | |
283 | #ifdef CONFIG_NAND_U_BOOT | |
6d0f6bcf JCPV |
284 | #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM |
285 | #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM | |
286 | #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NOR_BR_PRELIM | |
287 | #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NOR_OR_PRELIM | |
e4c09508 | 288 | #else |
6d0f6bcf JCPV |
289 | #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NOR_BR_PRELIM |
290 | #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NOR_OR_PRELIM | |
291 | #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM | |
292 | #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM | |
e4c09508 SW |
293 | #endif |
294 | ||
6d0f6bcf JCPV |
295 | #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE |
296 | #define CONFIG_SYS_LBLAWAR1_PRELIM 0x8000000E /* 32KB */ | |
96b8a054 | 297 | |
6d0f6bcf JCPV |
298 | #define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM |
299 | #define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM | |
e4c09508 | 300 | |
89c7784e | 301 | /* local bus read write buffer mapping */ |
6d0f6bcf JCPV |
302 | #define CONFIG_SYS_BR3_PRELIM 0xFA000801 /* map at 0xFA000000 */ |
303 | #define CONFIG_SYS_OR3_PRELIM 0xFFFF8FF7 /* 32kB */ | |
304 | #define CONFIG_SYS_LBLAWBAR3_PRELIM 0xFA000000 | |
305 | #define CONFIG_SYS_LBLAWAR3_PRELIM 0x8000000E /* 32KB */ | |
89c7784e TT |
306 | |
307 | /* Vitesse 7385 */ | |
308 | ||
6d0f6bcf | 309 | #define CONFIG_SYS_VSC7385_BASE 0xF0000000 |
96b8a054 | 310 | |
89c7784e TT |
311 | #ifdef CONFIG_VSC7385_ENET |
312 | ||
6d0f6bcf JCPV |
313 | #define CONFIG_SYS_BR2_PRELIM 0xf0000801 /* VSC7385 Base address */ |
314 | #define CONFIG_SYS_OR2_PRELIM 0xfffe09ff /* VSC7385, 128K bytes*/ | |
315 | #define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_VSC7385_BASE/* Access window base at VSC7385 base */ | |
316 | #define CONFIG_SYS_LBLAWAR2_PRELIM 0x80000010 /* Access window size 128K */ | |
96b8a054 | 317 | |
89c7784e | 318 | #endif |
96b8a054 SW |
319 | |
320 | /* pass open firmware flat tree */ | |
35cc4e48 | 321 | #define CONFIG_OF_LIBFDT 1 |
96b8a054 | 322 | #define CONFIG_OF_BOARD_SETUP 1 |
5b8bc606 | 323 | #define CONFIG_OF_STDOUT_VIA_ALIAS 1 |
96b8a054 SW |
324 | |
325 | /* | |
326 | * Serial Port | |
327 | */ | |
328 | #define CONFIG_CONS_INDEX 1 | |
6d0f6bcf JCPV |
329 | #define CONFIG_SYS_NS16550 |
330 | #define CONFIG_SYS_NS16550_SERIAL | |
331 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
96b8a054 | 332 | |
6d0f6bcf | 333 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
96b8a054 SW |
334 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} |
335 | ||
6d0f6bcf JCPV |
336 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) |
337 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) | |
96b8a054 SW |
338 | |
339 | /* Use the HUSH parser */ | |
6d0f6bcf JCPV |
340 | #define CONFIG_SYS_HUSH_PARSER |
341 | #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " | |
96b8a054 SW |
342 | |
343 | /* I2C */ | |
344 | #define CONFIG_HARD_I2C /* I2C with hardware support*/ | |
345 | #define CONFIG_FSL_I2C | |
346 | #define CONFIG_I2C_MULTI_BUS | |
6d0f6bcf JCPV |
347 | #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ |
348 | #define CONFIG_SYS_I2C_SLAVE 0x7F | |
349 | #define CONFIG_SYS_I2C_NOPROBES {{0,0x69}} /* Don't probe these addrs */ | |
350 | #define CONFIG_SYS_I2C_OFFSET 0x3000 | |
351 | #define CONFIG_SYS_I2C2_OFFSET 0x3100 | |
96b8a054 | 352 | |
96b8a054 SW |
353 | /* |
354 | * General PCI | |
355 | * Addresses are mapped 1-1. | |
356 | */ | |
6d0f6bcf JCPV |
357 | #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 |
358 | #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE | |
359 | #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ | |
360 | #define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000 | |
361 | #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE | |
362 | #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ | |
363 | #define CONFIG_SYS_PCI1_IO_BASE 0x00000000 | |
364 | #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000 | |
365 | #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ | |
96b8a054 SW |
366 | |
367 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ | |
6d0f6bcf | 368 | #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ |
96b8a054 SW |
369 | |
370 | /* | |
89c7784e | 371 | * TSEC |
96b8a054 SW |
372 | */ |
373 | #define CONFIG_TSEC_ENET /* TSEC ethernet support */ | |
374 | ||
89c7784e | 375 | #define CONFIG_GMII /* MII PHY management */ |
96b8a054 | 376 | |
89c7784e TT |
377 | #ifdef CONFIG_TSEC1 |
378 | #define CONFIG_HAS_ETH0 | |
255a3577 | 379 | #define CONFIG_TSEC1_NAME "TSEC0" |
6d0f6bcf | 380 | #define CONFIG_SYS_TSEC1_OFFSET 0x24000 |
89c7784e TT |
381 | #define TSEC1_PHY_ADDR 0x1c |
382 | #define TSEC1_FLAGS TSEC_GIGABIT | |
383 | #define TSEC1_PHYIDX 0 | |
384 | #endif | |
385 | ||
386 | #ifdef CONFIG_TSEC2 | |
387 | #define CONFIG_HAS_ETH1 | |
255a3577 | 388 | #define CONFIG_TSEC2_NAME "TSEC1" |
6d0f6bcf | 389 | #define CONFIG_SYS_TSEC2_OFFSET 0x25000 |
89c7784e TT |
390 | #define TSEC2_PHY_ADDR 4 |
391 | #define TSEC2_FLAGS TSEC_GIGABIT | |
392 | #define TSEC2_PHYIDX 0 | |
393 | #endif | |
394 | ||
96b8a054 SW |
395 | |
396 | /* Options are: TSEC[0-1] */ | |
397 | #define CONFIG_ETHPRIME "TSEC1" | |
398 | ||
399 | /* | |
400 | * Configure on-board RTC | |
401 | */ | |
402 | #define CONFIG_RTC_DS1337 | |
6d0f6bcf | 403 | #define CONFIG_SYS_I2C_RTC_ADDR 0x68 |
96b8a054 SW |
404 | |
405 | /* | |
406 | * Environment | |
407 | */ | |
e4c09508 | 408 | #if defined(CONFIG_NAND_U_BOOT) |
51bfee19 | 409 | #define CONFIG_ENV_IS_IN_NAND 1 |
0e8d1586 | 410 | #define CONFIG_ENV_OFFSET (512 * 1024) |
6d0f6bcf | 411 | #define CONFIG_ENV_SECT_SIZE CONFIG_SYS_NAND_BLOCK_SIZE |
0e8d1586 JCPV |
412 | #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE |
413 | #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE | |
414 | #define CONFIG_ENV_RANGE (CONFIG_ENV_SECT_SIZE * 4) | |
415 | #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE) | |
6d0f6bcf | 416 | #elif !defined(CONFIG_SYS_RAMBOOT) |
5a1aceb0 | 417 | #define CONFIG_ENV_IS_IN_FLASH 1 |
6d0f6bcf | 418 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) |
0e8d1586 JCPV |
419 | #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */ |
420 | #define CONFIG_ENV_SIZE 0x2000 | |
96b8a054 SW |
421 | |
422 | /* Address and size of Redundant Environment Sector */ | |
423 | #else | |
93f6d725 | 424 | #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ |
6d0f6bcf | 425 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) |
0e8d1586 | 426 | #define CONFIG_ENV_SIZE 0x2000 |
96b8a054 SW |
427 | #endif |
428 | ||
429 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
6d0f6bcf | 430 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
96b8a054 | 431 | |
079a136c JL |
432 | /* |
433 | * BOOTP options | |
434 | */ | |
435 | #define CONFIG_BOOTP_BOOTFILESIZE | |
436 | #define CONFIG_BOOTP_BOOTPATH | |
437 | #define CONFIG_BOOTP_GATEWAY | |
438 | #define CONFIG_BOOTP_HOSTNAME | |
439 | ||
440 | ||
8ea5499a JL |
441 | /* |
442 | * Command line configuration. | |
443 | */ | |
444 | #include <config_cmd_default.h> | |
96b8a054 | 445 | |
8ea5499a JL |
446 | #define CONFIG_CMD_PING |
447 | #define CONFIG_CMD_DHCP | |
448 | #define CONFIG_CMD_I2C | |
449 | #define CONFIG_CMD_MII | |
450 | #define CONFIG_CMD_DATE | |
451 | #define CONFIG_CMD_PCI | |
96b8a054 | 452 | |
6d0f6bcf | 453 | #if defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_NAND_U_BOOT) |
bdab39d3 | 454 | #undef CONFIG_CMD_SAVEENV |
8ea5499a | 455 | #undef CONFIG_CMD_LOADS |
96b8a054 SW |
456 | #endif |
457 | ||
8ea5499a | 458 | #define CONFIG_CMDLINE_EDITING 1 |
a059e90e | 459 | #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ |
96b8a054 SW |
460 | |
461 | /* | |
462 | * Miscellaneous configurable options | |
463 | */ | |
6d0f6bcf JCPV |
464 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
465 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ | |
466 | #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ | |
467 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ | |
96b8a054 | 468 | |
6d0f6bcf JCPV |
469 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
470 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
471 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
472 | #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ | |
96b8a054 SW |
473 | |
474 | /* | |
475 | * For booting Linux, the board info and command line data | |
9f530d59 | 476 | * have to be in the first 256 MB of memory, since this is |
96b8a054 SW |
477 | * the maximum mapped by the Linux kernel during initialization. |
478 | */ | |
9f530d59 | 479 | #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux*/ |
96b8a054 | 480 | |
6d0f6bcf | 481 | #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */ |
96b8a054 | 482 | |
6d0f6bcf | 483 | #ifdef CONFIG_SYS_66MHZ |
96b8a054 SW |
484 | |
485 | /* 66MHz IN, 133MHz CSB, 266 DDR, 266 CORE */ | |
486 | /* 0x62040000 */ | |
6d0f6bcf | 487 | #define CONFIG_SYS_HRCW_LOW (\ |
96b8a054 SW |
488 | 0x20000000 /* reserved, must be set */ |\ |
489 | HRCWL_DDRCM |\ | |
490 | HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ | |
491 | HRCWL_DDR_TO_SCB_CLK_2X1 |\ | |
492 | HRCWL_CSB_TO_CLKIN_2X1 |\ | |
493 | HRCWL_CORE_TO_CSB_2X1) | |
494 | ||
6d0f6bcf | 495 | #define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 2) |
e4c09508 | 496 | |
6d0f6bcf | 497 | #elif defined(CONFIG_SYS_33MHZ) |
96b8a054 SW |
498 | |
499 | /* 33MHz IN, 165MHz CSB, 330 DDR, 330 CORE */ | |
500 | /* 0x65040000 */ | |
6d0f6bcf | 501 | #define CONFIG_SYS_HRCW_LOW (\ |
96b8a054 SW |
502 | 0x20000000 /* reserved, must be set */ |\ |
503 | HRCWL_DDRCM |\ | |
504 | HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ | |
505 | HRCWL_DDR_TO_SCB_CLK_2X1 |\ | |
506 | HRCWL_CSB_TO_CLKIN_5X1 |\ | |
507 | HRCWL_CORE_TO_CSB_2X1) | |
508 | ||
6d0f6bcf | 509 | #define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 5) |
e4c09508 | 510 | |
96b8a054 SW |
511 | #endif |
512 | ||
6d0f6bcf | 513 | #define CONFIG_SYS_HRCW_HIGH_BASE (\ |
96b8a054 SW |
514 | HRCWH_PCI_HOST |\ |
515 | HRCWH_PCI1_ARBITER_ENABLE |\ | |
516 | HRCWH_CORE_ENABLE |\ | |
96b8a054 SW |
517 | HRCWH_BOOTSEQ_DISABLE |\ |
518 | HRCWH_SW_WATCHDOG_DISABLE |\ | |
96b8a054 SW |
519 | HRCWH_TSEC1M_IN_RGMII |\ |
520 | HRCWH_TSEC2M_IN_RGMII |\ | |
e4c09508 SW |
521 | HRCWH_BIG_ENDIAN) |
522 | ||
523 | #ifdef CONFIG_NAND_SPL | |
6d0f6bcf | 524 | #define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\ |
4b070809 WD |
525 | HRCWH_FROM_0XFFF00100 |\ |
526 | HRCWH_ROM_LOC_NAND_SP_8BIT |\ | |
527 | HRCWH_RL_EXT_NAND) | |
e4c09508 | 528 | #else |
6d0f6bcf | 529 | #define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\ |
4b070809 WD |
530 | HRCWH_FROM_0X00000100 |\ |
531 | HRCWH_ROM_LOC_LOCAL_16BIT |\ | |
532 | HRCWH_RL_EXT_LEGACY) | |
e4c09508 | 533 | #endif |
96b8a054 SW |
534 | |
535 | /* System IO Config */ | |
6d0f6bcf | 536 | #define CONFIG_SYS_SICRH (SICRH_TSOBI1 | SICRH_TSOBI2) /* RGMII */ |
f986325d | 537 | #define CONFIG_SYS_SICRL SICRL_USBDR_10 /* Enable Internal USB Phy */ |
96b8a054 | 538 | |
6d0f6bcf JCPV |
539 | #define CONFIG_SYS_HID0_INIT 0x000000000 |
540 | #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ | |
1a2e203b KP |
541 | HID0_ENABLE_INSTRUCTION_CACHE | \ |
542 | HID0_ENABLE_DYNAMIC_POWER_MANAGMENT) | |
96b8a054 | 543 | |
6d0f6bcf | 544 | #define CONFIG_SYS_HID2 HID2_HBE |
96b8a054 | 545 | |
31d82672 BB |
546 | #define CONFIG_HIGH_BATS 1 /* High BATs supported */ |
547 | ||
96b8a054 | 548 | /* DDR @ 0x00000000 */ |
6d0f6bcf JCPV |
549 | #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10) |
550 | #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) | |
96b8a054 SW |
551 | |
552 | /* PCI @ 0x80000000 */ | |
6d0f6bcf JCPV |
553 | #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_10) |
554 | #define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) | |
555 | #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) | |
556 | #define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP) | |
96b8a054 SW |
557 | |
558 | /* PCI2 not supported on 8313 */ | |
6d0f6bcf JCPV |
559 | #define CONFIG_SYS_IBAT3L (0) |
560 | #define CONFIG_SYS_IBAT3U (0) | |
561 | #define CONFIG_SYS_IBAT4L (0) | |
562 | #define CONFIG_SYS_IBAT4U (0) | |
96b8a054 SW |
563 | |
564 | /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */ | |
6d0f6bcf JCPV |
565 | #define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) |
566 | #define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR | BATU_BL_256M | BATU_VS | BATU_VP) | |
96b8a054 SW |
567 | |
568 | /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */ | |
c1230980 | 569 | #define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_10 | BATL_GUARDEDSTORAGE) |
6d0f6bcf JCPV |
570 | #define CONFIG_SYS_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) |
571 | ||
572 | #define CONFIG_SYS_IBAT7L (0) | |
573 | #define CONFIG_SYS_IBAT7U (0) | |
574 | ||
575 | #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L | |
576 | #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U | |
577 | #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L | |
578 | #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U | |
579 | #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L | |
580 | #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U | |
581 | #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L | |
582 | #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U | |
583 | #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L | |
584 | #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U | |
585 | #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L | |
586 | #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U | |
587 | #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L | |
588 | #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U | |
589 | #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L | |
590 | #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U | |
96b8a054 | 591 | |
96b8a054 SW |
592 | /* |
593 | * Environment Configuration | |
594 | */ | |
595 | #define CONFIG_ENV_OVERWRITE | |
596 | ||
96b8a054 SW |
597 | #define CONFIG_NETDEV eth1 |
598 | ||
599 | #define CONFIG_HOSTNAME mpc8313erdb | |
8b3637c6 | 600 | #define CONFIG_ROOTPATH "/nfs/root/path" |
b3f44c21 | 601 | #define CONFIG_BOOTFILE "uImage" |
96b8a054 SW |
602 | #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ |
603 | #define CONFIG_FDTFILE mpc8313erdb.dtb | |
604 | ||
79f516bc | 605 | #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ |
7fd0bea2 | 606 | #define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */ |
96b8a054 SW |
607 | #define CONFIG_BAUDRATE 115200 |
608 | ||
609 | #define XMK_STR(x) #x | |
610 | #define MK_STR(x) XMK_STR(x) | |
611 | ||
612 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
53677ef1 | 613 | "netdev=" MK_STR(CONFIG_NETDEV) "\0" \ |
96b8a054 | 614 | "ethprime=TSEC1\0" \ |
53677ef1 WD |
615 | "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ |
616 | "tftpflash=tftpboot $loadaddr $uboot; " \ | |
14d0a02a WD |
617 | "protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ |
618 | "erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ | |
619 | "cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; " \ | |
620 | "protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ | |
621 | "cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0" \ | |
79f516bc | 622 | "fdtaddr=780000\0" \ |
96b8a054 SW |
623 | "fdtfile=" MK_STR(CONFIG_FDTFILE) "\0" \ |
624 | "console=ttyS0\0" \ | |
625 | "setbootargs=setenv bootargs " \ | |
626 | "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \ | |
53677ef1 | 627 | "setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \ |
96b8a054 SW |
628 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ |
629 | "root=$rootdev rw console=$console,$baudrate $othbootargs\0" | |
630 | ||
631 | #define CONFIG_NFSBOOTCOMMAND \ | |
632 | "setenv rootdev /dev/nfs;" \ | |
53677ef1 WD |
633 | "run setbootargs;" \ |
634 | "run setipargs;" \ | |
96b8a054 SW |
635 | "tftp $loadaddr $bootfile;" \ |
636 | "tftp $fdtaddr $fdtfile;" \ | |
637 | "bootm $loadaddr - $fdtaddr" | |
638 | ||
639 | #define CONFIG_RAMBOOTCOMMAND \ | |
640 | "setenv rootdev /dev/ram;" \ | |
641 | "run setbootargs;" \ | |
642 | "tftp $ramdiskaddr $ramdiskfile;" \ | |
643 | "tftp $loadaddr $bootfile;" \ | |
644 | "tftp $fdtaddr $fdtfile;" \ | |
645 | "bootm $loadaddr $ramdiskaddr $fdtaddr" | |
646 | ||
647 | #undef MK_STR | |
648 | #undef XMK_STR | |
649 | ||
650 | #endif /* __CONFIG_H */ |