]>
Commit | Line | Data |
---|---|---|
991425fe | 1 | /* |
2ae18241 | 2 | * (C) Copyright 2006-2010 |
991425fe MB |
3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
4 | * | |
3765b3e7 | 5 | * SPDX-License-Identifier: GPL-2.0+ |
991425fe MB |
6 | */ |
7 | ||
8 | /* | |
9 | * mpc8349emds board configuration file | |
10 | * | |
11 | */ | |
12 | ||
13 | #ifndef __CONFIG_H | |
14 | #define __CONFIG_H | |
15 | ||
991425fe MB |
16 | /* |
17 | * High Level Configuration Options | |
18 | */ | |
19 | #define CONFIG_E300 1 /* E300 Family */ | |
2c7920af | 20 | #define CONFIG_MPC834x 1 /* MPC834x family */ |
991425fe | 21 | #define CONFIG_MPC8349 1 /* MPC8349 specific */ |
991425fe | 22 | |
2ae18241 WD |
23 | #define CONFIG_SYS_TEXT_BASE 0xFE000000 |
24 | ||
25 | #define CONFIG_PCI_66M | |
26 | #ifdef CONFIG_PCI_66M | |
991425fe MB |
27 | #define CONFIG_83XX_CLKIN 66000000 /* in Hz */ |
28 | #else | |
29 | #define CONFIG_83XX_CLKIN 33000000 /* in Hz */ | |
30 | #endif | |
31 | ||
447ad576 | 32 | #ifdef CONFIG_PCISLAVE |
447ad576 IS |
33 | #define CONFIG_83XX_PCICLK 66666666 /* in Hz */ |
34 | #endif /* CONFIG_PCISLAVE */ | |
35 | ||
991425fe | 36 | #ifndef CONFIG_SYS_CLK_FREQ |
2ae18241 | 37 | #ifdef CONFIG_PCI_66M |
991425fe | 38 | #define CONFIG_SYS_CLK_FREQ 66000000 |
8fe9bf61 | 39 | #define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_4X1 |
991425fe MB |
40 | #else |
41 | #define CONFIG_SYS_CLK_FREQ 33000000 | |
8fe9bf61 | 42 | #define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_8X1 |
991425fe MB |
43 | #endif |
44 | #endif | |
45 | ||
6d0f6bcf | 46 | #define CONFIG_SYS_IMMR 0xE0000000 |
991425fe | 47 | |
32795eca | 48 | #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ |
6d0f6bcf JCPV |
49 | #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */ |
50 | #define CONFIG_SYS_MEMTEST_END 0x00100000 | |
991425fe MB |
51 | |
52 | /* | |
53 | * DDR Setup | |
54 | */ | |
8d172c0f | 55 | #define CONFIG_DDR_ECC /* support DDR ECC function */ |
d326f4a2 | 56 | #define CONFIG_DDR_ECC_CMD /* use DDR ECC user commands */ |
991425fe MB |
57 | #define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/ |
58 | ||
d4b91066 | 59 | /* |
d26e34c4 YS |
60 | * SYS_FSL_DDR2 is selected in Kconfig to use unified DDR driver |
61 | * unselect it to use old spd_sdram.c | |
d4b91066 | 62 | */ |
d4b91066 YS |
63 | #define CONFIG_SYS_SPD_BUS_NUM 0 |
64 | #define SPD_EEPROM_ADDRESS1 0x52 | |
65 | #define SPD_EEPROM_ADDRESS2 0x51 | |
d4b91066 YS |
66 | #define CONFIG_DIMM_SLOTS_PER_CTLR 2 |
67 | #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) | |
68 | #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER | |
69 | #define CONFIG_MEM_INIT_VALUE 0xDeadBeef | |
d4b91066 | 70 | |
dc9e499c RJ |
71 | /* |
72 | * 32-bit data path mode. | |
cf48eb9a | 73 | * |
dc9e499c RJ |
74 | * Please note that using this mode for devices with the real density of 64-bit |
75 | * effectively reduces the amount of available memory due to the effect of | |
76 | * wrapping around while translating address to row/columns, for example in the | |
77 | * 256MB module the upper 128MB get aliased with contents of the lower | |
78 | * 128MB); normally this define should be used for devices with real 32-bit | |
cf48eb9a | 79 | * data path. |
dc9e499c RJ |
80 | */ |
81 | #undef CONFIG_DDR_32BIT | |
82 | ||
32795eca JH |
83 | #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/ |
84 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE | |
6d0f6bcf | 85 | #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE |
32795eca JH |
86 | #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \ |
87 | | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) | |
991425fe MB |
88 | #undef CONFIG_DDR_2T_TIMING |
89 | ||
8d172c0f XX |
90 | /* |
91 | * DDRCDR - DDR Control Driver Register | |
92 | */ | |
6d0f6bcf | 93 | #define CONFIG_SYS_DDRCDR_VALUE 0x80080001 |
8d172c0f | 94 | |
991425fe | 95 | #if defined(CONFIG_SPD_EEPROM) |
dc9e499c RJ |
96 | /* |
97 | * Determine DDR configuration from I2C interface. | |
98 | */ | |
99 | #define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */ | |
991425fe | 100 | #else |
dc9e499c RJ |
101 | /* |
102 | * Manually set up DDR parameters | |
103 | */ | |
6d0f6bcf | 104 | #define CONFIG_SYS_DDR_SIZE 256 /* MB */ |
8d172c0f | 105 | #if defined(CONFIG_DDR_II) |
6d0f6bcf | 106 | #define CONFIG_SYS_DDRCDR 0x80080001 |
32795eca | 107 | #define CONFIG_SYS_DDR_CS2_BNDS 0x0000000f |
6d0f6bcf | 108 | #define CONFIG_SYS_DDR_CS2_CONFIG 0x80330102 |
32795eca JH |
109 | #define CONFIG_SYS_DDR_TIMING_0 0x00220802 |
110 | #define CONFIG_SYS_DDR_TIMING_1 0x38357322 | |
111 | #define CONFIG_SYS_DDR_TIMING_2 0x2f9048c8 | |
112 | #define CONFIG_SYS_DDR_TIMING_3 0x00000000 | |
113 | #define CONFIG_SYS_DDR_CLK_CNTL 0x02000000 | |
6d0f6bcf JCPV |
114 | #define CONFIG_SYS_DDR_MODE 0x47d00432 |
115 | #define CONFIG_SYS_DDR_MODE2 0x8000c000 | |
32795eca | 116 | #define CONFIG_SYS_DDR_INTERVAL 0x03cf0080 |
6d0f6bcf JCPV |
117 | #define CONFIG_SYS_DDR_SDRAM_CFG 0x43000000 |
118 | #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 | |
8d172c0f | 119 | #else |
2e651b24 | 120 | #define CONFIG_SYS_DDR_CS2_CONFIG (CSCONFIG_EN \ |
32795eca JH |
121 | | CSCONFIG_ROW_BIT_13 \ |
122 | | CSCONFIG_COL_BIT_10) | |
6d0f6bcf JCPV |
123 | #define CONFIG_SYS_DDR_TIMING_1 0x36332321 |
124 | #define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */ | |
32795eca | 125 | #define CONFIG_SYS_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */ |
6d0f6bcf | 126 | #define CONFIG_SYS_DDR_INTERVAL 0x04060100 /* autocharge,no open page */ |
dc9e499c RJ |
127 | |
128 | #if defined(CONFIG_DDR_32BIT) | |
129 | /* set burst length to 8 for 32-bit data path */ | |
32795eca JH |
130 | /* DLL,normal,seq,4/2.5, 8 burst len */ |
131 | #define CONFIG_SYS_DDR_MODE 0x00000023 | |
dc9e499c RJ |
132 | #else |
133 | /* the default burst length is 4 - for 64-bit data path */ | |
32795eca JH |
134 | /* DLL,normal,seq,4/2.5, 4 burst len */ |
135 | #define CONFIG_SYS_DDR_MODE 0x00000022 | |
dc9e499c | 136 | #endif |
991425fe | 137 | #endif |
8d172c0f | 138 | #endif |
991425fe MB |
139 | |
140 | /* | |
141 | * SDRAM on the Local Bus | |
142 | */ | |
6d0f6bcf JCPV |
143 | #define CONFIG_SYS_LBC_SDRAM_BASE 0xF0000000 /* Localbus SDRAM */ |
144 | #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ | |
991425fe MB |
145 | |
146 | /* | |
147 | * FLASH on the Local Bus | |
148 | */ | |
32795eca JH |
149 | #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ |
150 | #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ | |
6d0f6bcf | 151 | #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */ |
32795eca JH |
152 | #define CONFIG_SYS_FLASH_SIZE 32 /* max flash size in MB */ |
153 | #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */ | |
6d0f6bcf | 154 | /* #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE */ |
991425fe | 155 | |
7d6a0982 JH |
156 | #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \ |
157 | | BR_PS_16 /* 16 bit port */ \ | |
158 | | BR_MS_GPCM /* MSEL = GPCM */ \ | |
159 | | BR_V) /* valid */ | |
160 | #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ | |
32795eca JH |
161 | | OR_UPM_XAM \ |
162 | | OR_GPCM_CSNT \ | |
163 | | OR_GPCM_ACS_DIV2 \ | |
164 | | OR_GPCM_XACS \ | |
165 | | OR_GPCM_SCY_15 \ | |
7d6a0982 JH |
166 | | OR_GPCM_TRLX_SET \ |
167 | | OR_GPCM_EHTR_SET \ | |
32795eca | 168 | | OR_GPCM_EAD) |
7d6a0982 | 169 | |
32795eca JH |
170 | /* window base at flash base */ |
171 | #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE | |
7d6a0982 | 172 | #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_32MB) |
991425fe | 173 | |
32795eca JH |
174 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ |
175 | #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */ | |
991425fe | 176 | |
6d0f6bcf JCPV |
177 | #undef CONFIG_SYS_FLASH_CHECKSUM |
178 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ | |
179 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ | |
991425fe | 180 | |
14d0a02a | 181 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ |
991425fe | 182 | |
6d0f6bcf JCPV |
183 | #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) |
184 | #define CONFIG_SYS_RAMBOOT | |
991425fe | 185 | #else |
6d0f6bcf | 186 | #undef CONFIG_SYS_RAMBOOT |
991425fe MB |
187 | #endif |
188 | ||
189 | /* | |
190 | * BCSR register on local bus 32KB, 8-bit wide for MDS config reg | |
191 | */ | |
32795eca JH |
192 | #define CONFIG_SYS_BCSR 0xE2400000 |
193 | /* Access window base at BCSR base */ | |
194 | #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_BCSR | |
7d6a0982 JH |
195 | #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) |
196 | #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_BCSR \ | |
197 | | BR_PS_8 \ | |
198 | | BR_MS_GPCM \ | |
199 | | BR_V) | |
200 | /* 0x00000801 */ | |
201 | #define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB \ | |
202 | | OR_GPCM_XAM \ | |
203 | | OR_GPCM_CSNT \ | |
204 | | OR_GPCM_SCY_15 \ | |
205 | | OR_GPCM_TRLX_CLEAR \ | |
206 | | OR_GPCM_EHTR_CLEAR) | |
207 | /* 0xFFFFE8F0 */ | |
991425fe | 208 | |
6d0f6bcf | 209 | #define CONFIG_SYS_INIT_RAM_LOCK 1 |
32795eca JH |
210 | #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM addr */ |
211 | #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/ | |
991425fe | 212 | |
32795eca JH |
213 | #define CONFIG_SYS_GBL_DATA_OFFSET \ |
214 | (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) | |
6d0f6bcf | 215 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
991425fe | 216 | |
16c8c170 | 217 | #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ |
c8a90646 | 218 | #define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */ |
991425fe MB |
219 | |
220 | /* | |
221 | * Local Bus LCRR and LBCR regs | |
222 | * LCRR: DLL bypass, Clock divider is 4 | |
223 | * External Local Bus rate is | |
224 | * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV | |
225 | */ | |
32795eca JH |
226 | #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP |
227 | #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4 | |
6d0f6bcf | 228 | #define CONFIG_SYS_LBC_LBCR 0x00000000 |
991425fe | 229 | |
8d172c0f XX |
230 | /* |
231 | * The MPC834xEA MDS for 834xE rev3.1 may not be assembled SDRAM memory. | |
6d0f6bcf | 232 | * if board has SRDAM on local bus, you can define CONFIG_SYS_LB_SDRAM |
8d172c0f | 233 | */ |
6d0f6bcf | 234 | #undef CONFIG_SYS_LB_SDRAM |
991425fe | 235 | |
6d0f6bcf | 236 | #ifdef CONFIG_SYS_LB_SDRAM |
991425fe MB |
237 | /* Local bus BR2, OR2 definition for SDRAM if soldered on the MDS board */ |
238 | /* | |
239 | * Base Register 2 and Option Register 2 configure SDRAM. | |
6d0f6bcf | 240 | * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000. |
991425fe MB |
241 | * |
242 | * For BR2, need: | |
243 | * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 | |
244 | * port-size = 32-bits = BR2[19:20] = 11 | |
245 | * no parity checking = BR2[21:22] = 00 | |
246 | * SDRAM for MSEL = BR2[24:26] = 011 | |
247 | * Valid = BR[31] = 1 | |
248 | * | |
249 | * 0 4 8 12 16 20 24 28 | |
250 | * 1111 0000 0000 0000 0001 1000 0110 0001 = F0001861 | |
991425fe MB |
251 | */ |
252 | ||
7d6a0982 JH |
253 | #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_LBC_SDRAM_BASE \ |
254 | | BR_PS_32 /* 32-bit port */ \ | |
255 | | BR_MS_SDRAM /* MSEL = SDRAM */ \ | |
256 | | BR_V) /* Valid */ | |
257 | /* 0xF0001861 */ | |
258 | #define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_LBC_SDRAM_BASE | |
259 | #define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_64MB) | |
991425fe MB |
260 | |
261 | /* | |
6d0f6bcf | 262 | * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64. |
991425fe MB |
263 | * |
264 | * For OR2, need: | |
265 | * 64MB mask for AM, OR2[0:7] = 1111 1100 | |
266 | * XAM, OR2[17:18] = 11 | |
267 | * 9 columns OR2[19-21] = 010 | |
268 | * 13 rows OR2[23-25] = 100 | |
269 | * EAD set for extra time OR[31] = 1 | |
270 | * | |
271 | * 0 4 8 12 16 20 24 28 | |
272 | * 1111 1100 0000 0000 0110 1001 0000 0001 = FC006901 | |
273 | */ | |
274 | ||
7d6a0982 JH |
275 | #define CONFIG_SYS_OR2_PRELIM (OR_AM_64MB \ |
276 | | OR_SDRAM_XAM \ | |
277 | | ((9 - OR_SDRAM_MIN_COLS) << OR_SDRAM_COLS_SHIFT) \ | |
278 | | ((13 - OR_SDRAM_MIN_ROWS) << OR_SDRAM_ROWS_SHIFT) \ | |
279 | | OR_SDRAM_EAD) | |
280 | /* 0xFC006901 */ | |
991425fe | 281 | |
32795eca JH |
282 | /* LB sdram refresh timer, about 6us */ |
283 | #define CONFIG_SYS_LBC_LSRT 0x32000000 | |
284 | /* LB refresh timer prescal, 266MHz/32 */ | |
285 | #define CONFIG_SYS_LBC_MRTPR 0x20000000 | |
991425fe | 286 | |
32795eca | 287 | #define CONFIG_SYS_LBC_LSDMR_COMMON (LSDMR_RFEN \ |
540dcf1c KG |
288 | | LSDMR_BSMA1516 \ |
289 | | LSDMR_RFCR8 \ | |
290 | | LSDMR_PRETOACT6 \ | |
291 | | LSDMR_ACTTORW3 \ | |
292 | | LSDMR_BL8 \ | |
293 | | LSDMR_WRC3 \ | |
32795eca | 294 | | LSDMR_CL3) |
991425fe MB |
295 | |
296 | /* | |
297 | * SDRAM Controller configuration sequence. | |
298 | */ | |
540dcf1c KG |
299 | #define CONFIG_SYS_LBC_LSDMR_1 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL) |
300 | #define CONFIG_SYS_LBC_LSDMR_2 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH) | |
301 | #define CONFIG_SYS_LBC_LSDMR_3 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH) | |
302 | #define CONFIG_SYS_LBC_LSDMR_4 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW) | |
303 | #define CONFIG_SYS_LBC_LSDMR_5 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL) | |
991425fe MB |
304 | #endif |
305 | ||
306 | /* | |
307 | * Serial Port | |
308 | */ | |
309 | #define CONFIG_CONS_INDEX 1 | |
6d0f6bcf JCPV |
310 | #define CONFIG_SYS_NS16550_SERIAL |
311 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
312 | #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) | |
991425fe | 313 | |
6d0f6bcf | 314 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
32795eca | 315 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} |
991425fe | 316 | |
6d0f6bcf JCPV |
317 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) |
318 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) | |
991425fe | 319 | |
22d71a71 | 320 | #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ |
a059e90e | 321 | #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ |
991425fe MB |
322 | |
323 | /* I2C */ | |
00f792e0 HS |
324 | #define CONFIG_SYS_I2C |
325 | #define CONFIG_SYS_I2C_FSL | |
326 | #define CONFIG_SYS_FSL_I2C_SPEED 400000 | |
327 | #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
328 | #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 | |
329 | #define CONFIG_SYS_FSL_I2C2_SPEED 400000 | |
330 | #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F | |
331 | #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 | |
332 | #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } | |
991425fe | 333 | |
80ddd226 | 334 | /* SPI */ |
8931ab17 | 335 | #define CONFIG_MPC8XXX_SPI |
80ddd226 | 336 | #undef CONFIG_SOFT_SPI /* SPI bit-banged */ |
80ddd226 BW |
337 | |
338 | /* GPIOs. Used as SPI chip selects */ | |
6d0f6bcf JCPV |
339 | #define CONFIG_SYS_GPIO1_PRELIM |
340 | #define CONFIG_SYS_GPIO1_DIR 0xC0000000 /* SPI CS on 0, LED on 1 */ | |
341 | #define CONFIG_SYS_GPIO1_DAT 0xC0000000 /* Both are active LOW */ | |
80ddd226 | 342 | |
991425fe | 343 | /* TSEC */ |
6d0f6bcf | 344 | #define CONFIG_SYS_TSEC1_OFFSET 0x24000 |
32795eca | 345 | #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET) |
6d0f6bcf | 346 | #define CONFIG_SYS_TSEC2_OFFSET 0x25000 |
32795eca | 347 | #define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET) |
991425fe | 348 | |
8fe9bf61 | 349 | /* USB */ |
6d0f6bcf | 350 | #define CONFIG_SYS_USE_MPC834XSYS_USB_PHY 1 /* Use SYS board PHY */ |
991425fe MB |
351 | |
352 | /* | |
353 | * General PCI | |
354 | * Addresses are mapped 1-1. | |
355 | */ | |
6d0f6bcf JCPV |
356 | #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 |
357 | #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE | |
358 | #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ | |
359 | #define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000 | |
360 | #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE | |
361 | #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ | |
32795eca JH |
362 | #define CONFIG_SYS_PCI1_IO_BASE 0x00000000 |
363 | #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000 | |
364 | #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ | |
6d0f6bcf JCPV |
365 | |
366 | #define CONFIG_SYS_PCI2_MEM_BASE 0xA0000000 | |
367 | #define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE | |
368 | #define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */ | |
369 | #define CONFIG_SYS_PCI2_MMIO_BASE 0xB0000000 | |
370 | #define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE | |
371 | #define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000 /* 256M */ | |
32795eca JH |
372 | #define CONFIG_SYS_PCI2_IO_BASE 0x00000000 |
373 | #define CONFIG_SYS_PCI2_IO_PHYS 0xE2100000 | |
374 | #define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */ | |
991425fe MB |
375 | |
376 | #if defined(CONFIG_PCI) | |
377 | ||
8fe9bf61 | 378 | #define PCI_ONE_PCI1 |
991425fe MB |
379 | #if defined(PCI_64BIT) |
380 | #undef PCI_ALL_PCI1 | |
381 | #undef PCI_TWO_PCI1 | |
382 | #undef PCI_ONE_PCI1 | |
383 | #endif | |
384 | ||
162338e1 | 385 | #define CONFIG_83XX_PCI_STREAMING |
991425fe MB |
386 | |
387 | #undef CONFIG_EEPRO100 | |
388 | #undef CONFIG_TULIP | |
389 | ||
390 | #if !defined(CONFIG_PCI_PNP) | |
391 | #define PCI_ENET0_IOADDR 0xFIXME | |
392 | #define PCI_ENET0_MEMADDR 0xFIXME | |
53677ef1 | 393 | #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ |
991425fe MB |
394 | #endif |
395 | ||
396 | #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ | |
6d0f6bcf | 397 | #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ |
991425fe MB |
398 | |
399 | #endif /* CONFIG_PCI */ | |
400 | ||
401 | /* | |
402 | * TSEC configuration | |
403 | */ | |
32795eca | 404 | #define CONFIG_TSEC_ENET /* TSEC ethernet support */ |
991425fe MB |
405 | |
406 | #if defined(CONFIG_TSEC_ENET) | |
991425fe MB |
407 | |
408 | #define CONFIG_GMII 1 /* MII PHY management */ | |
32795eca | 409 | #define CONFIG_TSEC1 1 |
255a3577 | 410 | #define CONFIG_TSEC1_NAME "TSEC0" |
32795eca | 411 | #define CONFIG_TSEC2 1 |
255a3577 | 412 | #define CONFIG_TSEC2_NAME "TSEC1" |
991425fe MB |
413 | #define TSEC1_PHY_ADDR 0 |
414 | #define TSEC2_PHY_ADDR 1 | |
415 | #define TSEC1_PHYIDX 0 | |
416 | #define TSEC2_PHYIDX 0 | |
3a79013e AF |
417 | #define TSEC1_FLAGS TSEC_GIGABIT |
418 | #define TSEC2_FLAGS TSEC_GIGABIT | |
991425fe MB |
419 | |
420 | /* Options are: TSEC[0-1] */ | |
421 | #define CONFIG_ETHPRIME "TSEC0" | |
422 | ||
423 | #endif /* CONFIG_TSEC_ENET */ | |
424 | ||
425 | /* | |
426 | * Configure on-board RTC | |
427 | */ | |
32795eca JH |
428 | #define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */ |
429 | #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */ | |
991425fe MB |
430 | |
431 | /* | |
432 | * Environment | |
433 | */ | |
6d0f6bcf | 434 | #ifndef CONFIG_SYS_RAMBOOT |
32795eca JH |
435 | #define CONFIG_ENV_ADDR \ |
436 | (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) | |
0e8d1586 JCPV |
437 | #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ |
438 | #define CONFIG_ENV_SIZE 0x2000 | |
991425fe MB |
439 | |
440 | /* Address and size of Redundant Environment Sector */ | |
0e8d1586 JCPV |
441 | #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) |
442 | #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) | |
991425fe MB |
443 | |
444 | #else | |
6d0f6bcf | 445 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) |
0e8d1586 | 446 | #define CONFIG_ENV_SIZE 0x2000 |
991425fe MB |
447 | #endif |
448 | ||
449 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
6d0f6bcf | 450 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
991425fe | 451 | |
659e2f67 JL |
452 | /* |
453 | * BOOTP options | |
454 | */ | |
455 | #define CONFIG_BOOTP_BOOTFILESIZE | |
456 | #define CONFIG_BOOTP_BOOTPATH | |
457 | #define CONFIG_BOOTP_GATEWAY | |
458 | #define CONFIG_BOOTP_HOSTNAME | |
459 | ||
8ea5499a JL |
460 | /* |
461 | * Command line configuration. | |
462 | */ | |
8ea5499a | 463 | |
991425fe MB |
464 | #undef CONFIG_WATCHDOG /* watchdog disabled */ |
465 | ||
466 | /* | |
467 | * Miscellaneous configurable options | |
468 | */ | |
6d0f6bcf JCPV |
469 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
470 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ | |
991425fe | 471 | |
991425fe MB |
472 | /* |
473 | * For booting Linux, the board info and command line data | |
9f530d59 | 474 | * have to be in the first 256 MB of memory, since this is |
991425fe MB |
475 | * the maximum mapped by the Linux kernel during initialization. |
476 | */ | |
32795eca JH |
477 | /* Initial Memory map for Linux*/ |
478 | #define CONFIG_SYS_BOOTMAPSZ (256 << 20) | |
63865278 | 479 | #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ |
991425fe | 480 | |
6d0f6bcf | 481 | #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */ |
991425fe MB |
482 | |
483 | #if 1 /*528/264*/ | |
6d0f6bcf | 484 | #define CONFIG_SYS_HRCW_LOW (\ |
991425fe MB |
485 | HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ |
486 | HRCWL_DDR_TO_SCB_CLK_1X1 |\ | |
8fe9bf61 | 487 | HRCWL_CSB_TO_CLKIN |\ |
991425fe MB |
488 | HRCWL_VCO_1X2 |\ |
489 | HRCWL_CORE_TO_CSB_2X1) | |
490 | #elif 0 /*396/132*/ | |
6d0f6bcf | 491 | #define CONFIG_SYS_HRCW_LOW (\ |
991425fe MB |
492 | HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ |
493 | HRCWL_DDR_TO_SCB_CLK_1X1 |\ | |
8fe9bf61 | 494 | HRCWL_CSB_TO_CLKIN |\ |
991425fe MB |
495 | HRCWL_VCO_1X4 |\ |
496 | HRCWL_CORE_TO_CSB_3X1) | |
497 | #elif 0 /*264/132*/ | |
6d0f6bcf | 498 | #define CONFIG_SYS_HRCW_LOW (\ |
991425fe MB |
499 | HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ |
500 | HRCWL_DDR_TO_SCB_CLK_1X1 |\ | |
8fe9bf61 | 501 | HRCWL_CSB_TO_CLKIN |\ |
991425fe MB |
502 | HRCWL_VCO_1X4 |\ |
503 | HRCWL_CORE_TO_CSB_2X1) | |
504 | #elif 0 /*132/132*/ | |
6d0f6bcf | 505 | #define CONFIG_SYS_HRCW_LOW (\ |
991425fe MB |
506 | HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ |
507 | HRCWL_DDR_TO_SCB_CLK_1X1 |\ | |
8fe9bf61 | 508 | HRCWL_CSB_TO_CLKIN |\ |
991425fe MB |
509 | HRCWL_VCO_1X4 |\ |
510 | HRCWL_CORE_TO_CSB_1X1) | |
511 | #elif 0 /*264/264 */ | |
6d0f6bcf | 512 | #define CONFIG_SYS_HRCW_LOW (\ |
991425fe MB |
513 | HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ |
514 | HRCWL_DDR_TO_SCB_CLK_1X1 |\ | |
8fe9bf61 | 515 | HRCWL_CSB_TO_CLKIN |\ |
991425fe MB |
516 | HRCWL_VCO_1X4 |\ |
517 | HRCWL_CORE_TO_CSB_1X1) | |
518 | #endif | |
519 | ||
447ad576 | 520 | #ifdef CONFIG_PCISLAVE |
6d0f6bcf | 521 | #define CONFIG_SYS_HRCW_HIGH (\ |
447ad576 IS |
522 | HRCWH_PCI_AGENT |\ |
523 | HRCWH_64_BIT_PCI |\ | |
524 | HRCWH_PCI1_ARBITER_DISABLE |\ | |
525 | HRCWH_PCI2_ARBITER_DISABLE |\ | |
526 | HRCWH_CORE_ENABLE |\ | |
527 | HRCWH_FROM_0X00000100 |\ | |
528 | HRCWH_BOOTSEQ_DISABLE |\ | |
529 | HRCWH_SW_WATCHDOG_DISABLE |\ | |
530 | HRCWH_ROM_LOC_LOCAL_16BIT |\ | |
531 | HRCWH_TSEC1M_IN_GMII |\ | |
32795eca | 532 | HRCWH_TSEC2M_IN_GMII) |
447ad576 | 533 | #else |
991425fe | 534 | #if defined(PCI_64BIT) |
6d0f6bcf | 535 | #define CONFIG_SYS_HRCW_HIGH (\ |
991425fe MB |
536 | HRCWH_PCI_HOST |\ |
537 | HRCWH_64_BIT_PCI |\ | |
538 | HRCWH_PCI1_ARBITER_ENABLE |\ | |
539 | HRCWH_PCI2_ARBITER_DISABLE |\ | |
540 | HRCWH_CORE_ENABLE |\ | |
541 | HRCWH_FROM_0X00000100 |\ | |
542 | HRCWH_BOOTSEQ_DISABLE |\ | |
543 | HRCWH_SW_WATCHDOG_DISABLE |\ | |
544 | HRCWH_ROM_LOC_LOCAL_16BIT |\ | |
545 | HRCWH_TSEC1M_IN_GMII |\ | |
32795eca | 546 | HRCWH_TSEC2M_IN_GMII) |
991425fe | 547 | #else |
6d0f6bcf | 548 | #define CONFIG_SYS_HRCW_HIGH (\ |
991425fe MB |
549 | HRCWH_PCI_HOST |\ |
550 | HRCWH_32_BIT_PCI |\ | |
551 | HRCWH_PCI1_ARBITER_ENABLE |\ | |
552 | HRCWH_PCI2_ARBITER_ENABLE |\ | |
553 | HRCWH_CORE_ENABLE |\ | |
554 | HRCWH_FROM_0X00000100 |\ | |
555 | HRCWH_BOOTSEQ_DISABLE |\ | |
556 | HRCWH_SW_WATCHDOG_DISABLE |\ | |
557 | HRCWH_ROM_LOC_LOCAL_16BIT |\ | |
558 | HRCWH_TSEC1M_IN_GMII |\ | |
32795eca | 559 | HRCWH_TSEC2M_IN_GMII) |
447ad576 IS |
560 | #endif /* PCI_64BIT */ |
561 | #endif /* CONFIG_PCISLAVE */ | |
991425fe | 562 | |
a5fe514e LN |
563 | /* |
564 | * System performance | |
565 | */ | |
6d0f6bcf | 566 | #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */ |
32795eca | 567 | #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */ |
6d0f6bcf JCPV |
568 | #define CONFIG_SYS_SPCR_TSEC1EP 3 /* TSEC1 emergency priority (0-3) */ |
569 | #define CONFIG_SYS_SPCR_TSEC2EP 3 /* TSEC2 emergency priority (0-3) */ | |
570 | #define CONFIG_SYS_SCCR_TSEC1CM 1 /* TSEC1 clock mode (0-3) */ | |
571 | #define CONFIG_SYS_SCCR_TSEC2CM 1 /* TSEC2 & I2C0 clock mode (0-3) */ | |
a5fe514e | 572 | |
991425fe | 573 | /* System IO Config */ |
3c9b1ee1 | 574 | #define CONFIG_SYS_SICRH 0 |
6d0f6bcf | 575 | #define CONFIG_SYS_SICRL SICRL_LDP_A |
991425fe | 576 | |
6d0f6bcf | 577 | #define CONFIG_SYS_HID0_INIT 0x000000000 |
32795eca JH |
578 | #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK \ |
579 | | HID0_ENABLE_INSTRUCTION_CACHE) | |
991425fe | 580 | |
32795eca | 581 | /* #define CONFIG_SYS_HID0_FINAL (\ |
991425fe MB |
582 | HID0_ENABLE_INSTRUCTION_CACHE |\ |
583 | HID0_ENABLE_M_BIT |\ | |
32795eca | 584 | HID0_ENABLE_ADDRESS_BROADCAST) */ |
991425fe | 585 | |
6d0f6bcf | 586 | #define CONFIG_SYS_HID2 HID2_HBE |
31d82672 | 587 | #define CONFIG_HIGH_BATS 1 /* High BATs supported */ |
991425fe MB |
588 | |
589 | /* DDR @ 0x00000000 */ | |
32795eca | 590 | #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \ |
72cd4087 | 591 | | BATL_PP_RW \ |
32795eca JH |
592 | | BATL_MEMCOHERENCE) |
593 | #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \ | |
594 | | BATU_BL_256M \ | |
595 | | BATU_VS \ | |
596 | | BATU_VP) | |
991425fe MB |
597 | |
598 | /* PCI @ 0x80000000 */ | |
599 | #ifdef CONFIG_PCI | |
842033e6 | 600 | #define CONFIG_PCI_INDIRECT_BRIDGE |
32795eca | 601 | #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE \ |
72cd4087 | 602 | | BATL_PP_RW \ |
32795eca JH |
603 | | BATL_MEMCOHERENCE) |
604 | #define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE \ | |
605 | | BATU_BL_256M \ | |
606 | | BATU_VS \ | |
607 | | BATU_VP) | |
608 | #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \ | |
72cd4087 | 609 | | BATL_PP_RW \ |
32795eca JH |
610 | | BATL_CACHEINHIBIT \ |
611 | | BATL_GUARDEDSTORAGE) | |
612 | #define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE \ | |
613 | | BATU_BL_256M \ | |
614 | | BATU_VS \ | |
615 | | BATU_VP) | |
991425fe | 616 | #else |
6d0f6bcf JCPV |
617 | #define CONFIG_SYS_IBAT1L (0) |
618 | #define CONFIG_SYS_IBAT1U (0) | |
619 | #define CONFIG_SYS_IBAT2L (0) | |
620 | #define CONFIG_SYS_IBAT2U (0) | |
991425fe MB |
621 | #endif |
622 | ||
8fe9bf61 | 623 | #ifdef CONFIG_MPC83XX_PCI2 |
32795eca | 624 | #define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI2_MEM_BASE \ |
72cd4087 | 625 | | BATL_PP_RW \ |
32795eca JH |
626 | | BATL_MEMCOHERENCE) |
627 | #define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI2_MEM_BASE \ | |
628 | | BATU_BL_256M \ | |
629 | | BATU_VS \ | |
630 | | BATU_VP) | |
631 | #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI2_MMIO_BASE \ | |
72cd4087 | 632 | | BATL_PP_RW \ |
32795eca JH |
633 | | BATL_CACHEINHIBIT \ |
634 | | BATL_GUARDEDSTORAGE) | |
635 | #define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI2_MMIO_BASE \ | |
636 | | BATU_BL_256M \ | |
637 | | BATU_VS \ | |
638 | | BATU_VP) | |
8fe9bf61 | 639 | #else |
6d0f6bcf JCPV |
640 | #define CONFIG_SYS_IBAT3L (0) |
641 | #define CONFIG_SYS_IBAT3U (0) | |
642 | #define CONFIG_SYS_IBAT4L (0) | |
643 | #define CONFIG_SYS_IBAT4U (0) | |
8fe9bf61 | 644 | #endif |
991425fe | 645 | |
8fe9bf61 | 646 | /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */ |
32795eca | 647 | #define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \ |
72cd4087 | 648 | | BATL_PP_RW \ |
32795eca JH |
649 | | BATL_CACHEINHIBIT \ |
650 | | BATL_GUARDEDSTORAGE) | |
651 | #define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \ | |
652 | | BATU_BL_256M \ | |
653 | | BATU_VS \ | |
654 | | BATU_VP) | |
991425fe | 655 | |
8fe9bf61 | 656 | /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */ |
32795eca | 657 | #define CONFIG_SYS_IBAT6L (0xF0000000 \ |
72cd4087 JH |
658 | | BATL_PP_RW \ |
659 | | BATL_MEMCOHERENCE \ | |
660 | | BATL_GUARDEDSTORAGE) | |
32795eca JH |
661 | #define CONFIG_SYS_IBAT6U (0xF0000000 \ |
662 | | BATU_BL_256M \ | |
663 | | BATU_VS \ | |
664 | | BATU_VP) | |
6d0f6bcf JCPV |
665 | |
666 | #define CONFIG_SYS_IBAT7L (0) | |
667 | #define CONFIG_SYS_IBAT7U (0) | |
668 | ||
669 | #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L | |
670 | #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U | |
671 | #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L | |
672 | #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U | |
673 | #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L | |
674 | #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U | |
675 | #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L | |
676 | #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U | |
677 | #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L | |
678 | #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U | |
679 | #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L | |
680 | #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U | |
681 | #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L | |
682 | #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U | |
683 | #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L | |
684 | #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U | |
991425fe | 685 | |
8ea5499a | 686 | #if defined(CONFIG_CMD_KGDB) |
991425fe | 687 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ |
991425fe MB |
688 | #endif |
689 | ||
690 | /* | |
691 | * Environment Configuration | |
692 | */ | |
693 | #define CONFIG_ENV_OVERWRITE | |
694 | ||
695 | #if defined(CONFIG_TSEC_ENET) | |
991425fe | 696 | #define CONFIG_HAS_ETH1 |
10327dc5 | 697 | #define CONFIG_HAS_ETH0 |
991425fe MB |
698 | #endif |
699 | ||
991425fe | 700 | #define CONFIG_HOSTNAME mpc8349emds |
8b3637c6 | 701 | #define CONFIG_ROOTPATH "/nfsroot/rootfs" |
b3f44c21 | 702 | #define CONFIG_BOOTFILE "uImage" |
991425fe | 703 | |
32795eca | 704 | #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ |
991425fe | 705 | |
991425fe | 706 | #define CONFIG_PREBOOT "echo;" \ |
32bf3d14 | 707 | "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ |
991425fe MB |
708 | "echo" |
709 | ||
710 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
711 | "netdev=eth0\0" \ | |
712 | "hostname=mpc8349emds\0" \ | |
713 | "nfsargs=setenv bootargs root=/dev/nfs rw " \ | |
714 | "nfsroot=${serverip}:${rootpath}\0" \ | |
715 | "ramargs=setenv bootargs root=/dev/ram rw\0" \ | |
716 | "addip=setenv bootargs ${bootargs} " \ | |
717 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ | |
718 | ":${hostname}:${netdev}:off panic=1\0" \ | |
719 | "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ | |
720 | "flash_nfs=run nfsargs addip addtty;" \ | |
721 | "bootm ${kernel_addr}\0" \ | |
722 | "flash_self=run ramargs addip addtty;" \ | |
723 | "bootm ${kernel_addr} ${ramdisk_addr}\0" \ | |
724 | "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ | |
725 | "bootm\0" \ | |
991425fe MB |
726 | "load=tftp 100000 /tftpboot/mpc8349emds/u-boot.bin\0" \ |
727 | "update=protect off fe000000 fe03ffff; " \ | |
32795eca | 728 | "era fe000000 fe03ffff; cp.b 100000 fe000000 ${filesize}\0"\ |
d8ab58b2 | 729 | "upd=run load update\0" \ |
79f516bc | 730 | "fdtaddr=780000\0" \ |
cc861f71 | 731 | "fdtfile=mpc834x_mds.dtb\0" \ |
991425fe MB |
732 | "" |
733 | ||
32795eca JH |
734 | #define CONFIG_NFSBOOTCOMMAND \ |
735 | "setenv bootargs root=/dev/nfs rw " \ | |
736 | "nfsroot=$serverip:$rootpath " \ | |
737 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \ | |
738 | "$netdev:off " \ | |
739 | "console=$consoledev,$baudrate $othbootargs;" \ | |
740 | "tftp $loadaddr $bootfile;" \ | |
741 | "tftp $fdtaddr $fdtfile;" \ | |
742 | "bootm $loadaddr - $fdtaddr" | |
bf0b542d KP |
743 | |
744 | #define CONFIG_RAMBOOTCOMMAND \ | |
32795eca JH |
745 | "setenv bootargs root=/dev/ram rw " \ |
746 | "console=$consoledev,$baudrate $othbootargs;" \ | |
747 | "tftp $ramdiskaddr $ramdiskfile;" \ | |
748 | "tftp $loadaddr $bootfile;" \ | |
749 | "tftp $fdtaddr $fdtfile;" \ | |
750 | "bootm $loadaddr $ramdiskaddr $fdtaddr" | |
bf0b542d | 751 | |
991425fe MB |
752 | #define CONFIG_BOOTCOMMAND "run flash_self" |
753 | ||
754 | #endif /* __CONFIG_H */ |