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5e918a98 KP |
1 | /* |
2 | * Copyright (C) 2007 Freescale Semiconductor, Inc. | |
3 | * Kevin Lam <kevin.lam@freescale.com> | |
4 | * Joe D'Abbraccio <joe.d'abbraccio@freescale.com> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License as | |
8 | * published by the Free Software Foundation; either version 2 of | |
9 | * the License, or (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, write to the Free Software | |
18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
19 | * MA 02111-1307 USA | |
20 | */ | |
21 | ||
22 | #ifndef __CONFIG_H | |
23 | #define __CONFIG_H | |
24 | ||
25 | /* | |
26 | * High Level Configuration Options | |
27 | */ | |
28 | #define CONFIG_E300 1 /* E300 family */ | |
2c7920af PT |
29 | #define CONFIG_MPC83xx 1 /* MPC83xx family */ |
30 | #define CONFIG_MPC837x 1 /* MPC837x CPU specific */ | |
5e918a98 KP |
31 | #define CONFIG_MPC837XERDB 1 |
32 | ||
2ae18241 WD |
33 | #define CONFIG_SYS_TEXT_BASE 0xFE000000 |
34 | ||
5e918a98 KP |
35 | #define CONFIG_PCI 1 |
36 | ||
2bd7460e | 37 | #define CONFIG_BOARD_EARLY_INIT_F |
89c7784e | 38 | #define CONFIG_MISC_INIT_R |
c9646ed7 | 39 | #define CONFIG_HWCONFIG |
89c7784e TT |
40 | |
41 | /* | |
42 | * On-board devices | |
43 | */ | |
44 | #define CONFIG_TSEC_ENET /* TSEC Ethernet support */ | |
45 | #define CONFIG_VSC7385_ENET | |
46 | ||
5e918a98 KP |
47 | /* |
48 | * System Clock Setup | |
49 | */ | |
50 | #ifdef CONFIG_PCISLAVE | |
51 | #define CONFIG_83XX_PCICLK 66666667 /* in HZ */ | |
52 | #else | |
53 | #define CONFIG_83XX_CLKIN 66666667 /* in Hz */ | |
be9b56df | 54 | #define CONFIG_PCIE |
5e918a98 KP |
55 | #endif |
56 | ||
57 | #ifndef CONFIG_SYS_CLK_FREQ | |
58 | #define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN | |
59 | #endif | |
60 | ||
61 | /* | |
62 | * Hardware Reset Configuration Word | |
63 | */ | |
6d0f6bcf | 64 | #define CONFIG_SYS_HRCW_LOW (\ |
5e918a98 KP |
65 | HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ |
66 | HRCWL_DDR_TO_SCB_CLK_1X1 |\ | |
67 | HRCWL_SVCOD_DIV_2 |\ | |
68 | HRCWL_CSB_TO_CLKIN_5X1 |\ | |
69 | HRCWL_CORE_TO_CSB_2X1) | |
70 | ||
71 | #ifdef CONFIG_PCISLAVE | |
6d0f6bcf | 72 | #define CONFIG_SYS_HRCW_HIGH (\ |
5e918a98 KP |
73 | HRCWH_PCI_AGENT |\ |
74 | HRCWH_PCI1_ARBITER_DISABLE |\ | |
75 | HRCWH_CORE_ENABLE |\ | |
76 | HRCWH_FROM_0XFFF00100 |\ | |
77 | HRCWH_BOOTSEQ_DISABLE |\ | |
78 | HRCWH_SW_WATCHDOG_DISABLE |\ | |
79 | HRCWH_ROM_LOC_LOCAL_16BIT |\ | |
80 | HRCWH_RL_EXT_LEGACY |\ | |
81 | HRCWH_TSEC1M_IN_RGMII |\ | |
82 | HRCWH_TSEC2M_IN_RGMII |\ | |
83 | HRCWH_BIG_ENDIAN |\ | |
84 | HRCWH_LDP_CLEAR) | |
85 | #else | |
6d0f6bcf | 86 | #define CONFIG_SYS_HRCW_HIGH (\ |
5e918a98 KP |
87 | HRCWH_PCI_HOST |\ |
88 | HRCWH_PCI1_ARBITER_ENABLE |\ | |
89 | HRCWH_CORE_ENABLE |\ | |
90 | HRCWH_FROM_0X00000100 |\ | |
91 | HRCWH_BOOTSEQ_DISABLE |\ | |
92 | HRCWH_SW_WATCHDOG_DISABLE |\ | |
93 | HRCWH_ROM_LOC_LOCAL_16BIT |\ | |
94 | HRCWH_RL_EXT_LEGACY |\ | |
95 | HRCWH_TSEC1M_IN_RGMII |\ | |
96 | HRCWH_TSEC2M_IN_RGMII |\ | |
97 | HRCWH_BIG_ENDIAN |\ | |
98 | HRCWH_LDP_CLEAR) | |
99 | #endif | |
100 | ||
6d0f6bcf | 101 | /* System performance - define the value i.e. CONFIG_SYS_XXX |
5e918a98 KP |
102 | */ |
103 | ||
104 | /* Arbiter Configuration Register */ | |
6d0f6bcf | 105 | #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */ |
5afe9722 | 106 | #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */ |
5e918a98 KP |
107 | |
108 | /* System Priority Control Regsiter */ | |
5afe9722 | 109 | #define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC1&2 emergency priority (0-3) */ |
5e918a98 KP |
110 | |
111 | /* System Clock Configuration Register */ | |
6d0f6bcf JCPV |
112 | #define CONFIG_SYS_SCCR_TSEC1CM 1 /* eTSEC1 clock mode (0-3) */ |
113 | #define CONFIG_SYS_SCCR_TSEC2CM 1 /* eTSEC2 clock mode (0-3) */ | |
5afe9722 | 114 | #define CONFIG_SYS_SCCR_SATACM SCCR_SATACM_2 /* SATA1-4 clock mode (0-3) */ |
5e918a98 KP |
115 | |
116 | /* | |
117 | * System IO Config | |
118 | */ | |
6d0f6bcf JCPV |
119 | #define CONFIG_SYS_SICRH 0x08200000 |
120 | #define CONFIG_SYS_SICRL 0x00000000 | |
5e918a98 KP |
121 | |
122 | /* | |
123 | * Output Buffer Impedance | |
124 | */ | |
6d0f6bcf | 125 | #define CONFIG_SYS_OBIR 0x30100000 |
5e918a98 KP |
126 | |
127 | /* | |
128 | * IMMR new address | |
129 | */ | |
6d0f6bcf | 130 | #define CONFIG_SYS_IMMR 0xE0000000 |
5e918a98 | 131 | |
89c7784e TT |
132 | /* |
133 | * Device configurations | |
134 | */ | |
135 | ||
136 | /* Vitesse 7385 */ | |
137 | ||
138 | #ifdef CONFIG_VSC7385_ENET | |
139 | ||
140 | #define CONFIG_TSEC2 | |
141 | ||
142 | /* The flash address and size of the VSC7385 firmware image */ | |
143 | #define CONFIG_VSC7385_IMAGE 0xFE7FE000 | |
144 | #define CONFIG_VSC7385_IMAGE_SIZE 8192 | |
145 | ||
146 | #endif | |
147 | ||
5e918a98 KP |
148 | /* |
149 | * DDR Setup | |
150 | */ | |
6d0f6bcf JCPV |
151 | #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ |
152 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE | |
153 | #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE | |
154 | #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL 0x03000000 | |
155 | #define CONFIG_SYS_83XX_DDR_USES_CS0 | |
5e918a98 | 156 | |
6d0f6bcf | 157 | #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_DHC_EN | DDRCDR_ODT | DDRCDR_Q_DRN) |
5e918a98 KP |
158 | |
159 | #undef CONFIG_DDR_ECC /* support DDR ECC function */ | |
160 | #undef CONFIG_DDR_ECC_CMD /* Use DDR ECC user commands */ | |
161 | ||
162 | #undef CONFIG_NEVER_ASSERT_ODT_TO_CPU /* Never assert ODT to internal IOs */ | |
163 | ||
164 | /* | |
165 | * Manually set up DDR parameters | |
166 | */ | |
6d0f6bcf | 167 | #define CONFIG_SYS_DDR_SIZE 256 /* MB */ |
2fef4020 JH |
168 | #define CONFIG_SYS_DDR_CS0_BNDS 0x0000000f |
169 | #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ | |
170 | | CSCONFIG_ODT_WR_ONLY_CURRENT \ | |
171 | | CSCONFIG_ROW_BIT_13 \ | |
172 | | CSCONFIG_COL_BIT_10) | |
5e918a98 | 173 | |
6d0f6bcf JCPV |
174 | #define CONFIG_SYS_DDR_TIMING_3 0x00000000 |
175 | #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \ | |
5e918a98 KP |
176 | | (0 << TIMING_CFG0_WRT_SHIFT) \ |
177 | | (0 << TIMING_CFG0_RRT_SHIFT) \ | |
178 | | (0 << TIMING_CFG0_WWT_SHIFT) \ | |
179 | | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \ | |
180 | | (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \ | |
181 | | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \ | |
182 | | (2 << TIMING_CFG0_MRS_CYC_SHIFT)) | |
5e918a98 | 183 | /* 0x00260802 */ /* DDR400 */ |
6d0f6bcf | 184 | #define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \ |
5e918a98 KP |
185 | | (9 << TIMING_CFG1_ACTTOPRE_SHIFT) \ |
186 | | (3 << TIMING_CFG1_ACTTORW_SHIFT) \ | |
187 | | (7 << TIMING_CFG1_CASLAT_SHIFT) \ | |
188 | | (13 << TIMING_CFG1_REFREC_SHIFT) \ | |
189 | | (3 << TIMING_CFG1_WRREC_SHIFT) \ | |
190 | | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \ | |
191 | | (2 << TIMING_CFG1_WRTORD_SHIFT)) | |
5e918a98 | 192 | /* 0x3937d322 */ |
2fef4020 JH |
193 | #define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \ |
194 | | (5 << TIMING_CFG2_CPO_SHIFT) \ | |
195 | | (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \ | |
196 | | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \ | |
197 | | (3 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \ | |
198 | | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \ | |
199 | | (8 << TIMING_CFG2_FOUR_ACT_SHIFT)) | |
200 | /* 0x02984cc8 */ | |
5e918a98 | 201 | |
8eceeb7f KP |
202 | #define CONFIG_SYS_DDR_INTERVAL ((1024 << SDRAM_INTERVAL_REFINT_SHIFT) \ |
203 | | (0 << SDRAM_INTERVAL_BSTOPRE_SHIFT)) | |
5e918a98 KP |
204 | /* 0x06090100 */ |
205 | ||
206 | #if defined(CONFIG_DDR_2T_TIMING) | |
5afe9722 | 207 | #define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \ |
2fef4020 JH |
208 | | SDRAM_CFG_SDRAM_TYPE_DDR2 \ |
209 | | SDRAM_CFG_32_BE \ | |
210 | | SDRAM_CFG_2T_EN) | |
211 | /* 0x43088000 */ | |
5e918a98 | 212 | #else |
5afe9722 | 213 | #define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \ |
2fef4020 | 214 | | SDRAM_CFG_SDRAM_TYPE_DDR2) |
5afe9722 | 215 | /* 0x43000000 */ |
5e918a98 | 216 | #endif |
6d0f6bcf | 217 | #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00001000 /* 1 posted refresh */ |
8eceeb7f | 218 | #define CONFIG_SYS_DDR_MODE ((0x0406 << SDRAM_MODE_ESD_SHIFT) \ |
5afe9722 JH |
219 | | (0x0442 << SDRAM_MODE_SD_SHIFT)) |
220 | /* 0x04400442 */ /* DDR400 */ | |
6d0f6bcf | 221 | #define CONFIG_SYS_DDR_MODE2 0x00000000 |
5e918a98 KP |
222 | |
223 | /* | |
224 | * Memory test | |
225 | */ | |
6d0f6bcf JCPV |
226 | #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ |
227 | #define CONFIG_SYS_MEMTEST_START 0x00040000 /* memtest region */ | |
228 | #define CONFIG_SYS_MEMTEST_END 0x0ef70010 | |
5e918a98 KP |
229 | |
230 | /* | |
231 | * The reserved memory | |
232 | */ | |
14d0a02a | 233 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ |
5e918a98 | 234 | |
6d0f6bcf JCPV |
235 | #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) |
236 | #define CONFIG_SYS_RAMBOOT | |
5e918a98 | 237 | #else |
6d0f6bcf | 238 | #undef CONFIG_SYS_RAMBOOT |
5e918a98 KP |
239 | #endif |
240 | ||
5afe9722 JH |
241 | #define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ |
242 | #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ | |
5e918a98 KP |
243 | |
244 | /* | |
245 | * Initial RAM Base Address Setup | |
246 | */ | |
6d0f6bcf JCPV |
247 | #define CONFIG_SYS_INIT_RAM_LOCK 1 |
248 | #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ | |
553f0982 | 249 | #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */ |
5afe9722 JH |
250 | #define CONFIG_SYS_GBL_DATA_OFFSET \ |
251 | (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) | |
5e918a98 KP |
252 | |
253 | /* | |
254 | * Local Bus Configuration & Clock Setup | |
255 | */ | |
c7190f02 KP |
256 | #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP |
257 | #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_8 | |
6d0f6bcf | 258 | #define CONFIG_SYS_LBC_LBCR 0x00000000 |
0914f483 | 259 | #define CONFIG_FSL_ELBC 1 |
5e918a98 KP |
260 | |
261 | /* | |
262 | * FLASH on the Local Bus | |
263 | */ | |
6d0f6bcf | 264 | #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ |
00b1883a | 265 | #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ |
6d0f6bcf JCPV |
266 | #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ |
267 | #define CONFIG_SYS_FLASH_SIZE 8 /* max FLASH size is 32M */ | |
5e918a98 | 268 | |
5afe9722 JH |
269 | #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */ |
270 | #define CONFIG_SYS_FLASH_EMPTY_INFO /* display empty sectors */ | |
271 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* buffer up multiple bytes */ | |
5e918a98 | 272 | |
5afe9722 JH |
273 | /* Window base at flash base */ |
274 | #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE | |
6d0f6bcf | 275 | #define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000016 /* 8 MB window size */ |
5e918a98 | 276 | |
5afe9722 | 277 | #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \ |
7d6a0982 JH |
278 | | BR_PS_16 /* 16 bit port */ \ |
279 | | BR_MS_GPCM /* MSEL = GPCM */ \ | |
280 | | BR_V) /* valid */ | |
281 | #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ | |
5e918a98 KP |
282 | | OR_GPCM_XACS \ |
283 | | OR_GPCM_SCY_9 \ | |
7d6a0982 | 284 | | OR_GPCM_EHTR_SET \ |
5e918a98 | 285 | | OR_GPCM_EAD) |
7d6a0982 | 286 | /* 0xFF800191 */ |
5e918a98 | 287 | |
6d0f6bcf JCPV |
288 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ |
289 | #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */ | |
5e918a98 | 290 | |
6d0f6bcf JCPV |
291 | #undef CONFIG_SYS_FLASH_CHECKSUM |
292 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ | |
293 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ | |
5e918a98 | 294 | |
46a3aeea AV |
295 | /* |
296 | * NAND Flash on the Local Bus | |
297 | */ | |
7d6a0982 | 298 | #define CONFIG_SYS_NAND_BASE 0xE0600000 |
5afe9722 | 299 | #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_NAND_BASE \ |
7d6a0982 JH |
300 | | BR_DECC_CHK_GEN /* Use HW ECC */ \ |
301 | | BR_PS_8 /* 8 bit port */ \ | |
302 | | BR_MS_FCM /* MSEL = FCM */ \ | |
5afe9722 | 303 | | BR_V) /* valid */ |
7d6a0982 | 304 | #define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB \ |
5afe9722 JH |
305 | | OR_FCM_CSCT \ |
306 | | OR_FCM_CST \ | |
307 | | OR_FCM_CHT \ | |
308 | | OR_FCM_SCY_1 \ | |
309 | | OR_FCM_TRLX \ | |
310 | | OR_FCM_EHTR) | |
6d0f6bcf | 311 | #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE |
7d6a0982 | 312 | #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) |
46a3aeea | 313 | |
89c7784e TT |
314 | /* Vitesse 7385 */ |
315 | ||
6d0f6bcf | 316 | #define CONFIG_SYS_VSC7385_BASE 0xF0000000 |
5e918a98 | 317 | |
89c7784e TT |
318 | #ifdef CONFIG_VSC7385_ENET |
319 | ||
7d6a0982 JH |
320 | #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_VSC7385_BASE \ |
321 | | BR_PS_8 \ | |
322 | | BR_MS_GPCM \ | |
323 | | BR_V) | |
324 | /* 0xF0000801 */ | |
325 | #define CONFIG_SYS_OR2_PRELIM (OR_AM_128KB \ | |
326 | | OR_GPCM_CSNT \ | |
327 | | OR_GPCM_XACS \ | |
328 | | OR_GPCM_SCY_15 \ | |
329 | | OR_GPCM_SETA \ | |
330 | | OR_GPCM_TRLX_SET \ | |
331 | | OR_GPCM_EHTR_SET \ | |
332 | | OR_GPCM_EAD) | |
333 | /* 0xfffe09ff */ | |
334 | ||
5afe9722 JH |
335 | /* Access Base */ |
336 | #define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_VSC7385_BASE | |
7d6a0982 | 337 | #define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_128KB) |
5e918a98 | 338 | |
89c7784e TT |
339 | #endif |
340 | ||
5e918a98 KP |
341 | /* |
342 | * Serial Port | |
343 | */ | |
344 | #define CONFIG_CONS_INDEX 1 | |
6d0f6bcf JCPV |
345 | #define CONFIG_SYS_NS16550 |
346 | #define CONFIG_SYS_NS16550_SERIAL | |
347 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
348 | #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) | |
5e918a98 | 349 | |
6d0f6bcf | 350 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
5afe9722 | 351 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} |
5e918a98 | 352 | |
6d0f6bcf JCPV |
353 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) |
354 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) | |
5e918a98 | 355 | |
2bd7460e AV |
356 | /* SERDES */ |
357 | #define CONFIG_FSL_SERDES | |
358 | #define CONFIG_FSL_SERDES1 0xe3000 | |
359 | #define CONFIG_FSL_SERDES2 0xe3100 | |
360 | ||
5e918a98 | 361 | /* Use the HUSH parser */ |
6d0f6bcf | 362 | #define CONFIG_SYS_HUSH_PARSER |
5e918a98 KP |
363 | |
364 | /* Pass open firmware flat tree */ | |
365 | #define CONFIG_OF_LIBFDT 1 | |
366 | #define CONFIG_OF_BOARD_SETUP 1 | |
aabce7fb | 367 | #define CONFIG_OF_STDOUT_VIA_ALIAS 1 |
5e918a98 KP |
368 | |
369 | /* I2C */ | |
00f792e0 HS |
370 | #define CONFIG_SYS_I2C |
371 | #define CONFIG_SYS_I2C_FSL | |
372 | #define CONFIG_SYS_FSL_I2C_SPEED 400000 | |
373 | #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
374 | #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 | |
375 | #define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} } | |
5e918a98 KP |
376 | |
377 | /* | |
378 | * Config on-board RTC | |
379 | */ | |
380 | #define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */ | |
6d0f6bcf | 381 | #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */ |
5e918a98 KP |
382 | |
383 | /* | |
384 | * General PCI | |
385 | * Addresses are mapped 1-1. | |
386 | */ | |
5afe9722 JH |
387 | #define CONFIG_SYS_PCI_MEM_BASE 0x80000000 |
388 | #define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BASE | |
389 | #define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 /* 256M */ | |
6d0f6bcf JCPV |
390 | #define CONFIG_SYS_PCI_MMIO_BASE 0x90000000 |
391 | #define CONFIG_SYS_PCI_MMIO_PHYS CONFIG_SYS_PCI_MMIO_BASE | |
392 | #define CONFIG_SYS_PCI_MMIO_SIZE 0x10000000 /* 256M */ | |
393 | #define CONFIG_SYS_PCI_IO_BASE 0x00000000 | |
394 | #define CONFIG_SYS_PCI_IO_PHYS 0xE0300000 | |
395 | #define CONFIG_SYS_PCI_IO_SIZE 0x100000 /* 1M */ | |
396 | ||
397 | #define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE | |
398 | #define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000 | |
399 | #define CONFIG_SYS_PCI_SLV_MEM_SIZE 0x80000000 | |
5e918a98 | 400 | |
7e915580 AV |
401 | #define CONFIG_SYS_PCIE1_BASE 0xA0000000 |
402 | #define CONFIG_SYS_PCIE1_CFG_BASE 0xA0000000 | |
403 | #define CONFIG_SYS_PCIE1_CFG_SIZE 0x08000000 | |
404 | #define CONFIG_SYS_PCIE1_MEM_BASE 0xA8000000 | |
405 | #define CONFIG_SYS_PCIE1_MEM_PHYS 0xA8000000 | |
406 | #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 | |
407 | #define CONFIG_SYS_PCIE1_IO_BASE 0x00000000 | |
408 | #define CONFIG_SYS_PCIE1_IO_PHYS 0xB8000000 | |
409 | #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 | |
410 | ||
411 | #define CONFIG_SYS_PCIE2_BASE 0xC0000000 | |
412 | #define CONFIG_SYS_PCIE2_CFG_BASE 0xC0000000 | |
413 | #define CONFIG_SYS_PCIE2_CFG_SIZE 0x08000000 | |
414 | #define CONFIG_SYS_PCIE2_MEM_BASE 0xC8000000 | |
415 | #define CONFIG_SYS_PCIE2_MEM_PHYS 0xC8000000 | |
416 | #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 | |
417 | #define CONFIG_SYS_PCIE2_IO_BASE 0x00000000 | |
418 | #define CONFIG_SYS_PCIE2_IO_PHYS 0xD8000000 | |
419 | #define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000 | |
420 | ||
5e918a98 | 421 | #ifdef CONFIG_PCI |
842033e6 | 422 | #define CONFIG_PCI_INDIRECT_BRIDGE |
5e918a98 KP |
423 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ |
424 | ||
5e918a98 | 425 | #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ |
6d0f6bcf | 426 | #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ |
5e918a98 KP |
427 | #endif /* CONFIG_PCI */ |
428 | ||
5e918a98 KP |
429 | /* |
430 | * TSEC | |
431 | */ | |
89c7784e | 432 | #ifdef CONFIG_TSEC_ENET |
5e918a98 | 433 | |
89c7784e TT |
434 | #define CONFIG_GMII /* MII PHY management */ |
435 | ||
436 | #define CONFIG_TSEC1 | |
437 | ||
438 | #ifdef CONFIG_TSEC1 | |
439 | #define CONFIG_HAS_ETH0 | |
5e918a98 | 440 | #define CONFIG_TSEC1_NAME "TSEC0" |
6d0f6bcf | 441 | #define CONFIG_SYS_TSEC1_OFFSET 0x24000 |
5e918a98 | 442 | #define TSEC1_PHY_ADDR 2 |
5e918a98 | 443 | #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) |
5e918a98 | 444 | #define TSEC1_PHYIDX 0 |
89c7784e | 445 | #endif |
5e918a98 | 446 | |
89c7784e TT |
447 | #ifdef CONFIG_TSEC2 |
448 | #define CONFIG_HAS_ETH1 | |
449 | #define CONFIG_TSEC2_NAME "TSEC1" | |
6d0f6bcf | 450 | #define CONFIG_SYS_TSEC2_OFFSET 0x25000 |
89c7784e TT |
451 | #define TSEC2_PHY_ADDR 0x1c |
452 | #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
453 | #define TSEC2_PHYIDX 0 | |
454 | #endif | |
5e918a98 KP |
455 | |
456 | /* Options are: TSEC[0-1] */ | |
457 | #define CONFIG_ETHPRIME "TSEC0" | |
458 | ||
89c7784e TT |
459 | #endif |
460 | ||
730e7929 KP |
461 | /* |
462 | * SATA | |
463 | */ | |
464 | #define CONFIG_LIBATA | |
465 | #define CONFIG_FSL_SATA | |
466 | ||
6d0f6bcf | 467 | #define CONFIG_SYS_SATA_MAX_DEVICE 2 |
730e7929 | 468 | #define CONFIG_SATA1 |
6d0f6bcf | 469 | #define CONFIG_SYS_SATA1_OFFSET 0x18000 |
5afe9722 JH |
470 | #define CONFIG_SYS_SATA1 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET) |
471 | #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA | |
730e7929 | 472 | #define CONFIG_SATA2 |
6d0f6bcf | 473 | #define CONFIG_SYS_SATA2_OFFSET 0x19000 |
5afe9722 JH |
474 | #define CONFIG_SYS_SATA2 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET) |
475 | #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA | |
730e7929 KP |
476 | |
477 | #ifdef CONFIG_FSL_SATA | |
478 | #define CONFIG_LBA48 | |
479 | #define CONFIG_CMD_SATA | |
480 | #define CONFIG_DOS_PARTITION | |
481 | #define CONFIG_CMD_EXT2 | |
482 | #endif | |
483 | ||
5e918a98 KP |
484 | /* |
485 | * Environment | |
486 | */ | |
6d0f6bcf | 487 | #ifndef CONFIG_SYS_RAMBOOT |
5a1aceb0 | 488 | #define CONFIG_ENV_IS_IN_FLASH 1 |
5afe9722 JH |
489 | #define CONFIG_ENV_ADDR \ |
490 | (CONFIG_SYS_MONITOR_BASE+CONFIG_SYS_MONITOR_LEN) | |
0e8d1586 JCPV |
491 | #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K (one sector) for env */ |
492 | #define CONFIG_ENV_SIZE 0x4000 | |
5e918a98 | 493 | #else |
5afe9722 | 494 | #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */ |
93f6d725 | 495 | #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ |
6d0f6bcf | 496 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE-0x1000) |
0e8d1586 | 497 | #define CONFIG_ENV_SIZE 0x2000 |
5e918a98 KP |
498 | #endif |
499 | ||
500 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
6d0f6bcf | 501 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
5e918a98 KP |
502 | |
503 | /* | |
504 | * BOOTP options | |
505 | */ | |
506 | #define CONFIG_BOOTP_BOOTFILESIZE | |
507 | #define CONFIG_BOOTP_BOOTPATH | |
508 | #define CONFIG_BOOTP_GATEWAY | |
509 | #define CONFIG_BOOTP_HOSTNAME | |
510 | ||
511 | ||
512 | /* | |
513 | * Command line configuration. | |
514 | */ | |
515 | #include <config_cmd_default.h> | |
516 | ||
517 | #define CONFIG_CMD_PING | |
518 | #define CONFIG_CMD_I2C | |
519 | #define CONFIG_CMD_MII | |
520 | #define CONFIG_CMD_DATE | |
521 | ||
522 | #if defined(CONFIG_PCI) | |
523 | #define CONFIG_CMD_PCI | |
524 | #endif | |
525 | ||
6d0f6bcf | 526 | #if defined(CONFIG_SYS_RAMBOOT) |
bdab39d3 | 527 | #undef CONFIG_CMD_SAVEENV |
5e918a98 KP |
528 | #undef CONFIG_CMD_LOADS |
529 | #endif | |
530 | ||
531 | #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ | |
5afe9722 | 532 | #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ |
5e918a98 KP |
533 | |
534 | #undef CONFIG_WATCHDOG /* watchdog disabled */ | |
535 | ||
c9646ed7 AV |
536 | #define CONFIG_MMC 1 |
537 | ||
538 | #ifdef CONFIG_MMC | |
539 | #define CONFIG_FSL_ESDHC | |
a6da8b81 | 540 | #define CONFIG_FSL_ESDHC_PIN_MUX |
c9646ed7 AV |
541 | #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR |
542 | #define CONFIG_CMD_MMC | |
543 | #define CONFIG_GENERIC_MMC | |
544 | #define CONFIG_CMD_EXT2 | |
545 | #define CONFIG_CMD_FAT | |
546 | #define CONFIG_DOS_PARTITION | |
547 | #endif | |
548 | ||
5e918a98 KP |
549 | /* |
550 | * Miscellaneous configurable options | |
551 | */ | |
5afe9722 JH |
552 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
553 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ | |
554 | #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ | |
5e918a98 KP |
555 | |
556 | #if defined(CONFIG_CMD_KGDB) | |
6d0f6bcf | 557 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
5e918a98 | 558 | #else |
6d0f6bcf | 559 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
5e918a98 KP |
560 | #endif |
561 | ||
5afe9722 JH |
562 | /* Print Buffer Size */ |
563 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) | |
564 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
565 | /* Boot Argument Buffer Size */ | |
566 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE | |
567 | #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ | |
5e918a98 KP |
568 | |
569 | /* | |
570 | * For booting Linux, the board info and command line data | |
9f530d59 | 571 | * have to be in the first 256 MB of memory, since this is |
5e918a98 KP |
572 | * the maximum mapped by the Linux kernel during initialization. |
573 | */ | |
5afe9722 | 574 | #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */ |
5e918a98 KP |
575 | |
576 | /* | |
577 | * Core HID Setup | |
578 | */ | |
1a2e203b | 579 | #define CONFIG_SYS_HID0_INIT 0x000000000 |
5afe9722 JH |
580 | #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK \ |
581 | | HID0_ENABLE_INSTRUCTION_CACHE) | |
6d0f6bcf | 582 | #define CONFIG_SYS_HID2 HID2_HBE |
5e918a98 KP |
583 | |
584 | /* | |
585 | * MMU Setup | |
586 | */ | |
587 | ||
31d82672 BB |
588 | #define CONFIG_HIGH_BATS 1 /* High BATs supported */ |
589 | ||
5e918a98 | 590 | /* DDR: cache cacheable */ |
6d0f6bcf JCPV |
591 | #define CONFIG_SYS_SDRAM_LOWER CONFIG_SYS_SDRAM_BASE |
592 | #define CONFIG_SYS_SDRAM_UPPER (CONFIG_SYS_SDRAM_BASE + 0x10000000) | |
5e918a98 | 593 | |
5afe9722 | 594 | #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_LOWER \ |
72cd4087 | 595 | | BATL_PP_RW \ |
5afe9722 JH |
596 | | BATL_MEMCOHERENCE) |
597 | #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_LOWER \ | |
598 | | BATU_BL_256M \ | |
599 | | BATU_VS \ | |
600 | | BATU_VP) | |
6d0f6bcf JCPV |
601 | #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L |
602 | #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U | |
5e918a98 | 603 | |
5afe9722 | 604 | #define CONFIG_SYS_IBAT1L (CONFIG_SYS_SDRAM_UPPER \ |
72cd4087 | 605 | | BATL_PP_RW \ |
5afe9722 JH |
606 | | BATL_MEMCOHERENCE) |
607 | #define CONFIG_SYS_IBAT1U (CONFIG_SYS_SDRAM_UPPER \ | |
608 | | BATU_BL_256M \ | |
609 | | BATU_VS \ | |
610 | | BATU_VP) | |
6d0f6bcf JCPV |
611 | #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L |
612 | #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U | |
5e918a98 KP |
613 | |
614 | /* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */ | |
5afe9722 | 615 | #define CONFIG_SYS_IBAT2L (CONFIG_SYS_IMMR \ |
72cd4087 | 616 | | BATL_PP_RW \ |
5afe9722 JH |
617 | | BATL_CACHEINHIBIT \ |
618 | | BATL_GUARDEDSTORAGE) | |
619 | #define CONFIG_SYS_IBAT2U (CONFIG_SYS_IMMR \ | |
620 | | BATU_BL_8M \ | |
621 | | BATU_VS \ | |
622 | | BATU_VP) | |
6d0f6bcf JCPV |
623 | #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L |
624 | #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U | |
5e918a98 KP |
625 | |
626 | /* L2 Switch: cache-inhibit and guarded */ | |
5afe9722 | 627 | #define CONFIG_SYS_IBAT3L (CONFIG_SYS_VSC7385_BASE \ |
72cd4087 | 628 | | BATL_PP_RW \ |
5afe9722 JH |
629 | | BATL_CACHEINHIBIT \ |
630 | | BATL_GUARDEDSTORAGE) | |
631 | #define CONFIG_SYS_IBAT3U (CONFIG_SYS_VSC7385_BASE \ | |
632 | | BATU_BL_128K \ | |
633 | | BATU_VS \ | |
634 | | BATU_VP) | |
6d0f6bcf JCPV |
635 | #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L |
636 | #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U | |
5e918a98 KP |
637 | |
638 | /* FLASH: icache cacheable, but dcache-inhibit and guarded */ | |
5afe9722 | 639 | #define CONFIG_SYS_IBAT4L (CONFIG_SYS_FLASH_BASE \ |
72cd4087 | 640 | | BATL_PP_RW \ |
5afe9722 JH |
641 | | BATL_MEMCOHERENCE) |
642 | #define CONFIG_SYS_IBAT4U (CONFIG_SYS_FLASH_BASE \ | |
643 | | BATU_BL_32M \ | |
644 | | BATU_VS \ | |
645 | | BATU_VP) | |
646 | #define CONFIG_SYS_DBAT4L (CONFIG_SYS_FLASH_BASE \ | |
72cd4087 | 647 | | BATL_PP_RW \ |
5afe9722 JH |
648 | | BATL_CACHEINHIBIT \ |
649 | | BATL_GUARDEDSTORAGE) | |
6d0f6bcf | 650 | #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U |
5e918a98 KP |
651 | |
652 | /* Stack in dcache: cacheable, no memory coherence */ | |
72cd4087 | 653 | #define CONFIG_SYS_IBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW) |
5afe9722 JH |
654 | #define CONFIG_SYS_IBAT5U (CONFIG_SYS_INIT_RAM_ADDR \ |
655 | | BATU_BL_128K \ | |
656 | | BATU_VS \ | |
657 | | BATU_VP) | |
6d0f6bcf JCPV |
658 | #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L |
659 | #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U | |
5e918a98 KP |
660 | |
661 | #ifdef CONFIG_PCI | |
662 | /* PCI MEM space: cacheable */ | |
5afe9722 | 663 | #define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI_MEM_PHYS \ |
72cd4087 | 664 | | BATL_PP_RW \ |
5afe9722 JH |
665 | | BATL_MEMCOHERENCE) |
666 | #define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI_MEM_PHYS \ | |
667 | | BATU_BL_256M \ | |
668 | | BATU_VS \ | |
669 | | BATU_VP) | |
6d0f6bcf JCPV |
670 | #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L |
671 | #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U | |
5e918a98 | 672 | /* PCI MMIO space: cache-inhibit and guarded */ |
5afe9722 | 673 | #define CONFIG_SYS_IBAT7L (CONFIG_SYS_PCI_MMIO_PHYS \ |
72cd4087 | 674 | | BATL_PP_RW \ |
5afe9722 JH |
675 | | BATL_CACHEINHIBIT \ |
676 | | BATL_GUARDEDSTORAGE) | |
677 | #define CONFIG_SYS_IBAT7U (CONFIG_SYS_PCI_MMIO_PHYS \ | |
678 | | BATU_BL_256M \ | |
679 | | BATU_VS \ | |
680 | | BATU_VP) | |
6d0f6bcf JCPV |
681 | #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L |
682 | #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U | |
5e918a98 | 683 | #else |
6d0f6bcf JCPV |
684 | #define CONFIG_SYS_IBAT6L (0) |
685 | #define CONFIG_SYS_IBAT6U (0) | |
686 | #define CONFIG_SYS_IBAT7L (0) | |
687 | #define CONFIG_SYS_IBAT7U (0) | |
688 | #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L | |
689 | #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U | |
690 | #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L | |
691 | #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U | |
5e918a98 KP |
692 | #endif |
693 | ||
5e918a98 KP |
694 | #if defined(CONFIG_CMD_KGDB) |
695 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ | |
696 | #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ | |
697 | #endif | |
698 | ||
699 | /* | |
700 | * Environment Configuration | |
701 | */ | |
702 | #define CONFIG_ENV_OVERWRITE | |
703 | ||
18e69a35 AV |
704 | #define CONFIG_HAS_FSL_DR_USB |
705 | ||
5afe9722 | 706 | #define CONFIG_NETDEV "eth1" |
5e918a98 KP |
707 | |
708 | #define CONFIG_HOSTNAME mpc837x_rdb | |
8b3637c6 | 709 | #define CONFIG_ROOTPATH "/nfsroot" |
5afe9722 | 710 | #define CONFIG_RAMDISKFILE "rootfs.ext2.gz.uboot" |
b3f44c21 | 711 | #define CONFIG_BOOTFILE "uImage" |
5afe9722 JH |
712 | /* U-Boot image on TFTP server */ |
713 | #define CONFIG_UBOOTPATH "u-boot.bin" | |
714 | #define CONFIG_FDTFILE "mpc8379_rdb.dtb" | |
5e918a98 | 715 | |
5afe9722 JH |
716 | /* default location for tftp and bootm */ |
717 | #define CONFIG_LOADADDR 800000 | |
7fd0bea2 | 718 | #define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */ |
5e918a98 KP |
719 | #define CONFIG_BAUDRATE 115200 |
720 | ||
5e918a98 | 721 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
5afe9722 JH |
722 | "netdev=" CONFIG_NETDEV "\0" \ |
723 | "uboot=" CONFIG_UBOOTPATH "\0" \ | |
5e918a98 | 724 | "tftpflash=tftp $loadaddr $uboot;" \ |
5368c55d MV |
725 | "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \ |
726 | " +$filesize; " \ | |
727 | "erase " __stringify(CONFIG_SYS_TEXT_BASE) \ | |
728 | " +$filesize; " \ | |
729 | "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ | |
730 | " $filesize; " \ | |
731 | "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \ | |
732 | " +$filesize; " \ | |
733 | "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ | |
734 | " $filesize\0" \ | |
79f516bc | 735 | "fdtaddr=780000\0" \ |
5afe9722 | 736 | "fdtfile=" CONFIG_FDTFILE "\0" \ |
5e918a98 | 737 | "ramdiskaddr=1000000\0" \ |
5afe9722 | 738 | "ramdiskfile=" CONFIG_RAMDISKFILE "\0" \ |
5e918a98 KP |
739 | "console=ttyS0\0" \ |
740 | "setbootargs=setenv bootargs " \ | |
741 | "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \ | |
742 | "setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \ | |
5afe9722 JH |
743 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \ |
744 | "$netdev:off " \ | |
5e918a98 KP |
745 | "root=$rootdev rw console=$console,$baudrate $othbootargs\0" |
746 | ||
747 | #define CONFIG_NFSBOOTCOMMAND \ | |
748 | "setenv rootdev /dev/nfs;" \ | |
749 | "run setbootargs;" \ | |
750 | "run setipargs;" \ | |
751 | "tftp $loadaddr $bootfile;" \ | |
752 | "tftp $fdtaddr $fdtfile;" \ | |
753 | "bootm $loadaddr - $fdtaddr" | |
754 | ||
755 | #define CONFIG_RAMBOOTCOMMAND \ | |
756 | "setenv rootdev /dev/ram;" \ | |
757 | "run setbootargs;" \ | |
758 | "tftp $ramdiskaddr $ramdiskfile;" \ | |
759 | "tftp $loadaddr $bootfile;" \ | |
760 | "tftp $fdtaddr $fdtfile;" \ | |
761 | "bootm $loadaddr $ramdiskaddr $fdtaddr" | |
762 | ||
5e918a98 | 763 | #endif /* __CONFIG_H */ |