projects / people / ms / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 129ba616 | 1 | /* |
| 7c57f3e8 | 2 | * Copyright 2007-2008,2010-2011 Freescale Semiconductor, Inc. |
| 129ba616 KG |
3 | * |
| 4 | * See file CREDITS for list of people who contributed to this | |
| 5 | * project. | |
| 6 | * | |
| 7 | * This program is free software; you can redistribute it and/or | |
| 8 | * modify it under the terms of the GNU General Public License as | |
| 9 | * published by the Free Software Foundation; either version 2 of | |
| 10 | * the License, or (at your option) any later version. | |
| 11 | * | |
| 12 | * This program is distributed in the hope that it will be useful, | |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 15 | * GNU General Public License for more details. | |
| 16 | * | |
| 17 | * You should have received a copy of the GNU General Public License | |
| 18 | * along with this program; if not, write to the Free Software | |
| 19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
| 20 | * MA 02111-1307 USA | |
| 21 | */ | |
| 22 | ||
| 23 | /* | |
| 24 | * mpc8572ds board configuration file | |
| 25 | * | |
| 26 | */ | |
| 27 | #ifndef __CONFIG_H | |
| 28 | #define __CONFIG_H | |
| 29 | ||
| 509c4c4c KG |
30 | #include "../board/freescale/common/ics307_clk.h" |
| 31 | ||
| d24f2d32 | 32 | #ifdef CONFIG_36BIT |
| f9edcc10 KG |
33 | #define CONFIG_PHYS_64BIT |
| 34 | #endif | |
| 35 | ||
| cb14e93b KG |
36 | #ifdef CONFIG_NAND |
| 37 | #define CONFIG_NAND_U_BOOT | |
| 38 | #define CONFIG_RAMBOOT_NAND | |
| 39 | #ifdef CONFIG_NAND_SPL | |
| 40 | #define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000 | |
| 41 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */ | |
| 42 | #else | |
| 00203c64 | 43 | #define CONFIG_SYS_LDSCRIPT $(TOPDIR)/$(CPUDIR)/u-boot-nand.lds |
| cb14e93b KG |
44 | #define CONFIG_SYS_TEXT_BASE 0xf8f82000 |
| 45 | #endif /* CONFIG_NAND_SPL */ | |
| 46 | #endif | |
| 47 | ||
| 48 | #ifndef CONFIG_SYS_TEXT_BASE | |
| 49 | #define CONFIG_SYS_TEXT_BASE 0xeff80000 | |
| 50 | #endif | |
| 51 | ||
| 7a577fda KG |
52 | #ifndef CONFIG_RESET_VECTOR_ADDRESS |
| 53 | #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc | |
| 54 | #endif | |
| 55 | ||
| cb14e93b KG |
56 | #ifndef CONFIG_SYS_MONITOR_BASE |
| 57 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ | |
| 58 | #endif | |
| 59 | ||
| 129ba616 KG |
60 | /* High Level Configuration Options */ |
| 61 | #define CONFIG_BOOKE 1 /* BOOKE */ | |
| 62 | #define CONFIG_E500 1 /* BOOKE e500 family */ | |
| 63 | #define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */ | |
| 64 | #define CONFIG_MPC8572 1 | |
| 65 | #define CONFIG_MPC8572DS 1 | |
| 66 | #define CONFIG_MP 1 /* support multiple processors */ | |
| 129ba616 | 67 | |
| c51fc5d5 | 68 | #define CONFIG_FSL_ELBC 1 /* Has Enhanced localbus controller */ |
| 129ba616 KG |
69 | #define CONFIG_PCI 1 /* Enable PCI/PCIE */ |
| 70 | #define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */ | |
| 71 | #define CONFIG_PCIE2 1 /* PCIE controler 2 (slot 2) */ | |
| 72 | #define CONFIG_PCIE3 1 /* PCIE controler 3 (ULI bridge) */ | |
| 73 | #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ | |
| 74 | #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ | |
| 0151cbac | 75 | #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ |
| 129ba616 KG |
76 | |
| 77 | #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ | |
| 78 | ||
| 79 | #define CONFIG_TSEC_ENET /* tsec ethernet support */ | |
| 80 | #define CONFIG_ENV_OVERWRITE | |
| 81 | ||
| 509c4c4c KG |
82 | #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */ |
| 83 | #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() /* ddrclk for MPC85xx */ | |
| 4ca06607 | 84 | #define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */ |
| 129ba616 KG |
85 | |
| 86 | /* | |
| 87 | * These can be toggled for performance analysis, otherwise use default. | |
| 88 | */ | |
| 89 | #define CONFIG_L2_CACHE /* toggle L2 cache */ | |
| 90 | #define CONFIG_BTB /* toggle branch predition */ | |
| 129ba616 KG |
91 | |
| 92 | #define CONFIG_ENABLE_36BIT_PHYS 1 | |
| 93 | ||
| 18af1c5f KG |
94 | #ifdef CONFIG_PHYS_64BIT |
| 95 | #define CONFIG_ADDR_MAP 1 | |
| 96 | #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ | |
| 97 | #endif | |
| 98 | ||
| 6d0f6bcf JCPV |
99 | #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */ |
| 100 | #define CONFIG_SYS_MEMTEST_END 0x7fffffff | |
| 129ba616 KG |
101 | #define CONFIG_PANIC_HANG /* do not reset board on panic */ |
| 102 | ||
| cb14e93b KG |
103 | /* |
| 104 | * Config the L2 Cache as L2 SRAM | |
| 105 | */ | |
| 106 | #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 | |
| 107 | #ifdef CONFIG_PHYS_64BIT | |
| 108 | #define CONFIG_SYS_INIT_L2_ADDR_PHYS 0xff8f80000ull | |
| 109 | #else | |
| 110 | #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR | |
| 111 | #endif | |
| 112 | #define CONFIG_SYS_L2_SIZE (512 << 10) | |
| 113 | #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) | |
| 114 | ||
| 129ba616 KG |
115 | /* |
| 116 | * Base addresses -- Note these are effective addresses where the | |
| 117 | * actual resources get mapped (not physical addresses) | |
| 118 | */ | |
| 6d0f6bcf | 119 | #define CONFIG_SYS_CCSRBAR 0xffe00000 /* relocated CCSRBAR */ |
| 18af1c5f KG |
120 | #ifdef CONFIG_PHYS_64BIT |
| 121 | #define CONFIG_SYS_CCSRBAR_PHYS 0xfffe00000ull /* physical addr of CCSRBAR */ | |
| 122 | #else | |
| 6d0f6bcf | 123 | #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */ |
| 18af1c5f | 124 | #endif |
| 6d0f6bcf | 125 | #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ |
| 129ba616 | 126 | |
| cb14e93b KG |
127 | #if defined(CONFIG_RAMBOOT_NAND) && !defined(CONFIG_NAND_SPL) |
| 128 | #define CONFIG_SYS_CCSRBAR_DEFAULT CONFIG_SYS_CCSRBAR | |
| 129 | #else | |
| 130 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ | |
| 131 | #endif | |
| 132 | ||
| 129ba616 | 133 | /* DDR Setup */ |
| f8523cb0 | 134 | #define CONFIG_VERY_BIG_RAM |
| 129ba616 KG |
135 | #define CONFIG_FSL_DDR2 |
| 136 | #undef CONFIG_FSL_DDR_INTERACTIVE | |
| 137 | #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ | |
| 138 | #define CONFIG_DDR_SPD | |
| 129ba616 | 139 | |
| d34897d3 | 140 | #define CONFIG_DDR_ECC |
| 9b0ad1b1 | 141 | #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER |
| 129ba616 KG |
142 | #define CONFIG_MEM_INIT_VALUE 0xDeadBeef |
| 143 | ||
| 6d0f6bcf JCPV |
144 | #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 |
| 145 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE | |
| 129ba616 KG |
146 | |
| 147 | #define CONFIG_NUM_DDR_CONTROLLERS 2 | |
| 148 | #define CONFIG_DIMM_SLOTS_PER_CTLR 1 | |
| 149 | #define CONFIG_CHIP_SELECTS_PER_CTRL 2 | |
| 150 | ||
| 151 | /* I2C addresses of SPD EEPROMs */ | |
| 6d0f6bcf | 152 | #define CONFIG_SYS_SPD_BUS_NUM 1 /* SPD EEPROMS locate on I2C bus 1 */ |
| 129ba616 KG |
153 | #define SPD_EEPROM_ADDRESS1 0x51 /* CTLR 0 DIMM 0 */ |
| 154 | #define SPD_EEPROM_ADDRESS2 0x52 /* CTLR 1 DIMM 0 */ | |
| 155 | ||
| 156 | /* These are used when DDR doesn't use SPD. */ | |
| dc889e86 DL |
157 | #define CONFIG_SYS_SDRAM_SIZE 512 /* DDR is 512MB */ |
| 158 | #define CONFIG_SYS_DDR_CS0_BNDS 0x0000001F | |
| 159 | #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010202 /* Enable, no interleaving */ | |
| 160 | #define CONFIG_SYS_DDR_TIMING_3 0x00020000 | |
| 161 | #define CONFIG_SYS_DDR_TIMING_0 0x00260802 | |
| 162 | #define CONFIG_SYS_DDR_TIMING_1 0x626b2634 | |
| 163 | #define CONFIG_SYS_DDR_TIMING_2 0x062874cf | |
| 164 | #define CONFIG_SYS_DDR_MODE_1 0x00440462 | |
| 6d0f6bcf | 165 | #define CONFIG_SYS_DDR_MODE_2 0x00000000 |
| dc889e86 | 166 | #define CONFIG_SYS_DDR_INTERVAL 0x0c300100 |
| 6d0f6bcf | 167 | #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef |
| dc889e86 DL |
168 | #define CONFIG_SYS_DDR_CLK_CTRL 0x00800000 |
| 169 | #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000 | |
| 6d0f6bcf | 170 | #define CONFIG_SYS_DDR_OCD_STATUS 0x00000000 |
| dc889e86 DL |
171 | #define CONFIG_SYS_DDR_CONTROL 0xc3000008 /* Type = DDR2 */ |
| 172 | #define CONFIG_SYS_DDR_CONTROL2 0x24400000 | |
| 6d0f6bcf JCPV |
173 | |
| 174 | #define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d | |
| 175 | #define CONFIG_SYS_DDR_ERR_DIS 0x00000000 | |
| 176 | #define CONFIG_SYS_DDR_SBE 0x00010000 | |
| 129ba616 | 177 | |
| 129ba616 KG |
178 | /* |
| 179 | * Make sure required options are set | |
| 180 | */ | |
| 181 | #ifndef CONFIG_SPD_EEPROM | |
| 182 | #error ("CONFIG_SPD_EEPROM is required") | |
| 183 | #endif | |
| 184 | ||
| 185 | #undef CONFIG_CLOCKS_IN_MHZ | |
| 186 | ||
| 187 | /* | |
| 188 | * Memory map | |
| 189 | * | |
| 190 | * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable | |
| 191 | * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable | |
| 192 | * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable | |
| 193 | * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable | |
| 194 | * | |
| 195 | * Localbus cacheable (TBD) | |
| 196 | * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable | |
| 197 | * | |
| 198 | * Localbus non-cacheable | |
| 199 | * 0xe000_0000 0xe80f_ffff Promjet/free 128M non-cacheable | |
| 200 | * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable | |
| 3cbd8231 | 201 | * 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable |
| 129ba616 KG |
202 | * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0 |
| 203 | * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 | |
| 204 | * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable | |
| 205 | */ | |
| 206 | ||
| 207 | /* | |
| 208 | * Local Bus Definitions | |
| 209 | */ | |
| 6d0f6bcf | 210 | #define CONFIG_SYS_FLASH_BASE 0xe0000000 /* start of FLASH 128M */ |
| 18af1c5f KG |
211 | #ifdef CONFIG_PHYS_64BIT |
| 212 | #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull | |
| 213 | #else | |
| c953ddfd | 214 | #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE |
| 18af1c5f | 215 | #endif |
| 129ba616 | 216 | |
| cb14e93b KG |
217 | |
| 218 | #define CONFIG_FLASH_BR_PRELIM \ | |
| 219 | (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) \ | |
| 220 | | BR_PS_16 | BR_V) | |
| 221 | #define CONFIG_FLASH_OR_PRELIM 0xf8000ff7 | |
| 129ba616 | 222 | |
| c953ddfd KG |
223 | #define CONFIG_SYS_BR1_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V) |
| 224 | #define CONFIG_SYS_OR1_PRELIM 0xf8000ff7 | |
| 129ba616 | 225 | |
| 18af1c5f | 226 | #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} |
| 6d0f6bcf | 227 | #define CONFIG_SYS_FLASH_QUIET_TEST |
| 129ba616 KG |
228 | #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ |
| 229 | ||
| 6d0f6bcf JCPV |
230 | #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ |
| 231 | #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ | |
| 232 | #undef CONFIG_SYS_FLASH_CHECKSUM | |
| 233 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ | |
| 234 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ | |
| 129ba616 | 235 | |
| cb14e93b KG |
236 | #if defined(CONFIG_RAMBOOT_NAND) |
| 237 | #define CONFIG_SYS_RAMBOOT | |
| 238 | #define CONFIG_SYS_EXTRA_ENV_RELOC | |
| 239 | #else | |
| 240 | #undef CONFIG_SYS_RAMBOOT | |
| 241 | #endif | |
| 129ba616 KG |
242 | |
| 243 | #define CONFIG_FLASH_CFI_DRIVER | |
| 6d0f6bcf JCPV |
244 | #define CONFIG_SYS_FLASH_CFI |
| 245 | #define CONFIG_SYS_FLASH_EMPTY_INFO | |
| 246 | #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 | |
| 129ba616 KG |
247 | |
| 248 | #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ | |
| 249 | ||
| 558710b9 | 250 | #define CONFIG_HWCONFIG /* enable hwconfig */ |
| 129ba616 KG |
251 | #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */ |
| 252 | #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */ | |
| 18af1c5f KG |
253 | #ifdef CONFIG_PHYS_64BIT |
| 254 | #define PIXIS_BASE_PHYS 0xfffdf0000ull | |
| 255 | #else | |
| 52b565f5 | 256 | #define PIXIS_BASE_PHYS PIXIS_BASE |
| 18af1c5f | 257 | #endif |
| 129ba616 | 258 | |
| 52b565f5 | 259 | #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V) |
| 6d0f6bcf | 260 | #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */ |
| 129ba616 KG |
261 | |
| 262 | #define PIXIS_ID 0x0 /* Board ID at offset 0 */ | |
| 263 | #define PIXIS_VER 0x1 /* Board version at offset 1 */ | |
| 264 | #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */ | |
| 265 | #define PIXIS_CSR 0x3 /* PIXIS General control/status register */ | |
| 266 | #define PIXIS_RST 0x4 /* PIXIS Reset Control register */ | |
| 267 | #define PIXIS_PWR 0x5 /* PIXIS Power status register */ | |
| 268 | #define PIXIS_AUX 0x6 /* Auxiliary 1 register */ | |
| 269 | #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */ | |
| 270 | #define PIXIS_AUX2 0x8 /* Auxiliary 2 register */ | |
| 271 | #define PIXIS_VCTL 0x10 /* VELA Control Register */ | |
| 272 | #define PIXIS_VSTAT 0x11 /* VELA Status Register */ | |
| 273 | #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */ | |
| 274 | #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */ | |
| 275 | #define PIXIS_VCORE0 0x14 /* VELA VCORE0 Register */ | |
| 276 | #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */ | |
| 6bb5b412 KG |
277 | #define PIXIS_VBOOT_LBMAP 0xc0 /* VBOOT - CFG_LBMAP */ |
| 278 | #define PIXIS_VBOOT_LBMAP_NOR0 0x00 /* cfg_lbmap - boot from NOR 0 */ | |
| 279 | #define PIXIS_VBOOT_LBMAP_PJET 0x01 /* cfg_lbmap - boot from projet */ | |
| 280 | #define PIXIS_VBOOT_LBMAP_NAND 0x02 /* cfg_lbmap - boot from NAND */ | |
| 281 | #define PIXIS_VBOOT_LBMAP_NOR1 0x03 /* cfg_lbmap - boot from NOR 1 */ | |
| 129ba616 KG |
282 | #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */ |
| 283 | #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ | |
| 284 | #define PIXIS_VSPEED2 0x19 /* VELA VSpeed 2 */ | |
| 285 | #define PIXIS_VSYSCLK0 0x1C /* VELA SYSCLK0 Register */ | |
| 286 | #define PIXIS_VSYSCLK1 0x1D /* VELA SYSCLK1 Register */ | |
| 287 | #define PIXIS_VSYSCLK2 0x1E /* VELA SYSCLK2 Register */ | |
| 288 | #define PIXIS_VDDRCLK0 0x1F /* VELA DDRCLK0 Register */ | |
| 289 | #define PIXIS_VDDRCLK1 0x20 /* VELA DDRCLK1 Register */ | |
| 290 | #define PIXIS_VDDRCLK2 0x21 /* VELA DDRCLK2 Register */ | |
| 291 | #define PIXIS_VWATCH 0x24 /* Watchdog Register */ | |
| 292 | #define PIXIS_LED 0x25 /* LED Register */ | |
| 293 | ||
| cb14e93b KG |
294 | #define PIXIS_SPD_SYSCLK_MASK 0x7 /* SYSCLK option */ |
| 295 | ||
| 129ba616 KG |
296 | /* old pixis referenced names */ |
| 297 | #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ | |
| 298 | #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ | |
| 6d0f6bcf | 299 | #define CONFIG_SYS_PIXIS_VBOOT_MASK 0xc0 |
| 7e183cad LY |
300 | #define PIXIS_VSPEED2_TSEC1SER 0x8 |
| 301 | #define PIXIS_VSPEED2_TSEC2SER 0x4 | |
| 302 | #define PIXIS_VSPEED2_TSEC3SER 0x2 | |
| 303 | #define PIXIS_VSPEED2_TSEC4SER 0x1 | |
| 304 | #define PIXIS_VCFGEN1_TSEC1SER 0x20 | |
| 305 | #define PIXIS_VCFGEN1_TSEC2SER 0x20 | |
| 306 | #define PIXIS_VCFGEN1_TSEC3SER 0x20 | |
| 307 | #define PIXIS_VCFGEN1_TSEC4SER 0x20 | |
| 308 | #define PIXIS_VSPEED2_MASK (PIXIS_VSPEED2_TSEC1SER \ | |
| 309 | | PIXIS_VSPEED2_TSEC2SER \ | |
| 310 | | PIXIS_VSPEED2_TSEC3SER \ | |
| 311 | | PIXIS_VSPEED2_TSEC4SER) | |
| 312 | #define PIXIS_VCFGEN1_MASK (PIXIS_VCFGEN1_TSEC1SER \ | |
| 313 | | PIXIS_VCFGEN1_TSEC2SER \ | |
| 314 | | PIXIS_VCFGEN1_TSEC3SER \ | |
| 315 | | PIXIS_VCFGEN1_TSEC4SER) | |
| 129ba616 | 316 | |
| 6d0f6bcf JCPV |
317 | #define CONFIG_SYS_INIT_RAM_LOCK 1 |
| 318 | #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ | |
| 553f0982 | 319 | #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */ |
| 129ba616 | 320 | |
| 25ddd1fb | 321 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
| 6d0f6bcf | 322 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
| 129ba616 | 323 | |
| 6d0f6bcf JCPV |
324 | #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ |
| 325 | #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ | |
| 129ba616 | 326 | |
| cb14e93b | 327 | #ifndef CONFIG_NAND_SPL |
| c013b749 | 328 | #define CONFIG_SYS_NAND_BASE 0xffa00000 |
| 18af1c5f KG |
329 | #ifdef CONFIG_PHYS_64BIT |
| 330 | #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull | |
| 331 | #else | |
| c013b749 | 332 | #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE |
| 18af1c5f | 333 | #endif |
| cb14e93b KG |
334 | #else |
| 335 | #define CONFIG_SYS_NAND_BASE 0xfff00000 | |
| 336 | #ifdef CONFIG_PHYS_64BIT | |
| 337 | #define CONFIG_SYS_NAND_BASE_PHYS 0xffff00000ull | |
| 338 | #else | |
| 339 | #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE | |
| 340 | #endif | |
| 341 | #endif | |
| 342 | ||
| c013b749 HW |
343 | #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE,\ |
| 344 | CONFIG_SYS_NAND_BASE + 0x40000, \ | |
| 345 | CONFIG_SYS_NAND_BASE + 0x80000,\ | |
| 346 | CONFIG_SYS_NAND_BASE + 0xC0000} | |
| 347 | #define CONFIG_SYS_MAX_NAND_DEVICE 4 | |
| c013b749 | 348 | #define CONFIG_MTD_NAND_VERIFY_WRITE |
| 3cbd8231 WD |
349 | #define CONFIG_CMD_NAND 1 |
| 350 | #define CONFIG_NAND_FSL_ELBC 1 | |
| c013b749 HW |
351 | #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) |
| 352 | ||
| cb14e93b KG |
353 | /* NAND boot: 4K NAND loader config */ |
| 354 | #define CONFIG_SYS_NAND_SPL_SIZE 0x1000 | |
| 355 | #define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) - 0x2000) | |
| 356 | #define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR) | |
| 357 | #define CONFIG_SYS_NAND_U_BOOT_START \ | |
| 358 | (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE) | |
| 359 | #define CONFIG_SYS_NAND_U_BOOT_OFFS (0) | |
| 360 | #define CONFIG_SYS_NAND_U_BOOT_RELOC (CONFIG_SYS_INIT_L2_END - 0x2000) | |
| 361 | #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) | |
| 362 | ||
| 363 | ||
| c013b749 | 364 | /* NAND flash config */ |
| a3055c58 | 365 | #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ |
| 3cbd8231 WD |
366 | | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ |
| 367 | | BR_PS_8 /* Port Size = 8 bit */ \ | |
| 368 | | BR_MS_FCM /* MSEL = FCM */ \ | |
| 369 | | BR_V) /* valid */ | |
| a3055c58 | 370 | #define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \ |
| 3cbd8231 WD |
371 | | OR_FCM_PGS /* Large Page*/ \ |
| 372 | | OR_FCM_CSCT \ | |
| 373 | | OR_FCM_CST \ | |
| 374 | | OR_FCM_CHT \ | |
| 375 | | OR_FCM_SCY_1 \ | |
| 376 | | OR_FCM_TRLX \ | |
| 377 | | OR_FCM_EHTR) | |
| c013b749 | 378 | |
| cb14e93b | 379 | #ifdef CONFIG_RAMBOOT_NAND |
| a3055c58 MM |
380 | #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ |
| 381 | #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ | |
| cb14e93b KG |
382 | #define CONFIG_SYS_BR2_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ |
| 383 | #define CONFIG_SYS_OR2_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ | |
| 384 | #else | |
| 385 | #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ | |
| 386 | #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ | |
| a3055c58 MM |
387 | #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ |
| 388 | #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ | |
| cb14e93b | 389 | #endif |
| 72a9414a | 390 | #define CONFIG_SYS_BR4_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x40000))\ |
| 3cbd8231 WD |
391 | | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ |
| 392 | | BR_PS_8 /* Port Size = 8 bit */ \ | |
| 393 | | BR_MS_FCM /* MSEL = FCM */ \ | |
| 394 | | BR_V) /* valid */ | |
| a3055c58 | 395 | #define CONFIG_SYS_OR4_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ |
| 72a9414a | 396 | #define CONFIG_SYS_BR5_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x80000))\ |
| 3cbd8231 WD |
397 | | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ |
| 398 | | BR_PS_8 /* Port Size = 8 bit */ \ | |
| 399 | | BR_MS_FCM /* MSEL = FCM */ \ | |
| 400 | | BR_V) /* valid */ | |
| a3055c58 | 401 | #define CONFIG_SYS_OR5_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ |
| c013b749 | 402 | |
| 72a9414a | 403 | #define CONFIG_SYS_BR6_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0xc0000))\ |
| 3cbd8231 WD |
404 | | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ |
| 405 | | BR_PS_8 /* Port Size = 8 bit */ \ | |
| 406 | | BR_MS_FCM /* MSEL = FCM */ \ | |
| 407 | | BR_V) /* valid */ | |
| a3055c58 | 408 | #define CONFIG_SYS_OR6_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ |
| c013b749 HW |
409 | |
| 410 | ||
| 129ba616 KG |
411 | /* Serial Port - controlled on board with jumper J8 |
| 412 | * open - index 2 | |
| 413 | * shorted - index 1 | |
| 414 | */ | |
| 415 | #define CONFIG_CONS_INDEX 1 | |
| 6d0f6bcf JCPV |
416 | #define CONFIG_SYS_NS16550 |
| 417 | #define CONFIG_SYS_NS16550_SERIAL | |
| 418 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
| 419 | #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) | |
| cb14e93b KG |
420 | #ifdef CONFIG_NAND_SPL |
| 421 | #define CONFIG_NS16550_MIN_FUNCTIONS | |
| 422 | #endif | |
| 129ba616 | 423 | |
| 6d0f6bcf | 424 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
| 129ba616 KG |
425 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} |
| 426 | ||
| 6d0f6bcf JCPV |
427 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) |
| 428 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) | |
| 129ba616 KG |
429 | |
| 430 | /* Use the HUSH parser */ | |
| 6d0f6bcf JCPV |
431 | #define CONFIG_SYS_HUSH_PARSER |
| 432 | #ifdef CONFIG_SYS_HUSH_PARSER | |
| 433 | #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " | |
| 129ba616 KG |
434 | #endif |
| 435 | ||
| 436 | /* | |
| 437 | * Pass open firmware flat tree | |
| 438 | */ | |
| 439 | #define CONFIG_OF_LIBFDT 1 | |
| 440 | #define CONFIG_OF_BOARD_SETUP 1 | |
| 441 | #define CONFIG_OF_STDOUT_VIA_ALIAS 1 | |
| 442 | ||
| 129ba616 KG |
443 | /* new uImage format support */ |
| 444 | #define CONFIG_FIT 1 | |
| 445 | #define CONFIG_FIT_VERBOSE 1 /* enable fit_format_{error,warning}() */ | |
| 446 | ||
| 447 | /* I2C */ | |
| 448 | #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ | |
| 449 | #define CONFIG_HARD_I2C /* I2C with hardware support */ | |
| 450 | #undef CONFIG_SOFT_I2C /* I2C bit-banged */ | |
| 1f3ba317 | 451 | #define CONFIG_I2C_MULTI_BUS |
| 6d0f6bcf JCPV |
452 | #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ |
| 453 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 | |
| 454 | #define CONFIG_SYS_I2C_SLAVE 0x7F | |
| 455 | #define CONFIG_SYS_I2C_NOPROBES {{0,0x29}}/* Don't probe these addrs */ | |
| 456 | #define CONFIG_SYS_I2C_OFFSET 0x3000 | |
| 457 | #define CONFIG_SYS_I2C2_OFFSET 0x3100 | |
| 129ba616 | 458 | |
| 445a7b38 HW |
459 | /* |
| 460 | * I2C2 EEPROM | |
| 461 | */ | |
| 462 | #define CONFIG_ID_EEPROM | |
| 463 | #ifdef CONFIG_ID_EEPROM | |
| 6d0f6bcf | 464 | #define CONFIG_SYS_I2C_EEPROM_NXID |
| 445a7b38 | 465 | #endif |
| 6d0f6bcf JCPV |
466 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 |
| 467 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 | |
| 468 | #define CONFIG_SYS_EEPROM_BUS_NUM 1 | |
| 445a7b38 | 469 | |
| 129ba616 KG |
470 | /* |
| 471 | * General PCI | |
| 472 | * Memory space is mapped 1-1, but I/O space must start from 0. | |
| 473 | */ | |
| 474 | ||
| 129ba616 | 475 | /* controller 3, direct to uli, tgtid 3, Base address 8000 */ |
| 18ea5551 | 476 | #define CONFIG_SYS_PCIE3_NAME "ULI" |
| 5af0fdd8 | 477 | #define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000 |
| 18af1c5f | 478 | #ifdef CONFIG_PHYS_64BIT |
| 156984a3 | 479 | #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 |
| 18af1c5f KG |
480 | #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc00000000ull |
| 481 | #else | |
| ad97dce1 | 482 | #define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000 |
| 5af0fdd8 | 483 | #define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000 |
| 18af1c5f | 484 | #endif |
| 6d0f6bcf | 485 | #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ |
| aca5f018 | 486 | #define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000 |
| 5f91ef6a | 487 | #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 |
| 18af1c5f KG |
488 | #ifdef CONFIG_PHYS_64BIT |
| 489 | #define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc00000ull | |
| 490 | #else | |
| 6d0f6bcf | 491 | #define CONFIG_SYS_PCIE3_IO_PHYS 0xffc00000 |
| 18af1c5f | 492 | #endif |
| 6d0f6bcf | 493 | #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ |
| 129ba616 KG |
494 | |
| 495 | /* controller 2, Slot 2, tgtid 2, Base address 9000 */ | |
| 18ea5551 | 496 | #define CONFIG_SYS_PCIE2_NAME "Slot 1" |
| 5af0fdd8 | 497 | #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 |
| 18af1c5f | 498 | #ifdef CONFIG_PHYS_64BIT |
| 156984a3 | 499 | #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 |
| 18af1c5f KG |
500 | #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull |
| 501 | #else | |
| ad97dce1 | 502 | #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 |
| 5af0fdd8 | 503 | #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 |
| 18af1c5f | 504 | #endif |
| 6d0f6bcf | 505 | #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ |
| aca5f018 | 506 | #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 |
| 5f91ef6a | 507 | #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 |
| 18af1c5f KG |
508 | #ifdef CONFIG_PHYS_64BIT |
| 509 | #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull | |
| 510 | #else | |
| 6d0f6bcf | 511 | #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 |
| 18af1c5f | 512 | #endif |
| 6d0f6bcf | 513 | #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ |
| 129ba616 KG |
514 | |
| 515 | /* controller 1, Slot 1, tgtid 1, Base address a000 */ | |
| 18ea5551 | 516 | #define CONFIG_SYS_PCIE1_NAME "Slot 2" |
| 5af0fdd8 | 517 | #define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000 |
| 18af1c5f | 518 | #ifdef CONFIG_PHYS_64BIT |
| 156984a3 | 519 | #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 |
| 18af1c5f KG |
520 | #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull |
| 521 | #else | |
| ad97dce1 | 522 | #define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000 |
| 5af0fdd8 | 523 | #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000 |
| 18af1c5f | 524 | #endif |
| 6d0f6bcf | 525 | #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ |
| aca5f018 | 526 | #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000 |
| 5f91ef6a | 527 | #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 |
| 18af1c5f KG |
528 | #ifdef CONFIG_PHYS_64BIT |
| 529 | #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc20000ull | |
| 530 | #else | |
| 6d0f6bcf | 531 | #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000 |
| 18af1c5f | 532 | #endif |
| 6d0f6bcf | 533 | #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ |
| 129ba616 KG |
534 | |
| 535 | #if defined(CONFIG_PCI) | |
| 536 | ||
| 537 | /*PCIE video card used*/ | |
| aca5f018 | 538 | #define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT |
| 129ba616 KG |
539 | |
| 540 | /* video */ | |
| 541 | #define CONFIG_VIDEO | |
| 542 | ||
| 543 | #if defined(CONFIG_VIDEO) | |
| 544 | #define CONFIG_BIOSEMU | |
| 545 | #define CONFIG_CFB_CONSOLE | |
| 546 | #define CONFIG_VIDEO_SW_CURSOR | |
| 547 | #define CONFIG_VGA_AS_SINGLE_DEVICE | |
| 548 | #define CONFIG_ATI_RADEON_FB | |
| 549 | #define CONFIG_VIDEO_LOGO | |
| 550 | /*#define CONFIG_CONSOLE_CURSOR*/ | |
| 6d0f6bcf | 551 | #define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET |
| 129ba616 KG |
552 | #endif |
| 553 | ||
| 554 | #define CONFIG_NET_MULTI | |
| 555 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ | |
| 556 | ||
| 557 | #undef CONFIG_EEPRO100 | |
| 558 | #undef CONFIG_TULIP | |
| 559 | #undef CONFIG_RTL8139 | |
| 16855ec1 | 560 | #define CONFIG_E1000 /* Define e1000 pci Ethernet card */ |
| 129ba616 | 561 | |
| 129ba616 | 562 | #ifndef CONFIG_PCI_PNP |
| 5f91ef6a KG |
563 | #define PCI_ENET0_IOADDR CONFIG_SYS_PCIE3_IO_BUS |
| 564 | #define PCI_ENET0_MEMADDR CONFIG_SYS_PCIE3_IO_BUS | |
| 129ba616 KG |
565 | #define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */ |
| 566 | #endif | |
| 567 | ||
| 568 | #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ | |
| 569 | #define CONFIG_DOS_PARTITION | |
| 570 | #define CONFIG_SCSI_AHCI | |
| 571 | ||
| 572 | #ifdef CONFIG_SCSI_AHCI | |
| 573 | #define CONFIG_SATA_ULI5288 | |
| 6d0f6bcf JCPV |
574 | #define CONFIG_SYS_SCSI_MAX_SCSI_ID 4 |
| 575 | #define CONFIG_SYS_SCSI_MAX_LUN 1 | |
| 576 | #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN) | |
| 577 | #define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE | |
| 129ba616 KG |
578 | #endif /* SCSI */ |
| 579 | ||
| 580 | #endif /* CONFIG_PCI */ | |
| 581 | ||
| 582 | ||
| 583 | #if defined(CONFIG_TSEC_ENET) | |
| 584 | ||
| 585 | #ifndef CONFIG_NET_MULTI | |
| 586 | #define CONFIG_NET_MULTI 1 | |
| 587 | #endif | |
| 588 | ||
| 589 | #define CONFIG_MII 1 /* MII PHY management */ | |
| 590 | #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ | |
| 591 | #define CONFIG_TSEC1 1 | |
| 592 | #define CONFIG_TSEC1_NAME "eTSEC1" | |
| 593 | #define CONFIG_TSEC2 1 | |
| 594 | #define CONFIG_TSEC2_NAME "eTSEC2" | |
| 595 | #define CONFIG_TSEC3 1 | |
| 596 | #define CONFIG_TSEC3_NAME "eTSEC3" | |
| 597 | #define CONFIG_TSEC4 1 | |
| 598 | #define CONFIG_TSEC4_NAME "eTSEC4" | |
| 599 | ||
| 7e183cad LY |
600 | #define CONFIG_PIXIS_SGMII_CMD |
| 601 | #define CONFIG_FSL_SGMII_RISER 1 | |
| 602 | #define SGMII_RISER_PHY_OFFSET 0x1c | |
| 603 | ||
| 604 | #ifdef CONFIG_FSL_SGMII_RISER | |
| 605 | #define CONFIG_SYS_TBIPA_VALUE 0x10 /* avoid conflict with eTSEC4 paddr */ | |
| 606 | #endif | |
| 607 | ||
| 129ba616 KG |
608 | #define TSEC1_PHY_ADDR 0 |
| 609 | #define TSEC2_PHY_ADDR 1 | |
| 610 | #define TSEC3_PHY_ADDR 2 | |
| 611 | #define TSEC4_PHY_ADDR 3 | |
| 612 | ||
| 613 | #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
| 614 | #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
| 615 | #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
| 616 | #define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
| 617 | ||
| 618 | #define TSEC1_PHYIDX 0 | |
| 619 | #define TSEC2_PHYIDX 0 | |
| 620 | #define TSEC3_PHYIDX 0 | |
| 621 | #define TSEC4_PHYIDX 0 | |
| 622 | ||
| 623 | #define CONFIG_ETHPRIME "eTSEC1" | |
| 624 | ||
| 625 | #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ | |
| 626 | #endif /* CONFIG_TSEC_ENET */ | |
| 627 | ||
| 628 | /* | |
| 629 | * Environment | |
| 630 | */ | |
| cb14e93b KG |
631 | |
| 632 | #if defined(CONFIG_SYS_RAMBOOT) | |
| 633 | #if defined(CONFIG_RAMBOOT_NAND) | |
| 634 | #define CONFIG_ENV_IS_IN_NAND 1 | |
| 635 | #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE | |
| 636 | #define CONFIG_ENV_OFFSET ((512 * 1024)\ | |
| 637 | + CONFIG_SYS_NAND_BLOCK_SIZE) | |
| 638 | #endif | |
| 639 | ||
| 129ba616 | 640 | #else |
| cb14e93b KG |
641 | #define CONFIG_ENV_IS_IN_FLASH 1 |
| 642 | #if CONFIG_SYS_MONITOR_BASE > 0xfff80000 | |
| 643 | #define CONFIG_ENV_ADDR 0xfff80000 | |
| 644 | #else | |
| 645 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) | |
| 646 | #endif | |
| 647 | #define CONFIG_ENV_SIZE 0x2000 | |
| 648 | #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ | |
| 129ba616 | 649 | #endif |
| 129ba616 KG |
650 | |
| 651 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
| 6d0f6bcf | 652 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
| 129ba616 KG |
653 | |
| 654 | /* | |
| 655 | * Command line configuration. | |
| 656 | */ | |
| 657 | #include <config_cmd_default.h> | |
| 658 | ||
| 67f94476 | 659 | #define CONFIG_CMD_ERRATA |
| 129ba616 KG |
660 | #define CONFIG_CMD_IRQ |
| 661 | #define CONFIG_CMD_PING | |
| 662 | #define CONFIG_CMD_I2C | |
| 663 | #define CONFIG_CMD_MII | |
| 664 | #define CONFIG_CMD_ELF | |
| 1c9aa76b | 665 | #define CONFIG_CMD_SETEXPR |
| 199e262e | 666 | #define CONFIG_CMD_REGINFO |
| 129ba616 KG |
667 | |
| 668 | #if defined(CONFIG_PCI) | |
| 669 | #define CONFIG_CMD_PCI | |
| 129ba616 KG |
670 | #define CONFIG_CMD_NET |
| 671 | #define CONFIG_CMD_SCSI | |
| 672 | #define CONFIG_CMD_EXT2 | |
| 673 | #endif | |
| 674 | ||
| 863a3eac ZC |
675 | /* |
| 676 | * USB | |
| 677 | */ | |
| 678 | #define CONFIG_USB_EHCI | |
| 679 | ||
| 680 | #ifdef CONFIG_USB_EHCI | |
| 681 | #define CONFIG_CMD_USB | |
| 682 | #define CONFIG_USB_EHCI_PCI | |
| 683 | #define CONFIG_EHCI_HCD_INIT_AFTER_RESET | |
| 684 | #define CONFIG_USB_STORAGE | |
| 685 | #define CONFIG_PCI_EHCI_DEVICE 0 | |
| 686 | #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 2 | |
| 687 | #endif | |
| 688 | ||
| 129ba616 KG |
689 | #undef CONFIG_WATCHDOG /* watchdog disabled */ |
| 690 | ||
| 691 | /* | |
| 692 | * Miscellaneous configurable options | |
| 693 | */ | |
| 6d0f6bcf | 694 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
| 5be58f5f KP |
695 | #define CONFIG_CMDLINE_EDITING /* Command-line editing */ |
| 696 | #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ | |
| 6d0f6bcf JCPV |
697 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ |
| 698 | #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ | |
| 129ba616 | 699 | #if defined(CONFIG_CMD_KGDB) |
| 6d0f6bcf | 700 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
| 129ba616 | 701 | #else |
| 6d0f6bcf | 702 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
| 129ba616 | 703 | #endif |
| 6d0f6bcf JCPV |
704 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
| 705 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
| 706 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
| 707 | #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ | |
| 129ba616 KG |
708 | |
| 709 | /* | |
| 710 | * For booting Linux, the board info and command line data | |
| a832ac41 | 711 | * have to be in the first 64 MB of memory, since this is |
| 129ba616 KG |
712 | * the maximum mapped by the Linux kernel during initialization. |
| 713 | */ | |
| a832ac41 KG |
714 | #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ |
| 715 | #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ | |
| 129ba616 | 716 | |
| 129ba616 KG |
717 | #if defined(CONFIG_CMD_KGDB) |
| 718 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ | |
| 719 | #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ | |
| 720 | #endif | |
| 721 | ||
| 722 | /* | |
| 723 | * Environment Configuration | |
| 724 | */ | |
| 725 | ||
| 726 | /* The mac addresses for all ethernet interface */ | |
| 727 | #if defined(CONFIG_TSEC_ENET) | |
| 728 | #define CONFIG_HAS_ETH0 | |
| 729 | #define CONFIG_ETHADDR 00:E0:0C:02:00:FD | |
| 730 | #define CONFIG_HAS_ETH1 | |
| 731 | #define CONFIG_ETH1ADDR 00:E0:0C:02:01:FD | |
| 732 | #define CONFIG_HAS_ETH2 | |
| 733 | #define CONFIG_ETH2ADDR 00:E0:0C:02:02:FD | |
| 734 | #define CONFIG_HAS_ETH3 | |
| 735 | #define CONFIG_ETH3ADDR 00:E0:0C:02:03:FD | |
| 736 | #endif | |
| 737 | ||
| 738 | #define CONFIG_IPADDR 192.168.1.254 | |
| 739 | ||
| 740 | #define CONFIG_HOSTNAME unknown | |
| 741 | #define CONFIG_ROOTPATH /opt/nfsroot | |
| 742 | #define CONFIG_BOOTFILE uImage | |
| 743 | #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ | |
| 744 | ||
| 745 | #define CONFIG_SERVERIP 192.168.1.1 | |
| 746 | #define CONFIG_GATEWAYIP 192.168.1.1 | |
| 747 | #define CONFIG_NETMASK 255.255.255.0 | |
| 748 | ||
| 749 | /* default location for tftp and bootm */ | |
| 750 | #define CONFIG_LOADADDR 1000000 | |
| 751 | ||
| 752 | #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ | |
| 753 | #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ | |
| 754 | ||
| 755 | #define CONFIG_BAUDRATE 115200 | |
| 756 | ||
| 757 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
| 5103d7aa | 758 | "hwconfig=fsl_ddr:ctlr_intlv=bank,ecc=off\0" \ |
| 129ba616 KG |
759 | "netdev=eth0\0" \ |
| 760 | "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ | |
| 761 | "tftpflash=tftpboot $loadaddr $uboot; " \ | |
| 14d0a02a WD |
762 | "protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ |
| 763 | "erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ | |
| 764 | "cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; " \ | |
| 765 | "protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ | |
| 766 | "cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0" \ | |
| 129ba616 KG |
767 | "consoledev=ttyS0\0" \ |
| 768 | "ramdiskaddr=2000000\0" \ | |
| 769 | "ramdiskfile=8572ds/ramdisk.uboot\0" \ | |
| 770 | "fdtaddr=c00000\0" \ | |
| 771 | "fdtfile=8572ds/mpc8572ds.dtb\0" \ | |
| 772 | "bdev=sda3\0" | |
| 773 | ||
| 774 | #define CONFIG_HDBOOT \ | |
| 775 | "setenv bootargs root=/dev/$bdev rw " \ | |
| 776 | "console=$consoledev,$baudrate $othbootargs;" \ | |
| 777 | "tftp $loadaddr $bootfile;" \ | |
| 778 | "tftp $fdtaddr $fdtfile;" \ | |
| 779 | "bootm $loadaddr - $fdtaddr" | |
| 780 | ||
| 781 | #define CONFIG_NFSBOOTCOMMAND \ | |
| 782 | "setenv bootargs root=/dev/nfs rw " \ | |
| 783 | "nfsroot=$serverip:$rootpath " \ | |
| 784 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ | |
| 785 | "console=$consoledev,$baudrate $othbootargs;" \ | |
| 786 | "tftp $loadaddr $bootfile;" \ | |
| 787 | "tftp $fdtaddr $fdtfile;" \ | |
| 788 | "bootm $loadaddr - $fdtaddr" | |
| 789 | ||
| 790 | #define CONFIG_RAMBOOTCOMMAND \ | |
| 791 | "setenv bootargs root=/dev/ram rw " \ | |
| 792 | "console=$consoledev,$baudrate $othbootargs;" \ | |
| 793 | "tftp $ramdiskaddr $ramdiskfile;" \ | |
| 794 | "tftp $loadaddr $bootfile;" \ | |
| 795 | "tftp $fdtaddr $fdtfile;" \ | |
| 796 | "bootm $loadaddr $ramdiskaddr $fdtaddr" | |
| 797 | ||
| 798 | #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT | |
| 799 | ||
| 800 | #endif /* __CONFIG_H */ |