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56523f12 1/*
69445d6c 2 * (C) Copyright 2003-2014
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3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
45a212c4 5 * (C) Copyright 2004-2006
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6 * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
7 *
3765b3e7 8 * SPDX-License-Identifier: GPL-2.0+
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9 */
10
11#ifndef __CONFIG_H
12#define __CONFIG_H
13
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14/*
15 * High Level Configuration Options
16 * (easy to change)
17 */
18
b2a6dfe4 19#define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */
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20#define CONFIG_TQM5200 1 /* ... on TQM5200 module */
21#undef CONFIG_TQM5200_REV100 /* define for revision 100 modules */
56523f12 22
2ae18241
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23/*
24 * Valid values for CONFIG_SYS_TEXT_BASE are:
25 * 0xFC000000 boot low (standard configuration with room for
26 * max 64 MByte Flash ROM)
27 * 0xFFF00000 boot high (for a backup copy of U-Boot)
28 * 0x00100000 boot from RAM (for testing only)
29 */
30#ifndef CONFIG_SYS_TEXT_BASE
31#define CONFIG_SYS_TEXT_BASE 0xFC000000
32#endif
33
5196a7a0 34/* On a Cameron or on a FO300 board or ... */
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35#if !defined(CONFIG_CAM5200) && !defined(CONFIG_CHARON) \
36 && !defined(CONFIG_FO300)
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37#define CONFIG_STK52XX 1 /* ... on a STK52XX board */
38#endif
39
6d0f6bcf 40#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
56523f12 41
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42#define CONFIG_HIGH_BATS 1 /* High BATs supported */
43
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44/*
45 * Serial console configuration
46 */
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47#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
48#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
6d0f6bcf 49#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
bef92e21 50#define CONFIG_BOOTCOUNT_LIMIT 1
56523f12 51
6d3bc9b8 52#ifdef CONFIG_FO300
6d0f6bcf 53#define CONFIG_SYS_DEVICE_NULLDEV 1 /* enable null device */
ddde6b7c 54#define CONFIG_USB_BIN_FIXUP 1 /* for a buggy USB device */
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55#if 0
56#define FO300_SILENT_CONSOLE_WHEN_S1_CLOSED 1 /* silent console on PSC1 when S1 */
57 /* switch is closed */
58#endif
59
60#undef FO300_SILENT_CONSOLE_WHEN_S1_CLOSED /* silent console on PSC1 when S1 */
61 /* switch is open */
5196a7a0 62#endif /* CONFIG_FO300 */
6d3bc9b8 63
98e69567 64#if defined(CONFIG_CHARON) || defined(CONFIG_STK52XX)
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65#define CONFIG_PS2KBD /* AT-PS/2 Keyboard */
66#define CONFIG_PS2MULT /* .. on PS/2 Multiplexer */
67#define CONFIG_PS2SERIAL 6 /* .. on PSC6 */
6d0f6bcf 68#define CONFIG_PS2MULT_DELAY (CONFIG_SYS_HZ/2) /* Initial delay */
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69#define CONFIG_BOARD_EARLY_INIT_R
70#endif /* CONFIG_STK52XX */
56523f12 71
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72/*
73 * PCI Mapping:
74 * 0x40000000 - 0x4fffffff - PCI Memory
75 * 0x50000000 - 0x50ffffff - PCI IO Space
76 */
98e69567 77#if defined(CONFIG_CHARON) || defined(CONFIG_STK52XX)
31a64923 78/* #define CONFIG_PCI_SCAN_SHOW 1 */
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79
80#define CONFIG_PCI_MEM_BUS 0x40000000
81#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
82#define CONFIG_PCI_MEM_SIZE 0x10000000
83
84#define CONFIG_PCI_IO_BUS 0x50000000
85#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
86#define CONFIG_PCI_IO_SIZE 0x01000000
87
cd65a3dc 88#define CONFIG_EEPRO100 1
6d0f6bcf 89#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
56523f12 90#define CONFIG_NS8382X 1
83e40ba7 91#endif /* CONFIG_STK52XX */
56523f12 92
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93/*
94 * Video console
95 */
5078cce8 96#ifndef CONFIG_TQM5200S /* No graphics controller on TQM5200S */
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97#define CONFIG_VIDEO_SM501
98#define CONFIG_VIDEO_SM501_32BPP
8f0b7cbe 99#define CONFIG_VIDEO_LOGO
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100
101#ifndef CONFIG_FO300
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102#else
103#define CONFIG_VIDEO_BMP_LOGO
104#endif
105
8f0b7cbe 106#define CONFIG_SPLASH_SCREEN
6d3bc9b8 107#endif /* #ifndef CONFIG_TQM5200S */
56523f12 108
56523f12 109/* Partitions */
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110
111/* USB */
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112#if defined(CONFIG_CHARON) || defined(CONFIG_FO300) || \
113 defined(CONFIG_STK52XX)
7b59b3c7 114#define CONFIG_USB_OHCI_NEW
6d0f6bcf 115#define CONFIG_SYS_OHCI_BE_CONTROLLER
53e336e9 116
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117#undef CONFIG_SYS_USB_OHCI_BOARD_INIT
118#define CONFIG_SYS_USB_OHCI_CPU_INIT
119#define CONFIG_SYS_USB_OHCI_REGS_BASE MPC5XXX_USB
120#define CONFIG_SYS_USB_OHCI_SLOT_NAME "mpc5200"
121#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
53e336e9 122
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123#endif
124
135ae006 125#ifndef CONFIG_CAM5200
56523f12 126/* POST support */
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127#define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \
128 CONFIG_SYS_POST_CPU | \
129 CONFIG_SYS_POST_I2C)
5078cce8 130#endif
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131
132#ifdef CONFIG_POST
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133/* preserve space for the post_word at end of on-chip SRAM */
134#define MPC5XXX_SRAM_POST_SIZE MPC5XXX_SRAM_SIZE-4
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135#endif
136
56523f12 137/*
a1aa0bb5 138 * BOOTP options
56523f12 139 */
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140#define CONFIG_BOOTP_BOOTFILESIZE
141#define CONFIG_BOOTP_BOOTPATH
142#define CONFIG_BOOTP_GATEWAY
143#define CONFIG_BOOTP_HOSTNAME
144
56523f12 145/*
2694690e 146 * Command line configuration.
56523f12 147 */
2694690e 148#define CONFIG_CMD_DATE
2694690e 149#define CONFIG_CMD_EEPROM
2694690e 150#define CONFIG_CMD_JFFS2
2694690e 151#define CONFIG_CMD_REGINFO
2694690e
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152#define CONFIG_CMD_BSP
153
154#ifdef CONFIG_VIDEO
155 #define CONFIG_CMD_BMP
156#endif
157
158#ifdef CONFIG_PCI
2b2a587d 159#define CONFIG_CMD_PCI
f33fca22 160#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
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161#endif
162
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163#if defined(CONFIG_CHARON) || defined(CONFIG_FO300) || \
164 defined(CONFIG_MINIFAP) || defined(CONFIG_STK52XX)
2694690e 165 #define CONFIG_CMD_IDE
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166#endif
167
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168#if defined(CONFIG_CHARON) || defined(CONFIG_FO300) || \
169 defined(CONFIG_STK52XX)
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170 #define CONFIG_CFG_USB
171 #define CONFIG_CFG_FAT
172#endif
173
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174#ifdef CONFIG_POST
175 #define CONFIG_CMD_DIAG
176#endif
177
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178#define CONFIG_TIMESTAMP /* display image timestamps */
179
14d0a02a 180#if (CONFIG_SYS_TEXT_BASE != 0xFFF00000)
6d0f6bcf 181# define CONFIG_SYS_LOWBOOT 1 /* Boot low */
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182#endif
183
184/*
185 * Autobooting
186 */
56523f12 187
81050926 188#define CONFIG_PREBOOT "echo;" \
4c4aca81 189 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
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190 "echo"
191
192#undef CONFIG_BOOTARGS
193
6d0f6bcf 194#if defined(CONFIG_TQM5200_B) && !defined(CONFIG_SYS_LOWBOOT)
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195# define ENV_UPDT \
196 "update=protect off FFF00000 +${filesize};" \
197 "erase FFF00000 +${filesize};" \
5078cce8 198 "cp.b 200000 FFF00000 ${filesize};" \
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199 "protect on FFF00000 +${filesize}\0"
200#else /* default lowboot configuration */
6d3bc9b8 201# define ENV_UPDT \
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202 "update=protect off FC000000 +${filesize};" \
203 "erase FC000000 +${filesize};" \
6d3bc9b8 204 "cp.b 200000 FC000000 ${filesize};" \
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205 "protect on FC000000 +${filesize}\0"
206#endif
5078cce8 207
e1f601b5 208#if defined(CONFIG_TQM5200)
6abaee42 209#define CUSTOM_ENV_SETTINGS \
e1f601b5 210 "hostname=tqm5200\0" \
6abaee42 211 "bootfile=/tftpboot/tqm5200/uImage\0" \
8f8416fa 212 "fdt_file=/tftpboot/tqm5200/tqm5200.dtb\0" \
6abaee42 213 "u-boot=/tftpboot/tqm5200/u-boot.bin\0"
e1f601b5 214#elif defined(CONFIG_CAM5200)
1636d1c8 215#define CUSTOM_ENV_SETTINGS \
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216 "bootfile=cam5200/uImage\0" \
217 "u-boot=cam5200/u-boot.bin\0" \
74de7aef 218 "setup=tftp 200000 cam5200/setup.img; source 200000\0"
6abaee42
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219#endif
220
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221#if defined(CONFIG_TQM5200_B)
222#define ENV_FLASH_LAYOUT \
223 "fdt_addr=FC100000\0" \
224 "kernel_addr=FC140000\0" \
225 "ramdisk_addr=FC600000\0"
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226#elif defined(CONFIG_CHARON)
227#define ENV_FLASH_LAYOUT \
228 "fdt_addr=FDFC0000\0" \
229 "kernel_addr=FC0A0000\0" \
230 "ramdisk_addr=FC200000\0"
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231#else /* !CONFIG_TQM5200_B */
232#define ENV_FLASH_LAYOUT \
233 "fdt_addr=FC0A0000\0" \
234 "kernel_addr=FC0C0000\0" \
235 "ramdisk_addr=FC300000\0"
236#endif
237
81050926 238#define CONFIG_EXTRA_ENV_SETTINGS \
56523f12 239 "netdev=eth0\0" \
e1f601b5 240 "console=ttyPSC0\0" \
a5cc5555 241 ENV_FLASH_LAYOUT \
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242 "kernel_addr_r=400000\0" \
243 "fdt_addr_r=600000\0" \
89c02e2c 244 "rootpath=/opt/eldk/ppc_6xx\0" \
56523f12 245 "ramargs=setenv bootargs root=/dev/ram rw\0" \
56523f12 246 "nfsargs=setenv bootargs root=/dev/nfs rw " \
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247 "nfsroot=${serverip}:${rootpath}\0" \
248 "addip=setenv bootargs ${bootargs} " \
249 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
250 ":${hostname}:${netdev}:off panic=1\0" \
5078cce8 251 "addcons=setenv bootargs ${bootargs} " \
8f8416fa 252 "console=${console},${baudrate}\0" \
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253 "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
254 "flash_self_old=sete console ttyS0; " \
255 "run ramargs addip addcons addmtd; " \
fe126d8b 256 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
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257 "flash_self=run ramargs addip addcons;" \
258 "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
259 "flash_nfs_old=sete console ttyS0; run nfsargs addip addcons;" \
fe126d8b 260 "bootm ${kernel_addr}\0" \
e1f601b5 261 "flash_nfs=run nfsargs addip addcons;" \
8f8416fa 262 "bootm ${kernel_addr} - ${fdt_addr}\0" \
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263 "net_nfs_old=tftp ${kernel_addr_r} ${bootfile};" \
264 "sete console ttyS0; run nfsargs addip addcons;bootm\0" \
265 "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \
266 "tftp ${fdt_addr_r} ${fdt_file}; " \
98e69567 267 "run nfsargs addip addcons addmtd; " \
e1f601b5 268 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
6abaee42 269 CUSTOM_ENV_SETTINGS \
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270 "load=tftp 200000 ${u-boot}\0" \
271 ENV_UPDT \
7e6bf358 272 ""
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273
274#define CONFIG_BOOTCOMMAND "run net_nfs"
275
276/*
277 * IPB Bus clocking configuration.
278 */
6d0f6bcf 279#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
56523f12 280
6d0f6bcf 281#if defined(CONFIG_SYS_IPBCLK_EQUALS_XLBCLK) && !defined(CONFIG_CAM5200)
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282/*
283 * PCI Bus clocking configuration
284 *
285 * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if
6d0f6bcf 286 * CONFIG_SYS_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock of
c99512d6 287 * 66 MHz yet hasn't been tested with a IPB Bus Clock of 66 MHz.
56523f12 288 */
6d0f6bcf 289#define CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2 /* define for 66MHz speed */
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290#endif
291
292/*
293 * I2C configuration
294 */
295#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
8f0b7cbe 296#ifdef CONFIG_TQM5200_REV100
6d0f6bcf 297#define CONFIG_SYS_I2C_MODULE 1 /* Select I2C module #1 for rev. 100 board */
56523f12 298#else
6d0f6bcf 299#define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #2 for all other revs */
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300#endif
301
302/*
303 * I2C clock frequency
304 *
305 * Please notice, that the resulting clock frequency could differ from the
306 * configured value. This is because the I2C clock is derived from system
a187559e 307 * clock over a frequency divider with only a few divider values. U-Boot
6d0f6bcf 308 * calculates the best approximation for CONFIG_SYS_I2C_SPEED. However the calculated
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309 * approximation allways lies below the configured value, never above.
310 */
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311#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */
312#define CONFIG_SYS_I2C_SLAVE 0x7F
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313
314/*
315 * EEPROM configuration for onboard EEPROM M24C32 (M24C64 should work
316 * also). For other EEPROMs configuration should be verified. On Mini-FAP the
317 * EEPROM (24C64) is on the same I2C address (but on other I2C bus), so the
318 * same configuration could be used.
319 */
6d0f6bcf
JCPV
320#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */
321#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
322#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* =32 Bytes per write */
323#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20
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324
325/*
326 * HW-Monitor configuration on Mini-FAP
327 */
328#if defined (CONFIG_MINIFAP)
6d0f6bcf 329#define CONFIG_SYS_I2C_HWMON_ADDR 0x2C
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330#endif
331
332/* List of I2C addresses to be verified by POST */
56523f12 333#if defined (CONFIG_MINIFAP)
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334#undef CONFIG_SYS_POST_I2C_ADDRS
335#define CONFIG_SYS_POST_I2C_ADDRS {CONFIG_SYS_I2C_EEPROM_ADDR, \
336 CONFIG_SYS_I2C_HWMON_ADDR, \
337 CONFIG_SYS_I2C_SLAVE}
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338#endif
339
340/*
341 * Flash configuration
342 */
6d0f6bcf 343#define CONFIG_SYS_FLASH_BASE 0xFC000000
56523f12 344
d9384de2 345#if defined(CONFIG_CAM5200) && defined(CONFIG_CAM5200_NIOSFLASH)
6d0f6bcf 346#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max num of flash banks
7299712c 347 (= chip selects) */
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348#define CONFIG_SYS_FLASH_WORD_SIZE unsigned int /* main flash device with */
349#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
350#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
351
352#define CONFIG_SYS_FLASH_ADDR0 0x555
353#define CONFIG_SYS_FLASH_ADDR1 0x2AA
354#define CONFIG_SYS_FLASH_2ND_16BIT_DEV 1 /* NIOS flash is a 16bit device */
355#define CONFIG_SYS_MAX_FLASH_SECT 128
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356#else
357/* use CFI flash driver */
6d0f6bcf 358#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
00b1883a 359#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
085ecde1 360#define CONFIG_FLASH_CFI_MTD /* with MTD support */
6d0f6bcf
JCPV
361#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_BOOTCS_START }
362#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks
d9384de2 363 (= chip selects) */
6d0f6bcf 364#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */
d9384de2 365#endif
7299712c 366
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367#define CONFIG_SYS_FLASH_EMPTY_INFO
368#define CONFIG_SYS_FLASH_SIZE 0x04000000 /* 64 MByte */
369#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
56523f12 370
135ae006 371#if defined (CONFIG_CAM5200)
6d0f6bcf 372# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00040000)
5078cce8 373#elif defined(CONFIG_TQM5200_B)
6d0f6bcf 374# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00080000)
45a212c4 375#else
6d0f6bcf 376# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00060000)
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377#endif
378
d534f5cc 379/* Dynamic MTD partition support */
68d7d651 380#define CONFIG_CMD_MTDPARTS
942556a9 381#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
259bff7c 382#define MTDIDS_DEFAULT "nor0=fc000000.flash"
5078cce8 383
5624d66a 384#if defined(CONFIG_STK52XX)
5078cce8 385# if defined(CONFIG_TQM5200_B)
6d0f6bcf 386# if defined(CONFIG_SYS_LOWBOOT)
259bff7c 387# define MTDPARTS_DEFAULT "mtdparts=fc000000.flash:1m(firmware)," \
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388 "256k(dtb)," \
389 "2304k(kernel)," \
390 "2560k(small-fs)," \
45a212c4 391 "2m(initrd)," \
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392 "8m(misc)," \
393 "16m(big-fs)"
394# else /* highboot */
259bff7c 395# define MTDPARTS_DEFAULT "mtdparts=fc000000.flash:2560k(kernel),"\
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396 "3584k(small-fs)," \
397 "2m(initrd)," \
398 "8m(misc)," \
399 "15m(big-fs)," \
400 "1m(firmware)"
6d0f6bcf 401# endif /* CONFIG_SYS_LOWBOOT */
5078cce8 402# else /* !CONFIG_TQM5200_B */
259bff7c 403# define MTDPARTS_DEFAULT "mtdparts=fc000000.flash:640k(firmware),"\
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404 "128k(dtb)," \
405 "2304k(kernel)," \
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406 "2m(initrd)," \
407 "4m(small-fs)," \
5078cce8 408 "8m(misc)," \
e1f601b5 409 "15m(big-fs)"
5078cce8 410# endif /* CONFIG_TQM5200_B */
135ae006 411#elif defined (CONFIG_CAM5200)
259bff7c 412# define MTDPARTS_DEFAULT "mtdparts=fc000000.flash:768k(firmware),"\
5078cce8 413 "1792k(kernel)," \
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414 "5632k(rootfs)," \
415 "24m(home)"
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416#elif defined (CONFIG_CHARON)
417# define MTDPARTS_DEFAULT "mtdparts=fc000000.flash:640k(firmware),"\
418 "1408k(kernel)," \
419 "2m(initrd)," \
420 "4m(small-fs)," \
421 "24320k(big-fs)," \
422 "256k(dts)"
6d3bc9b8 423#elif defined (CONFIG_FO300)
259bff7c 424# define MTDPARTS_DEFAULT "mtdparts=fc000000.flash:640k(firmware),"\
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425 "1408k(kernel)," \
426 "2m(initrd)," \
427 "4m(small-fs)," \
428 "8m(misc)," \
429 "16m(big-fs)"
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430#else
431# error "Unknown Carrier Board"
432#endif /* CONFIG_STK52XX */
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433
434/*
435 * Environment settings
436 */
5a1aceb0 437#define CONFIG_ENV_IS_IN_FLASH 1
0e8d1586 438#define CONFIG_ENV_SIZE 0x4000 /* 16 k - keep small for fast booting */
78d620eb 439#if defined(CONFIG_TQM5200_B) || defined (CONFIG_CAM5200)
0e8d1586 440#define CONFIG_ENV_SECT_SIZE 0x40000
45a212c4 441#else
0e8d1586 442#define CONFIG_ENV_SECT_SIZE 0x20000
5078cce8 443#endif /* CONFIG_TQM5200_B */
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444#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
445#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
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446
447/*
448 * Memory map
449 */
6d0f6bcf
JCPV
450#define CONFIG_SYS_MBAR 0xF0000000
451#define CONFIG_SYS_SDRAM_BASE 0x00000000
452#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
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453
454/* Use ON-Chip SRAM until RAM will be available */
6d0f6bcf 455#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
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456#ifdef CONFIG_POST
457/* preserve space for the post_word at end of on-chip SRAM */
553f0982 458#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_POST_SIZE
56523f12 459#else
553f0982 460#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE
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461#endif
462
25ddd1fb 463#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
6d0f6bcf 464#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
56523f12 465
14d0a02a 466#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
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467#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
468# define CONFIG_SYS_RAMBOOT 1
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469#endif
470
135ae006 471#if defined (CONFIG_CAM5200)
6d0f6bcf 472# define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
5078cce8 473#elif defined(CONFIG_TQM5200_B)
6d0f6bcf 474# define CONFIG_SYS_MONITOR_LEN (512 << 10) /* Reserve 512 kB for Monitor */
45a212c4 475#else
6d0f6bcf 476# define CONFIG_SYS_MONITOR_LEN (384 << 10) /* Reserve 384 kB for Monitor */
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477#endif
478
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479#define CONFIG_SYS_MALLOC_LEN (1024 << 10) /* Reserve 1024 kB for malloc() */
480#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
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481
482/*
483 * Ethernet configuration
484 */
485#define CONFIG_MPC5xxx_FEC 1
86321fc1 486#define CONFIG_MPC5xxx_FEC_MII100
56523f12 487/*
86321fc1 488 * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb
56523f12 489 */
86321fc1 490/* #define CONFIG_MPC5xxx_FEC_MII10 */
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491#define CONFIG_PHY_ADDR 0x00
492
493/*
494 * GPIO configuration
495 *
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496 * use CS1: Bit 0 (mask: 0x80000000):
497 * 1 -> Pin gpio_wkup_6 as second SDRAM chip select (mem_cs1).
56523f12 498 * use ALT CAN position: Bits 2-3 (mask: 0x30000000):
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499 * 00 -> No Alternatives, CAN1/2 on PSC2 according to PSC2 setting.
500 * SPI on PSC3 according to PSC3 setting. Use for CAM5200.
501 * 01 -> CAN1 on I2C1, CAN2 on Tmr0/1.
502 * Use for REV200 STK52XX boards and FO300 boards. Do not use
503 * with REV100 modules (because, there I2C1 is used as I2C bus).
504 * use ATA: Bits 6-7 (mask 0x03000000):
505 * 00 -> No ATA chip selects, csb_4/5 used as normal chip selects.
506 * Use for CAM5200 board.
507 * 01 -> ATA cs0/1 on csb_4/5. Use for the remaining boards.
508 * use PSC6: Bits 9-11 (mask 0x00700000):
509 * 000 -> use PSC6_0 to PSC6_3 as GPIO, PSC6 could not be used as
510 * UART, CODEC or IrDA.
511 * GPIO on PSC6_3 is used in post_hotkeys_pressed() to
512 * enable extended POST tests.
513 * Use for MINI-FAP and TQM5200_IB boards.
514 * 101 -> use PSC6 as UART. Pins PSC6_0 to PSC6_3 are used.
515 * Extended POST test is not available.
516 * Use for STK52xx, FO300 and CAM5200 boards.
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517 * WARNING: When the extended POST is enabled, these bits will
518 * be overridden by this code as GPIOs!
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519 * use PCI_DIS: Bit 16 (mask 0x00008000):
520 * 1 -> disable PCI controller (on CAM5200 board).
521 * use USB: Bits 18-19 (mask 0x00003000):
522 * 10 -> two UARTs (on FO300 and CAM5200).
523 * use PSC3: Bits 20-23 (mask: 0x00000f00):
524 * 0000 -> All PSC3 pins are GPIOs.
525 * 1100 -> UART/SPI (on FO300 board).
526 * 0100 -> UART (on CAM5200 board).
527 * use PSC2: Bits 25:27 (mask: 0x00000030):
528 * 000 -> All PSC2 pins are GPIOs.
529 * 100 -> UART (on CAM5200 board).
530 * 001 -> CAN1/2 on PSC2 pins.
95c44ec4 531 * Use for REV100 STK52xx boards
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532 * 01x -> Use AC97 (on FO300 board).
533 * use PSC1: Bits 29-31 (mask: 0x00000007):
534 * 100 -> UART (on all boards).
56523f12 535 */
98e69567 536#if !defined(CONFIG_SYS_GPS_PORT_CONFIG)
56523f12 537#if defined (CONFIG_MINIFAP)
6d0f6bcf 538# define CONFIG_SYS_GPS_PORT_CONFIG 0x91000004
7e6bf358 539#elif defined (CONFIG_STK52XX)
83e40ba7 540# if defined (CONFIG_STK52XX_REV100)
6d0f6bcf 541# define CONFIG_SYS_GPS_PORT_CONFIG 0x81500014
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542# else /* STK52xx REV200 and above */
543# if defined (CONFIG_TQM5200_REV100)
544# error TQM5200 REV100 not supported on STK52XX REV200 or above
545# else/* TQM5200 REV200 and above */
6d0f6bcf 546# define CONFIG_SYS_GPS_PORT_CONFIG 0x91500404
83e40ba7 547# endif
8f0b7cbe 548# endif
6d3bc9b8 549#elif defined (CONFIG_FO300)
6d0f6bcf 550# define CONFIG_SYS_GPS_PORT_CONFIG 0x91502c24
7299712c 551#elif defined (CONFIG_CAM5200)
6d0f6bcf 552# define CONFIG_SYS_GPS_PORT_CONFIG 0x8050A444
83e40ba7 553#else /* TMQ5200 Inbetriebnahme-Board */
6d0f6bcf 554# define CONFIG_SYS_GPS_PORT_CONFIG 0x81000004
56523f12 555#endif
98e69567 556#endif
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557
558/*
559 * RTC configuration
560 */
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561#if defined (CONFIG_STK52XX) && !defined (CONFIG_STK52XX_REV100)
562# define CONFIG_RTC_M41T11 1
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563# define CONFIG_SYS_I2C_RTC_ADDR 0x68
564# define CONFIG_SYS_M41T11_BASE_YEAR 1900 /* because Linux uses the same base
edd0b509 565 year */
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566#else
567# define CONFIG_RTC_MPC5200 1 /* use internal MPC5200 RTC */
568#endif
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569
570/*
571 * Miscellaneous configurable options
572 */
6d0f6bcf 573#define CONFIG_SYS_LONGHELP /* undef to save memory */
5078cce8 574
2751a95a 575#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
5078cce8 576
6d0f6bcf 577#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
2694690e 578#if defined(CONFIG_CMD_KGDB)
6d0f6bcf 579#define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
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580#endif
581
582#if defined(CONFIG_CMD_KGDB)
6d0f6bcf 583#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
56523f12 584#else
6d0f6bcf 585#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
56523f12 586#endif
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587#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
588#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
589#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
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590
591/* Enable an alternate, more extensive memory test */
6d0f6bcf 592#define CONFIG_SYS_ALT_MEMTEST
56523f12 593
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594#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
595#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
56523f12 596
6d0f6bcf 597#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
56523f12 598
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599/*
600 * Various low-level settings
601 */
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602#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
603#define CONFIG_SYS_HID0_FINAL HID0_ICE
56523f12 604
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605#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
606#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
607#ifdef CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2
608#define CONFIG_SYS_BOOTCS_CFG 0x0008DF30 /* for pci_clk = 66 MHz */
56523f12 609#else
6d0f6bcf 610#define CONFIG_SYS_BOOTCS_CFG 0x0004DF30 /* for pci_clk = 33 MHz */
56523f12 611#endif
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612#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
613#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
56523f12 614
7e6bf358 615#define CONFIG_LAST_STAGE_INIT
7e6bf358 616
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617/*
618 * SRAM - Do not map below 2 GB in address space, because this area is used
619 * for SDRAM autosizing.
620 */
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621#define CONFIG_SYS_CS2_START 0xE5000000
622#define CONFIG_SYS_CS2_SIZE 0x100000 /* 1 MByte */
623#define CONFIG_SYS_CS2_CFG 0x0004D930
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624
625/*
626 * Grafic controller - Do not map below 2 GB in address space, because this
627 * area is used for SDRAM autosizing.
628 */
8f0b7cbe 629#define SM501_FB_BASE 0xE0000000
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630#define CONFIG_SYS_CS1_START (SM501_FB_BASE)
631#define CONFIG_SYS_CS1_SIZE 0x4000000 /* 64 MByte */
632#define CONFIG_SYS_CS1_CFG 0x8F48FF70
633#define SM501_MMIO_BASE CONFIG_SYS_CS1_START + 0x03E00000
56523f12 634
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635#define CONFIG_SYS_CS_BURST 0x00000000
636#define CONFIG_SYS_CS_DEADCYCLE 0x33333311 /* 1 dead cycle for flash and SM501 */
56523f12 637
7299712c 638#if defined(CONFIG_CAM5200)
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639#define CONFIG_SYS_CS4_START 0xB0000000
640#define CONFIG_SYS_CS4_SIZE 0x00010000
641#define CONFIG_SYS_CS4_CFG 0x01019C10
7299712c 642
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643#define CONFIG_SYS_CS5_START 0xD0000000
644#define CONFIG_SYS_CS5_SIZE 0x01208000
645#define CONFIG_SYS_CS5_CFG 0x1414BF10
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646#endif
647
6d0f6bcf 648#define CONFIG_SYS_RESET_ADDRESS 0xff000000
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649
650/*-----------------------------------------------------------------------
651 * USB stuff
652 *-----------------------------------------------------------------------
653 */
654#define CONFIG_USB_CLOCK 0x0001BBBB
655#define CONFIG_USB_CONFIG 0x00001000
656
657/*-----------------------------------------------------------------------
658 * IDE/ATA stuff Supports IDE harddisk
659 *-----------------------------------------------------------------------
660 */
661
81050926 662#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
56523f12 663
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664#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
665#undef CONFIG_IDE_LED /* LED for ide not supported */
56523f12 666
81050926 667#define CONFIG_IDE_RESET /* reset for ide supported */
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668#define CONFIG_IDE_PREINIT
669
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670#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
671#define CONFIG_SYS_IDE_MAXDEVICE 2 /* max. 2 drives per IDE bus */
56523f12 672
6d0f6bcf 673#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
56523f12 674
6d0f6bcf 675#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA
56523f12 676
95c44ec4 677/* Offset for data I/O */
6d0f6bcf 678#define CONFIG_SYS_ATA_DATA_OFFSET (0x0060)
56523f12 679
95c44ec4 680/* Offset for normal register accesses */
6d0f6bcf 681#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET)
56523f12 682
95c44ec4 683/* Offset for alternate registers */
6d0f6bcf 684#define CONFIG_SYS_ATA_ALT_OFFSET (0x005C)
56523f12 685
95c44ec4 686/* Interval between registers */
6d0f6bcf 687#define CONFIG_SYS_ATA_STRIDE 4
56523f12 688
33af3e66 689/* Support ATAPI devices */
95c44ec4 690#define CONFIG_ATAPI 1
33af3e66 691
8f8416fa
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692/*-----------------------------------------------------------------------
693 * Open firmware flat tree support
694 *-----------------------------------------------------------------------
695 */
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696#define OF_CPU "PowerPC,5200@0"
697#define OF_SOC "soc5200@f0000000"
698#define OF_TBCLK (bd->bi_busfreq / 4)
699#define OF_STDOUT_PATH "/soc5200@f0000000/serial@2000"
700
56523f12 701#endif /* __CONFIG_H */