]> git.ipfire.org Git - people/ms/u-boot.git/blame - include/configs/TQM5200.h
configs: Migrate CONFIG_USB_STORAGE
[people/ms/u-boot.git] / include / configs / TQM5200.h
CommitLineData
56523f12 1/*
69445d6c 2 * (C) Copyright 2003-2014
56523f12
WD
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
45a212c4 5 * (C) Copyright 2004-2006
56523f12
WD
6 * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
7 *
3765b3e7 8 * SPDX-License-Identifier: GPL-2.0+
56523f12
WD
9 */
10
11#ifndef __CONFIG_H
12#define __CONFIG_H
13
56523f12
WD
14/*
15 * High Level Configuration Options
16 * (easy to change)
17 */
18
b2a6dfe4 19#define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */
5078cce8
WD
20#define CONFIG_TQM5200 1 /* ... on TQM5200 module */
21#undef CONFIG_TQM5200_REV100 /* define for revision 100 modules */
69445d6c 22#define CONFIG_DISPLAY_BOARDINFO
56523f12 23
2ae18241
WD
24/*
25 * Valid values for CONFIG_SYS_TEXT_BASE are:
26 * 0xFC000000 boot low (standard configuration with room for
27 * max 64 MByte Flash ROM)
28 * 0xFFF00000 boot high (for a backup copy of U-Boot)
29 * 0x00100000 boot from RAM (for testing only)
30 */
31#ifndef CONFIG_SYS_TEXT_BASE
32#define CONFIG_SYS_TEXT_BASE 0xFC000000
33#endif
34
5196a7a0 35/* On a Cameron or on a FO300 board or ... */
98e69567
HS
36#if !defined(CONFIG_CAM5200) && !defined(CONFIG_CHARON) \
37 && !defined(CONFIG_FO300)
5078cce8
WD
38#define CONFIG_STK52XX 1 /* ... on a STK52XX board */
39#endif
40
6d0f6bcf 41#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
56523f12 42
31d82672
BB
43#define CONFIG_HIGH_BATS 1 /* High BATs supported */
44
56523f12
WD
45/*
46 * Serial console configuration
47 */
5078cce8
WD
48#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
49#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
6d0f6bcf 50#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
bef92e21 51#define CONFIG_BOOTCOUNT_LIMIT 1
56523f12 52
6d3bc9b8 53#ifdef CONFIG_FO300
6d0f6bcf 54#define CONFIG_SYS_DEVICE_NULLDEV 1 /* enable null device */
6d3bc9b8
MB
55#define CONFIG_SILENT_CONSOLE 1 /* enable silent startup */
56#define CONFIG_BOARD_EARLY_INIT_F 1 /* used to detect S1 switch position */
ddde6b7c 57#define CONFIG_USB_BIN_FIXUP 1 /* for a buggy USB device */
6d3bc9b8
MB
58#if 0
59#define FO300_SILENT_CONSOLE_WHEN_S1_CLOSED 1 /* silent console on PSC1 when S1 */
60 /* switch is closed */
61#endif
62
63#undef FO300_SILENT_CONSOLE_WHEN_S1_CLOSED /* silent console on PSC1 when S1 */
64 /* switch is open */
5196a7a0 65#endif /* CONFIG_FO300 */
6d3bc9b8 66
98e69567 67#if defined(CONFIG_CHARON) || defined(CONFIG_STK52XX)
7e6bf358
WD
68#define CONFIG_PS2KBD /* AT-PS/2 Keyboard */
69#define CONFIG_PS2MULT /* .. on PS/2 Multiplexer */
70#define CONFIG_PS2SERIAL 6 /* .. on PSC6 */
6d0f6bcf 71#define CONFIG_PS2MULT_DELAY (CONFIG_SYS_HZ/2) /* Initial delay */
7e6bf358
WD
72#define CONFIG_BOARD_EARLY_INIT_R
73#endif /* CONFIG_STK52XX */
56523f12 74
56523f12
WD
75/*
76 * PCI Mapping:
77 * 0x40000000 - 0x4fffffff - PCI Memory
78 * 0x50000000 - 0x50ffffff - PCI IO Space
79 */
98e69567 80#if defined(CONFIG_CHARON) || defined(CONFIG_STK52XX)
7e6bf358 81#define CONFIG_PCI 1
56523f12 82#define CONFIG_PCI_PNP 1
31a64923 83/* #define CONFIG_PCI_SCAN_SHOW 1 */
56523f12
WD
84
85#define CONFIG_PCI_MEM_BUS 0x40000000
86#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
87#define CONFIG_PCI_MEM_SIZE 0x10000000
88
89#define CONFIG_PCI_IO_BUS 0x50000000
90#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
91#define CONFIG_PCI_IO_SIZE 0x01000000
92
cd65a3dc 93#define CONFIG_EEPRO100 1
6d0f6bcf 94#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
56523f12 95#define CONFIG_NS8382X 1
83e40ba7 96#endif /* CONFIG_STK52XX */
56523f12 97
8f0b7cbe
WD
98/*
99 * Video console
100 */
5078cce8 101#ifndef CONFIG_TQM5200S /* No graphics controller on TQM5200S */
8f0b7cbe
WD
102#define CONFIG_VIDEO
103#define CONFIG_VIDEO_SM501
104#define CONFIG_VIDEO_SM501_32BPP
105#define CONFIG_CFB_CONSOLE
106#define CONFIG_VIDEO_LOGO
6d3bc9b8
MB
107
108#ifndef CONFIG_FO300
8f0b7cbe 109#define CONFIG_CONSOLE_EXTRA_INFO
6d3bc9b8
MB
110#else
111#define CONFIG_VIDEO_BMP_LOGO
112#endif
113
114#define CONFIG_VGA_AS_SINGLE_DEVICE
8f0b7cbe
WD
115#define CONFIG_VIDEO_SW_CURSOR
116#define CONFIG_SPLASH_SCREEN
6d0f6bcf 117#define CONFIG_SYS_CONSOLE_IS_IN_ENV
6d3bc9b8 118#endif /* #ifndef CONFIG_TQM5200S */
56523f12 119
56523f12 120/* Partitions */
89c02e2c 121#define CONFIG_MAC_PARTITION
56523f12 122#define CONFIG_DOS_PARTITION
8f0b7cbe 123#define CONFIG_ISO_PARTITION
56523f12
WD
124
125/* USB */
98e69567
HS
126#if defined(CONFIG_CHARON) || defined(CONFIG_FO300) || \
127 defined(CONFIG_STK52XX)
7b59b3c7 128#define CONFIG_USB_OHCI_NEW
6d0f6bcf 129#define CONFIG_SYS_OHCI_BE_CONTROLLER
53e336e9 130
6d0f6bcf
JCPV
131#undef CONFIG_SYS_USB_OHCI_BOARD_INIT
132#define CONFIG_SYS_USB_OHCI_CPU_INIT
133#define CONFIG_SYS_USB_OHCI_REGS_BASE MPC5XXX_USB
134#define CONFIG_SYS_USB_OHCI_SLOT_NAME "mpc5200"
135#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
53e336e9 136
56523f12
WD
137#endif
138
135ae006 139#ifndef CONFIG_CAM5200
56523f12 140/* POST support */
6d0f6bcf
JCPV
141#define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \
142 CONFIG_SYS_POST_CPU | \
143 CONFIG_SYS_POST_I2C)
5078cce8 144#endif
56523f12
WD
145
146#ifdef CONFIG_POST
56523f12
WD
147/* preserve space for the post_word at end of on-chip SRAM */
148#define MPC5XXX_SRAM_POST_SIZE MPC5XXX_SRAM_SIZE-4
56523f12
WD
149#endif
150
56523f12 151/*
a1aa0bb5 152 * BOOTP options
56523f12 153 */
a1aa0bb5
JL
154#define CONFIG_BOOTP_BOOTFILESIZE
155#define CONFIG_BOOTP_BOOTPATH
156#define CONFIG_BOOTP_GATEWAY
157#define CONFIG_BOOTP_HOSTNAME
158
56523f12 159/*
2694690e 160 * Command line configuration.
56523f12 161 */
2694690e 162#define CONFIG_CMD_DATE
2694690e 163#define CONFIG_CMD_EEPROM
2694690e 164#define CONFIG_CMD_JFFS2
2694690e 165#define CONFIG_CMD_REGINFO
2694690e
JL
166#define CONFIG_CMD_BSP
167
168#ifdef CONFIG_VIDEO
169 #define CONFIG_CMD_BMP
170#endif
171
172#ifdef CONFIG_PCI
2b2a587d 173#define CONFIG_CMD_PCI
f33fca22 174#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
2694690e
JL
175#endif
176
98e69567
HS
177#if defined(CONFIG_CHARON) || defined(CONFIG_FO300) || \
178 defined(CONFIG_MINIFAP) || defined(CONFIG_STK52XX)
2694690e 179 #define CONFIG_CMD_IDE
2694690e
JL
180#endif
181
98e69567
HS
182#if defined(CONFIG_CHARON) || defined(CONFIG_FO300) || \
183 defined(CONFIG_STK52XX)
2694690e
JL
184 #define CONFIG_CFG_USB
185 #define CONFIG_CFG_FAT
186#endif
187
af075ee9
JL
188#ifdef CONFIG_POST
189 #define CONFIG_CMD_DIAG
190#endif
191
151ab83a
WD
192#define CONFIG_TIMESTAMP /* display image timestamps */
193
14d0a02a 194#if (CONFIG_SYS_TEXT_BASE != 0xFFF00000)
6d0f6bcf 195# define CONFIG_SYS_LOWBOOT 1 /* Boot low */
56523f12
WD
196#endif
197
198/*
199 * Autobooting
200 */
56523f12 201
81050926 202#define CONFIG_PREBOOT "echo;" \
4c4aca81 203 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
56523f12
WD
204 "echo"
205
206#undef CONFIG_BOOTARGS
207
6d0f6bcf 208#if defined(CONFIG_TQM5200_B) && !defined(CONFIG_SYS_LOWBOOT)
78d620eb
WD
209# define ENV_UPDT \
210 "update=protect off FFF00000 +${filesize};" \
211 "erase FFF00000 +${filesize};" \
5078cce8 212 "cp.b 200000 FFF00000 ${filesize};" \
78d620eb
WD
213 "protect on FFF00000 +${filesize}\0"
214#else /* default lowboot configuration */
6d3bc9b8 215# define ENV_UPDT \
78d620eb
WD
216 "update=protect off FC000000 +${filesize};" \
217 "erase FC000000 +${filesize};" \
6d3bc9b8 218 "cp.b 200000 FC000000 ${filesize};" \
78d620eb
WD
219 "protect on FC000000 +${filesize}\0"
220#endif
5078cce8 221
e1f601b5 222#if defined(CONFIG_TQM5200)
6abaee42 223#define CUSTOM_ENV_SETTINGS \
e1f601b5 224 "hostname=tqm5200\0" \
6abaee42 225 "bootfile=/tftpboot/tqm5200/uImage\0" \
8f8416fa 226 "fdt_file=/tftpboot/tqm5200/tqm5200.dtb\0" \
6abaee42 227 "u-boot=/tftpboot/tqm5200/u-boot.bin\0"
e1f601b5 228#elif defined(CONFIG_CAM5200)
1636d1c8 229#define CUSTOM_ENV_SETTINGS \
6abaee42
RT
230 "bootfile=cam5200/uImage\0" \
231 "u-boot=cam5200/u-boot.bin\0" \
74de7aef 232 "setup=tftp 200000 cam5200/setup.img; source 200000\0"
6abaee42
RT
233#endif
234
a5cc5555
MK
235#if defined(CONFIG_TQM5200_B)
236#define ENV_FLASH_LAYOUT \
237 "fdt_addr=FC100000\0" \
238 "kernel_addr=FC140000\0" \
239 "ramdisk_addr=FC600000\0"
5624d66a
HS
240#elif defined(CONFIG_CHARON)
241#define ENV_FLASH_LAYOUT \
242 "fdt_addr=FDFC0000\0" \
243 "kernel_addr=FC0A0000\0" \
244 "ramdisk_addr=FC200000\0"
a5cc5555
MK
245#else /* !CONFIG_TQM5200_B */
246#define ENV_FLASH_LAYOUT \
247 "fdt_addr=FC0A0000\0" \
248 "kernel_addr=FC0C0000\0" \
249 "ramdisk_addr=FC300000\0"
250#endif
251
81050926 252#define CONFIG_EXTRA_ENV_SETTINGS \
56523f12 253 "netdev=eth0\0" \
e1f601b5 254 "console=ttyPSC0\0" \
a5cc5555 255 ENV_FLASH_LAYOUT \
d78791ae
BS
256 "kernel_addr_r=400000\0" \
257 "fdt_addr_r=600000\0" \
89c02e2c 258 "rootpath=/opt/eldk/ppc_6xx\0" \
56523f12 259 "ramargs=setenv bootargs root=/dev/ram rw\0" \
56523f12 260 "nfsargs=setenv bootargs root=/dev/nfs rw " \
fe126d8b
WD
261 "nfsroot=${serverip}:${rootpath}\0" \
262 "addip=setenv bootargs ${bootargs} " \
263 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
264 ":${hostname}:${netdev}:off panic=1\0" \
5078cce8 265 "addcons=setenv bootargs ${bootargs} " \
8f8416fa 266 "console=${console},${baudrate}\0" \
98e69567
HS
267 "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
268 "flash_self_old=sete console ttyS0; " \
269 "run ramargs addip addcons addmtd; " \
fe126d8b 270 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
e1f601b5
BS
271 "flash_self=run ramargs addip addcons;" \
272 "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
273 "flash_nfs_old=sete console ttyS0; run nfsargs addip addcons;" \
fe126d8b 274 "bootm ${kernel_addr}\0" \
e1f601b5 275 "flash_nfs=run nfsargs addip addcons;" \
8f8416fa 276 "bootm ${kernel_addr} - ${fdt_addr}\0" \
e1f601b5
BS
277 "net_nfs_old=tftp ${kernel_addr_r} ${bootfile};" \
278 "sete console ttyS0; run nfsargs addip addcons;bootm\0" \
279 "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \
280 "tftp ${fdt_addr_r} ${fdt_file}; " \
98e69567 281 "run nfsargs addip addcons addmtd; " \
e1f601b5 282 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
6abaee42 283 CUSTOM_ENV_SETTINGS \
5078cce8
WD
284 "load=tftp 200000 ${u-boot}\0" \
285 ENV_UPDT \
7e6bf358 286 ""
56523f12
WD
287
288#define CONFIG_BOOTCOMMAND "run net_nfs"
289
290/*
291 * IPB Bus clocking configuration.
292 */
6d0f6bcf 293#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
56523f12 294
6d0f6bcf 295#if defined(CONFIG_SYS_IPBCLK_EQUALS_XLBCLK) && !defined(CONFIG_CAM5200)
56523f12
WD
296/*
297 * PCI Bus clocking configuration
298 *
299 * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if
6d0f6bcf 300 * CONFIG_SYS_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock of
c99512d6 301 * 66 MHz yet hasn't been tested with a IPB Bus Clock of 66 MHz.
56523f12 302 */
6d0f6bcf 303#define CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2 /* define for 66MHz speed */
56523f12
WD
304#endif
305
306/*
307 * I2C configuration
308 */
309#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
8f0b7cbe 310#ifdef CONFIG_TQM5200_REV100
6d0f6bcf 311#define CONFIG_SYS_I2C_MODULE 1 /* Select I2C module #1 for rev. 100 board */
56523f12 312#else
6d0f6bcf 313#define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #2 for all other revs */
56523f12
WD
314#endif
315
316/*
317 * I2C clock frequency
318 *
319 * Please notice, that the resulting clock frequency could differ from the
320 * configured value. This is because the I2C clock is derived from system
a187559e 321 * clock over a frequency divider with only a few divider values. U-Boot
6d0f6bcf 322 * calculates the best approximation for CONFIG_SYS_I2C_SPEED. However the calculated
56523f12
WD
323 * approximation allways lies below the configured value, never above.
324 */
6d0f6bcf
JCPV
325#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */
326#define CONFIG_SYS_I2C_SLAVE 0x7F
56523f12
WD
327
328/*
329 * EEPROM configuration for onboard EEPROM M24C32 (M24C64 should work
330 * also). For other EEPROMs configuration should be verified. On Mini-FAP the
331 * EEPROM (24C64) is on the same I2C address (but on other I2C bus), so the
332 * same configuration could be used.
333 */
6d0f6bcf
JCPV
334#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */
335#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
336#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* =32 Bytes per write */
337#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20
56523f12
WD
338
339/*
340 * HW-Monitor configuration on Mini-FAP
341 */
342#if defined (CONFIG_MINIFAP)
6d0f6bcf 343#define CONFIG_SYS_I2C_HWMON_ADDR 0x2C
56523f12
WD
344#endif
345
346/* List of I2C addresses to be verified by POST */
56523f12 347#if defined (CONFIG_MINIFAP)
60aaaa07
PT
348#undef CONFIG_SYS_POST_I2C_ADDRS
349#define CONFIG_SYS_POST_I2C_ADDRS {CONFIG_SYS_I2C_EEPROM_ADDR, \
350 CONFIG_SYS_I2C_HWMON_ADDR, \
351 CONFIG_SYS_I2C_SLAVE}
56523f12
WD
352#endif
353
354/*
355 * Flash configuration
356 */
6d0f6bcf 357#define CONFIG_SYS_FLASH_BASE 0xFC000000
56523f12 358
d9384de2 359#if defined(CONFIG_CAM5200) && defined(CONFIG_CAM5200_NIOSFLASH)
6d0f6bcf 360#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max num of flash banks
7299712c 361 (= chip selects) */
6d0f6bcf
JCPV
362#define CONFIG_SYS_FLASH_WORD_SIZE unsigned int /* main flash device with */
363#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
364#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
365
366#define CONFIG_SYS_FLASH_ADDR0 0x555
367#define CONFIG_SYS_FLASH_ADDR1 0x2AA
368#define CONFIG_SYS_FLASH_2ND_16BIT_DEV 1 /* NIOS flash is a 16bit device */
369#define CONFIG_SYS_MAX_FLASH_SECT 128
d9384de2
MB
370#else
371/* use CFI flash driver */
6d0f6bcf 372#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
00b1883a 373#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
085ecde1 374#define CONFIG_FLASH_CFI_MTD /* with MTD support */
6d0f6bcf
JCPV
375#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_BOOTCS_START }
376#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks
d9384de2 377 (= chip selects) */
6d0f6bcf 378#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */
d9384de2 379#endif
7299712c 380
6d0f6bcf
JCPV
381#define CONFIG_SYS_FLASH_EMPTY_INFO
382#define CONFIG_SYS_FLASH_SIZE 0x04000000 /* 64 MByte */
383#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
56523f12 384
135ae006 385#if defined (CONFIG_CAM5200)
6d0f6bcf 386# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00040000)
5078cce8 387#elif defined(CONFIG_TQM5200_B)
6d0f6bcf 388# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00080000)
45a212c4 389#else
6d0f6bcf 390# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00060000)
5078cce8
WD
391#endif
392
d534f5cc 393/* Dynamic MTD partition support */
68d7d651 394#define CONFIG_CMD_MTDPARTS
942556a9 395#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
259bff7c 396#define MTDIDS_DEFAULT "nor0=fc000000.flash"
5078cce8 397
5624d66a 398#if defined(CONFIG_STK52XX)
5078cce8 399# if defined(CONFIG_TQM5200_B)
6d0f6bcf 400# if defined(CONFIG_SYS_LOWBOOT)
259bff7c 401# define MTDPARTS_DEFAULT "mtdparts=fc000000.flash:1m(firmware)," \
a5cc5555
MK
402 "256k(dtb)," \
403 "2304k(kernel)," \
404 "2560k(small-fs)," \
45a212c4 405 "2m(initrd)," \
5078cce8
WD
406 "8m(misc)," \
407 "16m(big-fs)"
408# else /* highboot */
259bff7c 409# define MTDPARTS_DEFAULT "mtdparts=fc000000.flash:2560k(kernel),"\
5078cce8
WD
410 "3584k(small-fs)," \
411 "2m(initrd)," \
412 "8m(misc)," \
413 "15m(big-fs)," \
414 "1m(firmware)"
6d0f6bcf 415# endif /* CONFIG_SYS_LOWBOOT */
5078cce8 416# else /* !CONFIG_TQM5200_B */
259bff7c 417# define MTDPARTS_DEFAULT "mtdparts=fc000000.flash:640k(firmware),"\
e1f601b5
BS
418 "128k(dtb)," \
419 "2304k(kernel)," \
d534f5cc
WD
420 "2m(initrd)," \
421 "4m(small-fs)," \
5078cce8 422 "8m(misc)," \
e1f601b5 423 "15m(big-fs)"
5078cce8 424# endif /* CONFIG_TQM5200_B */
135ae006 425#elif defined (CONFIG_CAM5200)
259bff7c 426# define MTDPARTS_DEFAULT "mtdparts=fc000000.flash:768k(firmware),"\
5078cce8 427 "1792k(kernel)," \
7299712c
MB
428 "5632k(rootfs)," \
429 "24m(home)"
5624d66a
HS
430#elif defined (CONFIG_CHARON)
431# define MTDPARTS_DEFAULT "mtdparts=fc000000.flash:640k(firmware),"\
432 "1408k(kernel)," \
433 "2m(initrd)," \
434 "4m(small-fs)," \
435 "24320k(big-fs)," \
436 "256k(dts)"
6d3bc9b8 437#elif defined (CONFIG_FO300)
259bff7c 438# define MTDPARTS_DEFAULT "mtdparts=fc000000.flash:640k(firmware),"\
6d3bc9b8
MB
439 "1408k(kernel)," \
440 "2m(initrd)," \
441 "4m(small-fs)," \
442 "8m(misc)," \
443 "16m(big-fs)"
5078cce8
WD
444#else
445# error "Unknown Carrier Board"
446#endif /* CONFIG_STK52XX */
56523f12
WD
447
448/*
449 * Environment settings
450 */
5a1aceb0 451#define CONFIG_ENV_IS_IN_FLASH 1
0e8d1586 452#define CONFIG_ENV_SIZE 0x4000 /* 16 k - keep small for fast booting */
78d620eb 453#if defined(CONFIG_TQM5200_B) || defined (CONFIG_CAM5200)
0e8d1586 454#define CONFIG_ENV_SECT_SIZE 0x40000
45a212c4 455#else
0e8d1586 456#define CONFIG_ENV_SECT_SIZE 0x20000
5078cce8 457#endif /* CONFIG_TQM5200_B */
0e8d1586
JCPV
458#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
459#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
56523f12
WD
460
461/*
462 * Memory map
463 */
6d0f6bcf
JCPV
464#define CONFIG_SYS_MBAR 0xF0000000
465#define CONFIG_SYS_SDRAM_BASE 0x00000000
466#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
56523f12
WD
467
468/* Use ON-Chip SRAM until RAM will be available */
6d0f6bcf 469#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
56523f12
WD
470#ifdef CONFIG_POST
471/* preserve space for the post_word at end of on-chip SRAM */
553f0982 472#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_POST_SIZE
56523f12 473#else
553f0982 474#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE
56523f12
WD
475#endif
476
25ddd1fb 477#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
6d0f6bcf 478#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
56523f12 479
14d0a02a 480#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
6d0f6bcf
JCPV
481#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
482# define CONFIG_SYS_RAMBOOT 1
56523f12
WD
483#endif
484
135ae006 485#if defined (CONFIG_CAM5200)
6d0f6bcf 486# define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
5078cce8 487#elif defined(CONFIG_TQM5200_B)
6d0f6bcf 488# define CONFIG_SYS_MONITOR_LEN (512 << 10) /* Reserve 512 kB for Monitor */
45a212c4 489#else
6d0f6bcf 490# define CONFIG_SYS_MONITOR_LEN (384 << 10) /* Reserve 384 kB for Monitor */
5078cce8
WD
491#endif
492
6d0f6bcf
JCPV
493#define CONFIG_SYS_MALLOC_LEN (1024 << 10) /* Reserve 1024 kB for malloc() */
494#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
56523f12
WD
495
496/*
497 * Ethernet configuration
498 */
499#define CONFIG_MPC5xxx_FEC 1
86321fc1 500#define CONFIG_MPC5xxx_FEC_MII100
56523f12 501/*
86321fc1 502 * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb
56523f12 503 */
86321fc1 504/* #define CONFIG_MPC5xxx_FEC_MII10 */
56523f12
WD
505#define CONFIG_PHY_ADDR 0x00
506
507/*
508 * GPIO configuration
509 *
7299712c
MB
510 * use CS1: Bit 0 (mask: 0x80000000):
511 * 1 -> Pin gpio_wkup_6 as second SDRAM chip select (mem_cs1).
56523f12 512 * use ALT CAN position: Bits 2-3 (mask: 0x30000000):
7299712c
MB
513 * 00 -> No Alternatives, CAN1/2 on PSC2 according to PSC2 setting.
514 * SPI on PSC3 according to PSC3 setting. Use for CAM5200.
515 * 01 -> CAN1 on I2C1, CAN2 on Tmr0/1.
516 * Use for REV200 STK52XX boards and FO300 boards. Do not use
517 * with REV100 modules (because, there I2C1 is used as I2C bus).
518 * use ATA: Bits 6-7 (mask 0x03000000):
519 * 00 -> No ATA chip selects, csb_4/5 used as normal chip selects.
520 * Use for CAM5200 board.
521 * 01 -> ATA cs0/1 on csb_4/5. Use for the remaining boards.
522 * use PSC6: Bits 9-11 (mask 0x00700000):
523 * 000 -> use PSC6_0 to PSC6_3 as GPIO, PSC6 could not be used as
524 * UART, CODEC or IrDA.
525 * GPIO on PSC6_3 is used in post_hotkeys_pressed() to
526 * enable extended POST tests.
527 * Use for MINI-FAP and TQM5200_IB boards.
528 * 101 -> use PSC6 as UART. Pins PSC6_0 to PSC6_3 are used.
529 * Extended POST test is not available.
530 * Use for STK52xx, FO300 and CAM5200 boards.
95c44ec4
DZ
531 * WARNING: When the extended POST is enabled, these bits will
532 * be overridden by this code as GPIOs!
7299712c
MB
533 * use PCI_DIS: Bit 16 (mask 0x00008000):
534 * 1 -> disable PCI controller (on CAM5200 board).
535 * use USB: Bits 18-19 (mask 0x00003000):
536 * 10 -> two UARTs (on FO300 and CAM5200).
537 * use PSC3: Bits 20-23 (mask: 0x00000f00):
538 * 0000 -> All PSC3 pins are GPIOs.
539 * 1100 -> UART/SPI (on FO300 board).
540 * 0100 -> UART (on CAM5200 board).
541 * use PSC2: Bits 25:27 (mask: 0x00000030):
542 * 000 -> All PSC2 pins are GPIOs.
543 * 100 -> UART (on CAM5200 board).
544 * 001 -> CAN1/2 on PSC2 pins.
95c44ec4 545 * Use for REV100 STK52xx boards
7299712c
MB
546 * 01x -> Use AC97 (on FO300 board).
547 * use PSC1: Bits 29-31 (mask: 0x00000007):
548 * 100 -> UART (on all boards).
56523f12 549 */
98e69567 550#if !defined(CONFIG_SYS_GPS_PORT_CONFIG)
56523f12 551#if defined (CONFIG_MINIFAP)
6d0f6bcf 552# define CONFIG_SYS_GPS_PORT_CONFIG 0x91000004
7e6bf358 553#elif defined (CONFIG_STK52XX)
83e40ba7 554# if defined (CONFIG_STK52XX_REV100)
6d0f6bcf 555# define CONFIG_SYS_GPS_PORT_CONFIG 0x81500014
83e40ba7
WD
556# else /* STK52xx REV200 and above */
557# if defined (CONFIG_TQM5200_REV100)
558# error TQM5200 REV100 not supported on STK52XX REV200 or above
559# else/* TQM5200 REV200 and above */
6d0f6bcf 560# define CONFIG_SYS_GPS_PORT_CONFIG 0x91500404
83e40ba7 561# endif
8f0b7cbe 562# endif
6d3bc9b8 563#elif defined (CONFIG_FO300)
6d0f6bcf 564# define CONFIG_SYS_GPS_PORT_CONFIG 0x91502c24
7299712c 565#elif defined (CONFIG_CAM5200)
6d0f6bcf 566# define CONFIG_SYS_GPS_PORT_CONFIG 0x8050A444
83e40ba7 567#else /* TMQ5200 Inbetriebnahme-Board */
6d0f6bcf 568# define CONFIG_SYS_GPS_PORT_CONFIG 0x81000004
56523f12 569#endif
98e69567 570#endif
56523f12
WD
571
572/*
573 * RTC configuration
574 */
4f562f14
WD
575#if defined (CONFIG_STK52XX) && !defined (CONFIG_STK52XX_REV100)
576# define CONFIG_RTC_M41T11 1
6d0f6bcf
JCPV
577# define CONFIG_SYS_I2C_RTC_ADDR 0x68
578# define CONFIG_SYS_M41T11_BASE_YEAR 1900 /* because Linux uses the same base
edd0b509 579 year */
4f562f14
WD
580#else
581# define CONFIG_RTC_MPC5200 1 /* use internal MPC5200 RTC */
582#endif
56523f12
WD
583
584/*
585 * Miscellaneous configurable options
586 */
6d0f6bcf 587#define CONFIG_SYS_LONGHELP /* undef to save memory */
5078cce8 588
2751a95a 589#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
5078cce8 590
6d0f6bcf 591#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
2694690e 592#if defined(CONFIG_CMD_KGDB)
6d0f6bcf 593#define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
2694690e
JL
594#endif
595
596#if defined(CONFIG_CMD_KGDB)
6d0f6bcf 597#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
56523f12 598#else
6d0f6bcf 599#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
56523f12 600#endif
6d0f6bcf
JCPV
601#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
602#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
603#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
56523f12
WD
604
605/* Enable an alternate, more extensive memory test */
6d0f6bcf 606#define CONFIG_SYS_ALT_MEMTEST
56523f12 607
6d0f6bcf
JCPV
608#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
609#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
56523f12 610
6d0f6bcf 611#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
56523f12 612
56523f12
WD
613/*
614 * Various low-level settings
615 */
6d0f6bcf
JCPV
616#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
617#define CONFIG_SYS_HID0_FINAL HID0_ICE
56523f12 618
6d0f6bcf
JCPV
619#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
620#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
621#ifdef CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2
622#define CONFIG_SYS_BOOTCS_CFG 0x0008DF30 /* for pci_clk = 66 MHz */
56523f12 623#else
6d0f6bcf 624#define CONFIG_SYS_BOOTCS_CFG 0x0004DF30 /* for pci_clk = 33 MHz */
56523f12 625#endif
6d0f6bcf
JCPV
626#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
627#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
56523f12 628
7e6bf358 629#define CONFIG_LAST_STAGE_INIT
7e6bf358 630
56523f12
WD
631/*
632 * SRAM - Do not map below 2 GB in address space, because this area is used
633 * for SDRAM autosizing.
634 */
6d0f6bcf
JCPV
635#define CONFIG_SYS_CS2_START 0xE5000000
636#define CONFIG_SYS_CS2_SIZE 0x100000 /* 1 MByte */
637#define CONFIG_SYS_CS2_CFG 0x0004D930
56523f12
WD
638
639/*
640 * Grafic controller - Do not map below 2 GB in address space, because this
641 * area is used for SDRAM autosizing.
642 */
8f0b7cbe 643#define SM501_FB_BASE 0xE0000000
6d0f6bcf
JCPV
644#define CONFIG_SYS_CS1_START (SM501_FB_BASE)
645#define CONFIG_SYS_CS1_SIZE 0x4000000 /* 64 MByte */
646#define CONFIG_SYS_CS1_CFG 0x8F48FF70
647#define SM501_MMIO_BASE CONFIG_SYS_CS1_START + 0x03E00000
56523f12 648
6d0f6bcf
JCPV
649#define CONFIG_SYS_CS_BURST 0x00000000
650#define CONFIG_SYS_CS_DEADCYCLE 0x33333311 /* 1 dead cycle for flash and SM501 */
56523f12 651
7299712c 652#if defined(CONFIG_CAM5200)
6d0f6bcf
JCPV
653#define CONFIG_SYS_CS4_START 0xB0000000
654#define CONFIG_SYS_CS4_SIZE 0x00010000
655#define CONFIG_SYS_CS4_CFG 0x01019C10
7299712c 656
6d0f6bcf
JCPV
657#define CONFIG_SYS_CS5_START 0xD0000000
658#define CONFIG_SYS_CS5_SIZE 0x01208000
659#define CONFIG_SYS_CS5_CFG 0x1414BF10
7299712c
MB
660#endif
661
6d0f6bcf 662#define CONFIG_SYS_RESET_ADDRESS 0xff000000
56523f12
WD
663
664/*-----------------------------------------------------------------------
665 * USB stuff
666 *-----------------------------------------------------------------------
667 */
668#define CONFIG_USB_CLOCK 0x0001BBBB
669#define CONFIG_USB_CONFIG 0x00001000
670
671/*-----------------------------------------------------------------------
672 * IDE/ATA stuff Supports IDE harddisk
673 *-----------------------------------------------------------------------
674 */
675
81050926 676#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
56523f12 677
81050926
WD
678#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
679#undef CONFIG_IDE_LED /* LED for ide not supported */
56523f12 680
81050926 681#define CONFIG_IDE_RESET /* reset for ide supported */
56523f12
WD
682#define CONFIG_IDE_PREINIT
683
6d0f6bcf
JCPV
684#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
685#define CONFIG_SYS_IDE_MAXDEVICE 2 /* max. 2 drives per IDE bus */
56523f12 686
6d0f6bcf 687#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
56523f12 688
6d0f6bcf 689#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA
56523f12 690
95c44ec4 691/* Offset for data I/O */
6d0f6bcf 692#define CONFIG_SYS_ATA_DATA_OFFSET (0x0060)
56523f12 693
95c44ec4 694/* Offset for normal register accesses */
6d0f6bcf 695#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET)
56523f12 696
95c44ec4 697/* Offset for alternate registers */
6d0f6bcf 698#define CONFIG_SYS_ATA_ALT_OFFSET (0x005C)
56523f12 699
95c44ec4 700/* Interval between registers */
6d0f6bcf 701#define CONFIG_SYS_ATA_STRIDE 4
56523f12 702
33af3e66 703/* Support ATAPI devices */
95c44ec4 704#define CONFIG_ATAPI 1
33af3e66 705
8f8416fa
BS
706/*-----------------------------------------------------------------------
707 * Open firmware flat tree support
708 *-----------------------------------------------------------------------
709 */
8f8416fa
BS
710#define OF_CPU "PowerPC,5200@0"
711#define OF_SOC "soc5200@f0000000"
712#define OF_TBCLK (bd->bi_busfreq / 4)
713#define OF_STDOUT_PATH "/soc5200@f0000000/serial@2000"
714
56523f12 715#endif /* __CONFIG_H */