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56523f12 1/*
69445d6c 2 * (C) Copyright 2003-2014
56523f12
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3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
45a212c4 5 * (C) Copyright 2004-2006
56523f12
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6 * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
7 *
3765b3e7 8 * SPDX-License-Identifier: GPL-2.0+
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9 */
10
11#ifndef __CONFIG_H
12#define __CONFIG_H
13
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14/*
15 * High Level Configuration Options
16 * (easy to change)
17 */
18
b2a6dfe4 19#define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */
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20#define CONFIG_TQM5200 1 /* ... on TQM5200 module */
21#undef CONFIG_TQM5200_REV100 /* define for revision 100 modules */
56523f12 22
2ae18241
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23/*
24 * Valid values for CONFIG_SYS_TEXT_BASE are:
25 * 0xFC000000 boot low (standard configuration with room for
26 * max 64 MByte Flash ROM)
27 * 0xFFF00000 boot high (for a backup copy of U-Boot)
28 * 0x00100000 boot from RAM (for testing only)
29 */
30#ifndef CONFIG_SYS_TEXT_BASE
31#define CONFIG_SYS_TEXT_BASE 0xFC000000
32#endif
33
5196a7a0 34/* On a Cameron or on a FO300 board or ... */
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35#if !defined(CONFIG_CAM5200) && !defined(CONFIG_CHARON) \
36 && !defined(CONFIG_FO300)
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37#define CONFIG_STK52XX 1 /* ... on a STK52XX board */
38#endif
39
6d0f6bcf 40#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
56523f12 41
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42#define CONFIG_HIGH_BATS 1 /* High BATs supported */
43
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44/*
45 * Serial console configuration
46 */
5078cce8 47#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
6d0f6bcf 48#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
bef92e21 49#define CONFIG_BOOTCOUNT_LIMIT 1
56523f12 50
6d3bc9b8 51#ifdef CONFIG_FO300
6d0f6bcf 52#define CONFIG_SYS_DEVICE_NULLDEV 1 /* enable null device */
ddde6b7c 53#define CONFIG_USB_BIN_FIXUP 1 /* for a buggy USB device */
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54#if 0
55#define FO300_SILENT_CONSOLE_WHEN_S1_CLOSED 1 /* silent console on PSC1 when S1 */
56 /* switch is closed */
57#endif
58
59#undef FO300_SILENT_CONSOLE_WHEN_S1_CLOSED /* silent console on PSC1 when S1 */
60 /* switch is open */
5196a7a0 61#endif /* CONFIG_FO300 */
6d3bc9b8 62
98e69567 63#if defined(CONFIG_CHARON) || defined(CONFIG_STK52XX)
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64#define CONFIG_PS2KBD /* AT-PS/2 Keyboard */
65#define CONFIG_PS2MULT /* .. on PS/2 Multiplexer */
66#define CONFIG_PS2SERIAL 6 /* .. on PSC6 */
6d0f6bcf 67#define CONFIG_PS2MULT_DELAY (CONFIG_SYS_HZ/2) /* Initial delay */
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68#define CONFIG_BOARD_EARLY_INIT_R
69#endif /* CONFIG_STK52XX */
56523f12 70
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71/*
72 * PCI Mapping:
73 * 0x40000000 - 0x4fffffff - PCI Memory
74 * 0x50000000 - 0x50ffffff - PCI IO Space
75 */
98e69567 76#if defined(CONFIG_CHARON) || defined(CONFIG_STK52XX)
31a64923 77/* #define CONFIG_PCI_SCAN_SHOW 1 */
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78
79#define CONFIG_PCI_MEM_BUS 0x40000000
80#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
81#define CONFIG_PCI_MEM_SIZE 0x10000000
82
83#define CONFIG_PCI_IO_BUS 0x50000000
84#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
85#define CONFIG_PCI_IO_SIZE 0x01000000
86
cd65a3dc 87#define CONFIG_EEPRO100 1
6d0f6bcf 88#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
56523f12 89#define CONFIG_NS8382X 1
83e40ba7 90#endif /* CONFIG_STK52XX */
56523f12 91
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92/*
93 * Video console
94 */
5078cce8 95#ifndef CONFIG_TQM5200S /* No graphics controller on TQM5200S */
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96#define CONFIG_VIDEO_SM501
97#define CONFIG_VIDEO_SM501_32BPP
8f0b7cbe 98#define CONFIG_VIDEO_LOGO
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99
100#ifndef CONFIG_FO300
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101#else
102#define CONFIG_VIDEO_BMP_LOGO
103#endif
104
8f0b7cbe 105#define CONFIG_SPLASH_SCREEN
6d3bc9b8 106#endif /* #ifndef CONFIG_TQM5200S */
56523f12 107
56523f12 108/* Partitions */
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109
110/* USB */
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111#if defined(CONFIG_CHARON) || defined(CONFIG_FO300) || \
112 defined(CONFIG_STK52XX)
7b59b3c7 113#define CONFIG_USB_OHCI_NEW
6d0f6bcf 114#define CONFIG_SYS_OHCI_BE_CONTROLLER
53e336e9 115
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116#undef CONFIG_SYS_USB_OHCI_BOARD_INIT
117#define CONFIG_SYS_USB_OHCI_CPU_INIT
118#define CONFIG_SYS_USB_OHCI_REGS_BASE MPC5XXX_USB
119#define CONFIG_SYS_USB_OHCI_SLOT_NAME "mpc5200"
120#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
53e336e9 121
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122#endif
123
135ae006 124#ifndef CONFIG_CAM5200
56523f12 125/* POST support */
6d0f6bcf 126#define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \
eb5ba3ae 127 CONFIG_SYS_POST_CPU)
5078cce8 128#endif
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129
130#ifdef CONFIG_POST
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131/* preserve space for the post_word at end of on-chip SRAM */
132#define MPC5XXX_SRAM_POST_SIZE MPC5XXX_SRAM_SIZE-4
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133#endif
134
56523f12 135/*
a1aa0bb5 136 * BOOTP options
56523f12 137 */
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138#define CONFIG_BOOTP_BOOTFILESIZE
139#define CONFIG_BOOTP_BOOTPATH
140#define CONFIG_BOOTP_GATEWAY
141#define CONFIG_BOOTP_HOSTNAME
142
56523f12 143/*
2694690e 144 * Command line configuration.
56523f12 145 */
2694690e 146#define CONFIG_CMD_JFFS2
2694690e 147#define CONFIG_CMD_REGINFO
2694690e 148
2694690e 149#ifdef CONFIG_PCI
2b2a587d 150#define CONFIG_CMD_PCI
f33fca22 151#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
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152#endif
153
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154#if defined(CONFIG_CHARON) || defined(CONFIG_FO300) || \
155 defined(CONFIG_MINIFAP) || defined(CONFIG_STK52XX)
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156#endif
157
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158#if defined(CONFIG_CHARON) || defined(CONFIG_FO300) || \
159 defined(CONFIG_STK52XX)
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160 #define CONFIG_CFG_USB
161 #define CONFIG_CFG_FAT
162#endif
163
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164#define CONFIG_TIMESTAMP /* display image timestamps */
165
14d0a02a 166#if (CONFIG_SYS_TEXT_BASE != 0xFFF00000)
6d0f6bcf 167# define CONFIG_SYS_LOWBOOT 1 /* Boot low */
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168#endif
169
170/*
171 * Autobooting
172 */
56523f12 173
81050926 174#define CONFIG_PREBOOT "echo;" \
4c4aca81 175 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
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176 "echo"
177
178#undef CONFIG_BOOTARGS
179
6d0f6bcf 180#if defined(CONFIG_TQM5200_B) && !defined(CONFIG_SYS_LOWBOOT)
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181# define ENV_UPDT \
182 "update=protect off FFF00000 +${filesize};" \
183 "erase FFF00000 +${filesize};" \
5078cce8 184 "cp.b 200000 FFF00000 ${filesize};" \
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185 "protect on FFF00000 +${filesize}\0"
186#else /* default lowboot configuration */
6d3bc9b8 187# define ENV_UPDT \
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188 "update=protect off FC000000 +${filesize};" \
189 "erase FC000000 +${filesize};" \
6d3bc9b8 190 "cp.b 200000 FC000000 ${filesize};" \
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191 "protect on FC000000 +${filesize}\0"
192#endif
5078cce8 193
e1f601b5 194#if defined(CONFIG_TQM5200)
6abaee42 195#define CUSTOM_ENV_SETTINGS \
e1f601b5 196 "hostname=tqm5200\0" \
6abaee42 197 "bootfile=/tftpboot/tqm5200/uImage\0" \
8f8416fa 198 "fdt_file=/tftpboot/tqm5200/tqm5200.dtb\0" \
6abaee42 199 "u-boot=/tftpboot/tqm5200/u-boot.bin\0"
e1f601b5 200#elif defined(CONFIG_CAM5200)
1636d1c8 201#define CUSTOM_ENV_SETTINGS \
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202 "bootfile=cam5200/uImage\0" \
203 "u-boot=cam5200/u-boot.bin\0" \
74de7aef 204 "setup=tftp 200000 cam5200/setup.img; source 200000\0"
6abaee42
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205#endif
206
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207#if defined(CONFIG_TQM5200_B)
208#define ENV_FLASH_LAYOUT \
209 "fdt_addr=FC100000\0" \
210 "kernel_addr=FC140000\0" \
211 "ramdisk_addr=FC600000\0"
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212#elif defined(CONFIG_CHARON)
213#define ENV_FLASH_LAYOUT \
214 "fdt_addr=FDFC0000\0" \
215 "kernel_addr=FC0A0000\0" \
216 "ramdisk_addr=FC200000\0"
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217#else /* !CONFIG_TQM5200_B */
218#define ENV_FLASH_LAYOUT \
219 "fdt_addr=FC0A0000\0" \
220 "kernel_addr=FC0C0000\0" \
221 "ramdisk_addr=FC300000\0"
222#endif
223
81050926 224#define CONFIG_EXTRA_ENV_SETTINGS \
56523f12 225 "netdev=eth0\0" \
e1f601b5 226 "console=ttyPSC0\0" \
a5cc5555 227 ENV_FLASH_LAYOUT \
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228 "kernel_addr_r=400000\0" \
229 "fdt_addr_r=600000\0" \
89c02e2c 230 "rootpath=/opt/eldk/ppc_6xx\0" \
56523f12 231 "ramargs=setenv bootargs root=/dev/ram rw\0" \
56523f12 232 "nfsargs=setenv bootargs root=/dev/nfs rw " \
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233 "nfsroot=${serverip}:${rootpath}\0" \
234 "addip=setenv bootargs ${bootargs} " \
235 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
236 ":${hostname}:${netdev}:off panic=1\0" \
5078cce8 237 "addcons=setenv bootargs ${bootargs} " \
8f8416fa 238 "console=${console},${baudrate}\0" \
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239 "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
240 "flash_self_old=sete console ttyS0; " \
241 "run ramargs addip addcons addmtd; " \
fe126d8b 242 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
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243 "flash_self=run ramargs addip addcons;" \
244 "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
245 "flash_nfs_old=sete console ttyS0; run nfsargs addip addcons;" \
fe126d8b 246 "bootm ${kernel_addr}\0" \
e1f601b5 247 "flash_nfs=run nfsargs addip addcons;" \
8f8416fa 248 "bootm ${kernel_addr} - ${fdt_addr}\0" \
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249 "net_nfs_old=tftp ${kernel_addr_r} ${bootfile};" \
250 "sete console ttyS0; run nfsargs addip addcons;bootm\0" \
251 "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \
252 "tftp ${fdt_addr_r} ${fdt_file}; " \
98e69567 253 "run nfsargs addip addcons addmtd; " \
e1f601b5 254 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
6abaee42 255 CUSTOM_ENV_SETTINGS \
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256 "load=tftp 200000 ${u-boot}\0" \
257 ENV_UPDT \
7e6bf358 258 ""
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259
260#define CONFIG_BOOTCOMMAND "run net_nfs"
261
262/*
263 * IPB Bus clocking configuration.
264 */
6d0f6bcf 265#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
56523f12 266
6d0f6bcf 267#if defined(CONFIG_SYS_IPBCLK_EQUALS_XLBCLK) && !defined(CONFIG_CAM5200)
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268/*
269 * PCI Bus clocking configuration
270 *
271 * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if
6d0f6bcf 272 * CONFIG_SYS_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock of
c99512d6 273 * 66 MHz yet hasn't been tested with a IPB Bus Clock of 66 MHz.
56523f12 274 */
6d0f6bcf 275#define CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2 /* define for 66MHz speed */
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276#endif
277
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278/*
279 * Flash configuration
280 */
6d0f6bcf 281#define CONFIG_SYS_FLASH_BASE 0xFC000000
56523f12 282
d9384de2 283#if defined(CONFIG_CAM5200) && defined(CONFIG_CAM5200_NIOSFLASH)
6d0f6bcf 284#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max num of flash banks
7299712c 285 (= chip selects) */
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286#define CONFIG_SYS_FLASH_WORD_SIZE unsigned int /* main flash device with */
287#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
288#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
289
290#define CONFIG_SYS_FLASH_ADDR0 0x555
291#define CONFIG_SYS_FLASH_ADDR1 0x2AA
292#define CONFIG_SYS_FLASH_2ND_16BIT_DEV 1 /* NIOS flash is a 16bit device */
293#define CONFIG_SYS_MAX_FLASH_SECT 128
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294#else
295/* use CFI flash driver */
6d0f6bcf 296#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
00b1883a 297#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
085ecde1 298#define CONFIG_FLASH_CFI_MTD /* with MTD support */
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JCPV
299#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_BOOTCS_START }
300#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks
d9384de2 301 (= chip selects) */
6d0f6bcf 302#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */
d9384de2 303#endif
7299712c 304
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305#define CONFIG_SYS_FLASH_EMPTY_INFO
306#define CONFIG_SYS_FLASH_SIZE 0x04000000 /* 64 MByte */
307#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
56523f12 308
135ae006 309#if defined (CONFIG_CAM5200)
6d0f6bcf 310# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00040000)
5078cce8 311#elif defined(CONFIG_TQM5200_B)
6d0f6bcf 312# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00080000)
45a212c4 313#else
6d0f6bcf 314# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00060000)
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315#endif
316
d534f5cc 317/* Dynamic MTD partition support */
68d7d651 318#define CONFIG_CMD_MTDPARTS
942556a9 319#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
259bff7c 320#define MTDIDS_DEFAULT "nor0=fc000000.flash"
5078cce8 321
5624d66a 322#if defined(CONFIG_STK52XX)
5078cce8 323# if defined(CONFIG_TQM5200_B)
6d0f6bcf 324# if defined(CONFIG_SYS_LOWBOOT)
259bff7c 325# define MTDPARTS_DEFAULT "mtdparts=fc000000.flash:1m(firmware)," \
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326 "256k(dtb)," \
327 "2304k(kernel)," \
328 "2560k(small-fs)," \
45a212c4 329 "2m(initrd)," \
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330 "8m(misc)," \
331 "16m(big-fs)"
332# else /* highboot */
259bff7c 333# define MTDPARTS_DEFAULT "mtdparts=fc000000.flash:2560k(kernel),"\
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334 "3584k(small-fs)," \
335 "2m(initrd)," \
336 "8m(misc)," \
337 "15m(big-fs)," \
338 "1m(firmware)"
6d0f6bcf 339# endif /* CONFIG_SYS_LOWBOOT */
5078cce8 340# else /* !CONFIG_TQM5200_B */
259bff7c 341# define MTDPARTS_DEFAULT "mtdparts=fc000000.flash:640k(firmware),"\
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342 "128k(dtb)," \
343 "2304k(kernel)," \
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344 "2m(initrd)," \
345 "4m(small-fs)," \
5078cce8 346 "8m(misc)," \
e1f601b5 347 "15m(big-fs)"
5078cce8 348# endif /* CONFIG_TQM5200_B */
135ae006 349#elif defined (CONFIG_CAM5200)
259bff7c 350# define MTDPARTS_DEFAULT "mtdparts=fc000000.flash:768k(firmware),"\
5078cce8 351 "1792k(kernel)," \
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352 "5632k(rootfs)," \
353 "24m(home)"
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354#elif defined (CONFIG_CHARON)
355# define MTDPARTS_DEFAULT "mtdparts=fc000000.flash:640k(firmware),"\
356 "1408k(kernel)," \
357 "2m(initrd)," \
358 "4m(small-fs)," \
359 "24320k(big-fs)," \
360 "256k(dts)"
6d3bc9b8 361#elif defined (CONFIG_FO300)
259bff7c 362# define MTDPARTS_DEFAULT "mtdparts=fc000000.flash:640k(firmware),"\
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363 "1408k(kernel)," \
364 "2m(initrd)," \
365 "4m(small-fs)," \
366 "8m(misc)," \
367 "16m(big-fs)"
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368#else
369# error "Unknown Carrier Board"
370#endif /* CONFIG_STK52XX */
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371
372/*
373 * Environment settings
374 */
5a1aceb0 375#define CONFIG_ENV_IS_IN_FLASH 1
0e8d1586 376#define CONFIG_ENV_SIZE 0x4000 /* 16 k - keep small for fast booting */
78d620eb 377#if defined(CONFIG_TQM5200_B) || defined (CONFIG_CAM5200)
0e8d1586 378#define CONFIG_ENV_SECT_SIZE 0x40000
45a212c4 379#else
0e8d1586 380#define CONFIG_ENV_SECT_SIZE 0x20000
5078cce8 381#endif /* CONFIG_TQM5200_B */
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382#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
383#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
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384
385/*
386 * Memory map
387 */
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388#define CONFIG_SYS_MBAR 0xF0000000
389#define CONFIG_SYS_SDRAM_BASE 0x00000000
390#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
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391
392/* Use ON-Chip SRAM until RAM will be available */
6d0f6bcf 393#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
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394#ifdef CONFIG_POST
395/* preserve space for the post_word at end of on-chip SRAM */
553f0982 396#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_POST_SIZE
56523f12 397#else
553f0982 398#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE
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399#endif
400
25ddd1fb 401#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
6d0f6bcf 402#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
56523f12 403
14d0a02a 404#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
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405#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
406# define CONFIG_SYS_RAMBOOT 1
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407#endif
408
135ae006 409#if defined (CONFIG_CAM5200)
6d0f6bcf 410# define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
5078cce8 411#elif defined(CONFIG_TQM5200_B)
6d0f6bcf 412# define CONFIG_SYS_MONITOR_LEN (512 << 10) /* Reserve 512 kB for Monitor */
45a212c4 413#else
6d0f6bcf 414# define CONFIG_SYS_MONITOR_LEN (384 << 10) /* Reserve 384 kB for Monitor */
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415#endif
416
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JCPV
417#define CONFIG_SYS_MALLOC_LEN (1024 << 10) /* Reserve 1024 kB for malloc() */
418#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
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419
420/*
421 * Ethernet configuration
422 */
423#define CONFIG_MPC5xxx_FEC 1
86321fc1 424#define CONFIG_MPC5xxx_FEC_MII100
56523f12 425/*
86321fc1 426 * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb
56523f12 427 */
86321fc1 428/* #define CONFIG_MPC5xxx_FEC_MII10 */
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429#define CONFIG_PHY_ADDR 0x00
430
431/*
432 * GPIO configuration
433 *
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434 * use CS1: Bit 0 (mask: 0x80000000):
435 * 1 -> Pin gpio_wkup_6 as second SDRAM chip select (mem_cs1).
56523f12 436 * use ALT CAN position: Bits 2-3 (mask: 0x30000000):
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437 * 00 -> No Alternatives, CAN1/2 on PSC2 according to PSC2 setting.
438 * SPI on PSC3 according to PSC3 setting. Use for CAM5200.
439 * 01 -> CAN1 on I2C1, CAN2 on Tmr0/1.
440 * Use for REV200 STK52XX boards and FO300 boards. Do not use
441 * with REV100 modules (because, there I2C1 is used as I2C bus).
442 * use ATA: Bits 6-7 (mask 0x03000000):
443 * 00 -> No ATA chip selects, csb_4/5 used as normal chip selects.
444 * Use for CAM5200 board.
445 * 01 -> ATA cs0/1 on csb_4/5. Use for the remaining boards.
446 * use PSC6: Bits 9-11 (mask 0x00700000):
447 * 000 -> use PSC6_0 to PSC6_3 as GPIO, PSC6 could not be used as
448 * UART, CODEC or IrDA.
449 * GPIO on PSC6_3 is used in post_hotkeys_pressed() to
450 * enable extended POST tests.
451 * Use for MINI-FAP and TQM5200_IB boards.
452 * 101 -> use PSC6 as UART. Pins PSC6_0 to PSC6_3 are used.
453 * Extended POST test is not available.
454 * Use for STK52xx, FO300 and CAM5200 boards.
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455 * WARNING: When the extended POST is enabled, these bits will
456 * be overridden by this code as GPIOs!
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457 * use PCI_DIS: Bit 16 (mask 0x00008000):
458 * 1 -> disable PCI controller (on CAM5200 board).
459 * use USB: Bits 18-19 (mask 0x00003000):
460 * 10 -> two UARTs (on FO300 and CAM5200).
461 * use PSC3: Bits 20-23 (mask: 0x00000f00):
462 * 0000 -> All PSC3 pins are GPIOs.
463 * 1100 -> UART/SPI (on FO300 board).
464 * 0100 -> UART (on CAM5200 board).
465 * use PSC2: Bits 25:27 (mask: 0x00000030):
466 * 000 -> All PSC2 pins are GPIOs.
467 * 100 -> UART (on CAM5200 board).
468 * 001 -> CAN1/2 on PSC2 pins.
95c44ec4 469 * Use for REV100 STK52xx boards
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470 * 01x -> Use AC97 (on FO300 board).
471 * use PSC1: Bits 29-31 (mask: 0x00000007):
472 * 100 -> UART (on all boards).
56523f12 473 */
98e69567 474#if !defined(CONFIG_SYS_GPS_PORT_CONFIG)
56523f12 475#if defined (CONFIG_MINIFAP)
6d0f6bcf 476# define CONFIG_SYS_GPS_PORT_CONFIG 0x91000004
7e6bf358 477#elif defined (CONFIG_STK52XX)
83e40ba7 478# if defined (CONFIG_STK52XX_REV100)
6d0f6bcf 479# define CONFIG_SYS_GPS_PORT_CONFIG 0x81500014
83e40ba7
WD
480# else /* STK52xx REV200 and above */
481# if defined (CONFIG_TQM5200_REV100)
482# error TQM5200 REV100 not supported on STK52XX REV200 or above
483# else/* TQM5200 REV200 and above */
6d0f6bcf 484# define CONFIG_SYS_GPS_PORT_CONFIG 0x91500404
83e40ba7 485# endif
8f0b7cbe 486# endif
6d3bc9b8 487#elif defined (CONFIG_FO300)
6d0f6bcf 488# define CONFIG_SYS_GPS_PORT_CONFIG 0x91502c24
7299712c 489#elif defined (CONFIG_CAM5200)
6d0f6bcf 490# define CONFIG_SYS_GPS_PORT_CONFIG 0x8050A444
83e40ba7 491#else /* TMQ5200 Inbetriebnahme-Board */
6d0f6bcf 492# define CONFIG_SYS_GPS_PORT_CONFIG 0x81000004
56523f12 493#endif
98e69567 494#endif
56523f12 495
56523f12
WD
496/*
497 * Miscellaneous configurable options
498 */
6d0f6bcf 499#define CONFIG_SYS_LONGHELP /* undef to save memory */
5078cce8 500
2751a95a 501#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
5078cce8 502
6d0f6bcf 503#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
2694690e 504#if defined(CONFIG_CMD_KGDB)
6d0f6bcf 505#define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
2694690e
JL
506#endif
507
508#if defined(CONFIG_CMD_KGDB)
6d0f6bcf 509#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
56523f12 510#else
6d0f6bcf 511#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
56523f12 512#endif
6d0f6bcf
JCPV
513#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
514#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
515#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
56523f12
WD
516
517/* Enable an alternate, more extensive memory test */
6d0f6bcf 518#define CONFIG_SYS_ALT_MEMTEST
56523f12 519
6d0f6bcf
JCPV
520#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
521#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
56523f12 522
6d0f6bcf 523#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
56523f12 524
56523f12
WD
525/*
526 * Various low-level settings
527 */
6d0f6bcf
JCPV
528#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
529#define CONFIG_SYS_HID0_FINAL HID0_ICE
56523f12 530
6d0f6bcf
JCPV
531#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
532#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
533#ifdef CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2
534#define CONFIG_SYS_BOOTCS_CFG 0x0008DF30 /* for pci_clk = 66 MHz */
56523f12 535#else
6d0f6bcf 536#define CONFIG_SYS_BOOTCS_CFG 0x0004DF30 /* for pci_clk = 33 MHz */
56523f12 537#endif
6d0f6bcf
JCPV
538#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
539#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
56523f12 540
7e6bf358 541#define CONFIG_LAST_STAGE_INIT
7e6bf358 542
56523f12
WD
543/*
544 * SRAM - Do not map below 2 GB in address space, because this area is used
545 * for SDRAM autosizing.
546 */
6d0f6bcf
JCPV
547#define CONFIG_SYS_CS2_START 0xE5000000
548#define CONFIG_SYS_CS2_SIZE 0x100000 /* 1 MByte */
549#define CONFIG_SYS_CS2_CFG 0x0004D930
56523f12
WD
550
551/*
552 * Grafic controller - Do not map below 2 GB in address space, because this
553 * area is used for SDRAM autosizing.
554 */
8f0b7cbe 555#define SM501_FB_BASE 0xE0000000
6d0f6bcf
JCPV
556#define CONFIG_SYS_CS1_START (SM501_FB_BASE)
557#define CONFIG_SYS_CS1_SIZE 0x4000000 /* 64 MByte */
558#define CONFIG_SYS_CS1_CFG 0x8F48FF70
559#define SM501_MMIO_BASE CONFIG_SYS_CS1_START + 0x03E00000
56523f12 560
6d0f6bcf
JCPV
561#define CONFIG_SYS_CS_BURST 0x00000000
562#define CONFIG_SYS_CS_DEADCYCLE 0x33333311 /* 1 dead cycle for flash and SM501 */
56523f12 563
7299712c 564#if defined(CONFIG_CAM5200)
6d0f6bcf
JCPV
565#define CONFIG_SYS_CS4_START 0xB0000000
566#define CONFIG_SYS_CS4_SIZE 0x00010000
567#define CONFIG_SYS_CS4_CFG 0x01019C10
7299712c 568
6d0f6bcf
JCPV
569#define CONFIG_SYS_CS5_START 0xD0000000
570#define CONFIG_SYS_CS5_SIZE 0x01208000
571#define CONFIG_SYS_CS5_CFG 0x1414BF10
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572#endif
573
6d0f6bcf 574#define CONFIG_SYS_RESET_ADDRESS 0xff000000
56523f12
WD
575
576/*-----------------------------------------------------------------------
577 * USB stuff
578 *-----------------------------------------------------------------------
579 */
580#define CONFIG_USB_CLOCK 0x0001BBBB
581#define CONFIG_USB_CONFIG 0x00001000
582
583/*-----------------------------------------------------------------------
584 * IDE/ATA stuff Supports IDE harddisk
585 *-----------------------------------------------------------------------
586 */
587
81050926 588#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
56523f12 589
81050926
WD
590#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
591#undef CONFIG_IDE_LED /* LED for ide not supported */
56523f12 592
81050926 593#define CONFIG_IDE_RESET /* reset for ide supported */
56523f12
WD
594#define CONFIG_IDE_PREINIT
595
6d0f6bcf
JCPV
596#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
597#define CONFIG_SYS_IDE_MAXDEVICE 2 /* max. 2 drives per IDE bus */
56523f12 598
6d0f6bcf 599#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
56523f12 600
6d0f6bcf 601#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA
56523f12 602
95c44ec4 603/* Offset for data I/O */
6d0f6bcf 604#define CONFIG_SYS_ATA_DATA_OFFSET (0x0060)
56523f12 605
95c44ec4 606/* Offset for normal register accesses */
6d0f6bcf 607#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET)
56523f12 608
95c44ec4 609/* Offset for alternate registers */
6d0f6bcf 610#define CONFIG_SYS_ATA_ALT_OFFSET (0x005C)
56523f12 611
95c44ec4 612/* Interval between registers */
6d0f6bcf 613#define CONFIG_SYS_ATA_STRIDE 4
56523f12 614
33af3e66 615/* Support ATAPI devices */
95c44ec4 616#define CONFIG_ATAPI 1
33af3e66 617
8f8416fa
BS
618/*-----------------------------------------------------------------------
619 * Open firmware flat tree support
620 *-----------------------------------------------------------------------
621 */
8f8416fa
BS
622#define OF_CPU "PowerPC,5200@0"
623#define OF_SOC "soc5200@f0000000"
624#define OF_TBCLK (bd->bi_busfreq / 4)
625#define OF_STDOUT_PATH "/soc5200@f0000000/serial@2000"
626
56523f12 627#endif /* __CONFIG_H */