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56523f12 1/*
69445d6c 2 * (C) Copyright 2003-2014
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3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
45a212c4 5 * (C) Copyright 2004-2006
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6 * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
7 *
3765b3e7 8 * SPDX-License-Identifier: GPL-2.0+
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9 */
10
11#ifndef __CONFIG_H
12#define __CONFIG_H
13
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14/*
15 * High Level Configuration Options
16 * (easy to change)
17 */
18
b2a6dfe4 19#define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */
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20#define CONFIG_TQM5200 1 /* ... on TQM5200 module */
21#undef CONFIG_TQM5200_REV100 /* define for revision 100 modules */
69445d6c 22#define CONFIG_DISPLAY_BOARDINFO
56523f12 23
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24/*
25 * Valid values for CONFIG_SYS_TEXT_BASE are:
26 * 0xFC000000 boot low (standard configuration with room for
27 * max 64 MByte Flash ROM)
28 * 0xFFF00000 boot high (for a backup copy of U-Boot)
29 * 0x00100000 boot from RAM (for testing only)
30 */
31#ifndef CONFIG_SYS_TEXT_BASE
32#define CONFIG_SYS_TEXT_BASE 0xFC000000
33#endif
34
5196a7a0 35/* On a Cameron or on a FO300 board or ... */
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36#if !defined(CONFIG_CAM5200) && !defined(CONFIG_CHARON) \
37 && !defined(CONFIG_FO300)
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38#define CONFIG_STK52XX 1 /* ... on a STK52XX board */
39#endif
40
6d0f6bcf 41#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
56523f12 42
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43#define CONFIG_HIGH_BATS 1 /* High BATs supported */
44
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45/*
46 * Serial console configuration
47 */
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48#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
49#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
6d0f6bcf 50#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
bef92e21 51#define CONFIG_BOOTCOUNT_LIMIT 1
56523f12 52
6d3bc9b8 53#ifdef CONFIG_FO300
6d0f6bcf 54#define CONFIG_SYS_DEVICE_NULLDEV 1 /* enable null device */
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55#define CONFIG_SILENT_CONSOLE 1 /* enable silent startup */
56#define CONFIG_BOARD_EARLY_INIT_F 1 /* used to detect S1 switch position */
ddde6b7c 57#define CONFIG_USB_BIN_FIXUP 1 /* for a buggy USB device */
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58#if 0
59#define FO300_SILENT_CONSOLE_WHEN_S1_CLOSED 1 /* silent console on PSC1 when S1 */
60 /* switch is closed */
61#endif
62
63#undef FO300_SILENT_CONSOLE_WHEN_S1_CLOSED /* silent console on PSC1 when S1 */
64 /* switch is open */
5196a7a0 65#endif /* CONFIG_FO300 */
6d3bc9b8 66
98e69567 67#if defined(CONFIG_CHARON) || defined(CONFIG_STK52XX)
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68#define CONFIG_PS2KBD /* AT-PS/2 Keyboard */
69#define CONFIG_PS2MULT /* .. on PS/2 Multiplexer */
70#define CONFIG_PS2SERIAL 6 /* .. on PSC6 */
6d0f6bcf 71#define CONFIG_PS2MULT_DELAY (CONFIG_SYS_HZ/2) /* Initial delay */
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72#define CONFIG_BOARD_EARLY_INIT_R
73#endif /* CONFIG_STK52XX */
56523f12 74
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75/*
76 * PCI Mapping:
77 * 0x40000000 - 0x4fffffff - PCI Memory
78 * 0x50000000 - 0x50ffffff - PCI IO Space
79 */
98e69567 80#if defined(CONFIG_CHARON) || defined(CONFIG_STK52XX)
7e6bf358 81#define CONFIG_PCI 1
56523f12 82#define CONFIG_PCI_PNP 1
31a64923 83/* #define CONFIG_PCI_SCAN_SHOW 1 */
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84
85#define CONFIG_PCI_MEM_BUS 0x40000000
86#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
87#define CONFIG_PCI_MEM_SIZE 0x10000000
88
89#define CONFIG_PCI_IO_BUS 0x50000000
90#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
91#define CONFIG_PCI_IO_SIZE 0x01000000
92
cd65a3dc 93#define CONFIG_EEPRO100 1
6d0f6bcf 94#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
56523f12 95#define CONFIG_NS8382X 1
83e40ba7 96#endif /* CONFIG_STK52XX */
56523f12 97
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98/*
99 * Video console
100 */
5078cce8 101#ifndef CONFIG_TQM5200S /* No graphics controller on TQM5200S */
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102#define CONFIG_VIDEO
103#define CONFIG_VIDEO_SM501
104#define CONFIG_VIDEO_SM501_32BPP
105#define CONFIG_CFB_CONSOLE
106#define CONFIG_VIDEO_LOGO
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107
108#ifndef CONFIG_FO300
8f0b7cbe 109#define CONFIG_CONSOLE_EXTRA_INFO
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110#else
111#define CONFIG_VIDEO_BMP_LOGO
112#endif
113
114#define CONFIG_VGA_AS_SINGLE_DEVICE
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115#define CONFIG_VIDEO_SW_CURSOR
116#define CONFIG_SPLASH_SCREEN
6d0f6bcf 117#define CONFIG_SYS_CONSOLE_IS_IN_ENV
6d3bc9b8 118#endif /* #ifndef CONFIG_TQM5200S */
56523f12 119
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120
121/* Partitions */
89c02e2c 122#define CONFIG_MAC_PARTITION
56523f12 123#define CONFIG_DOS_PARTITION
8f0b7cbe 124#define CONFIG_ISO_PARTITION
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125
126/* USB */
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127#if defined(CONFIG_CHARON) || defined(CONFIG_FO300) || \
128 defined(CONFIG_STK52XX)
7b59b3c7 129#define CONFIG_USB_OHCI_NEW
6d0f6bcf 130#define CONFIG_SYS_OHCI_BE_CONTROLLER
56523f12 131#define CONFIG_USB_STORAGE
afaac86f 132#define CONFIG_CMD_FAT
53e336e9 133
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134#undef CONFIG_SYS_USB_OHCI_BOARD_INIT
135#define CONFIG_SYS_USB_OHCI_CPU_INIT
136#define CONFIG_SYS_USB_OHCI_REGS_BASE MPC5XXX_USB
137#define CONFIG_SYS_USB_OHCI_SLOT_NAME "mpc5200"
138#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
53e336e9 139
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140#endif
141
135ae006 142#ifndef CONFIG_CAM5200
56523f12 143/* POST support */
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144#define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \
145 CONFIG_SYS_POST_CPU | \
146 CONFIG_SYS_POST_I2C)
5078cce8 147#endif
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148
149#ifdef CONFIG_POST
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150/* preserve space for the post_word at end of on-chip SRAM */
151#define MPC5XXX_SRAM_POST_SIZE MPC5XXX_SRAM_SIZE-4
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152#endif
153
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154
155/*
a1aa0bb5 156 * BOOTP options
56523f12 157 */
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158#define CONFIG_BOOTP_BOOTFILESIZE
159#define CONFIG_BOOTP_BOOTPATH
160#define CONFIG_BOOTP_GATEWAY
161#define CONFIG_BOOTP_HOSTNAME
162
163
56523f12 164/*
2694690e 165 * Command line configuration.
56523f12 166 */
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167#define CONFIG_CMD_ASKENV
168#define CONFIG_CMD_DATE
2694690e 169#define CONFIG_CMD_EEPROM
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170#define CONFIG_CMD_JFFS2
171#define CONFIG_CMD_MII
2694690e 172#define CONFIG_CMD_REGINFO
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173#define CONFIG_CMD_BSP
174
175#ifdef CONFIG_VIDEO
176 #define CONFIG_CMD_BMP
177#endif
178
179#ifdef CONFIG_PCI
2b2a587d 180#define CONFIG_CMD_PCI
f33fca22 181#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
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182#endif
183
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184#if defined(CONFIG_CHARON) || defined(CONFIG_FO300) || \
185 defined(CONFIG_MINIFAP) || defined(CONFIG_STK52XX)
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186 #define CONFIG_CMD_IDE
187 #define CONFIG_CMD_FAT
188 #define CONFIG_CMD_EXT2
189#endif
190
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191#if defined(CONFIG_CHARON) || defined(CONFIG_FO300) || \
192 defined(CONFIG_STK52XX)
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193 #define CONFIG_CFG_USB
194 #define CONFIG_CFG_FAT
195#endif
196
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197#ifdef CONFIG_POST
198 #define CONFIG_CMD_DIAG
199#endif
200
56523f12 201
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202#define CONFIG_TIMESTAMP /* display image timestamps */
203
14d0a02a 204#if (CONFIG_SYS_TEXT_BASE != 0xFFF00000)
6d0f6bcf 205# define CONFIG_SYS_LOWBOOT 1 /* Boot low */
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206#endif
207
208/*
209 * Autobooting
210 */
211#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
212
81050926 213#define CONFIG_PREBOOT "echo;" \
4c4aca81 214 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
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215 "echo"
216
217#undef CONFIG_BOOTARGS
218
6d0f6bcf 219#if defined(CONFIG_TQM5200_B) && !defined(CONFIG_SYS_LOWBOOT)
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220# define ENV_UPDT \
221 "update=protect off FFF00000 +${filesize};" \
222 "erase FFF00000 +${filesize};" \
5078cce8 223 "cp.b 200000 FFF00000 ${filesize};" \
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224 "protect on FFF00000 +${filesize}\0"
225#else /* default lowboot configuration */
6d3bc9b8 226# define ENV_UPDT \
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227 "update=protect off FC000000 +${filesize};" \
228 "erase FC000000 +${filesize};" \
6d3bc9b8 229 "cp.b 200000 FC000000 ${filesize};" \
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230 "protect on FC000000 +${filesize}\0"
231#endif
5078cce8 232
e1f601b5 233#if defined(CONFIG_TQM5200)
6abaee42 234#define CUSTOM_ENV_SETTINGS \
e1f601b5 235 "hostname=tqm5200\0" \
6abaee42 236 "bootfile=/tftpboot/tqm5200/uImage\0" \
8f8416fa 237 "fdt_file=/tftpboot/tqm5200/tqm5200.dtb\0" \
6abaee42 238 "u-boot=/tftpboot/tqm5200/u-boot.bin\0"
e1f601b5 239#elif defined(CONFIG_CAM5200)
1636d1c8 240#define CUSTOM_ENV_SETTINGS \
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241 "bootfile=cam5200/uImage\0" \
242 "u-boot=cam5200/u-boot.bin\0" \
74de7aef 243 "setup=tftp 200000 cam5200/setup.img; source 200000\0"
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244#endif
245
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246#if defined(CONFIG_TQM5200_B)
247#define ENV_FLASH_LAYOUT \
248 "fdt_addr=FC100000\0" \
249 "kernel_addr=FC140000\0" \
250 "ramdisk_addr=FC600000\0"
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251#elif defined(CONFIG_CHARON)
252#define ENV_FLASH_LAYOUT \
253 "fdt_addr=FDFC0000\0" \
254 "kernel_addr=FC0A0000\0" \
255 "ramdisk_addr=FC200000\0"
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256#else /* !CONFIG_TQM5200_B */
257#define ENV_FLASH_LAYOUT \
258 "fdt_addr=FC0A0000\0" \
259 "kernel_addr=FC0C0000\0" \
260 "ramdisk_addr=FC300000\0"
261#endif
262
81050926 263#define CONFIG_EXTRA_ENV_SETTINGS \
56523f12 264 "netdev=eth0\0" \
e1f601b5 265 "console=ttyPSC0\0" \
a5cc5555 266 ENV_FLASH_LAYOUT \
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267 "kernel_addr_r=400000\0" \
268 "fdt_addr_r=600000\0" \
89c02e2c 269 "rootpath=/opt/eldk/ppc_6xx\0" \
56523f12 270 "ramargs=setenv bootargs root=/dev/ram rw\0" \
56523f12 271 "nfsargs=setenv bootargs root=/dev/nfs rw " \
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272 "nfsroot=${serverip}:${rootpath}\0" \
273 "addip=setenv bootargs ${bootargs} " \
274 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
275 ":${hostname}:${netdev}:off panic=1\0" \
5078cce8 276 "addcons=setenv bootargs ${bootargs} " \
8f8416fa 277 "console=${console},${baudrate}\0" \
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278 "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
279 "flash_self_old=sete console ttyS0; " \
280 "run ramargs addip addcons addmtd; " \
fe126d8b 281 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
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282 "flash_self=run ramargs addip addcons;" \
283 "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
284 "flash_nfs_old=sete console ttyS0; run nfsargs addip addcons;" \
fe126d8b 285 "bootm ${kernel_addr}\0" \
e1f601b5 286 "flash_nfs=run nfsargs addip addcons;" \
8f8416fa 287 "bootm ${kernel_addr} - ${fdt_addr}\0" \
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288 "net_nfs_old=tftp ${kernel_addr_r} ${bootfile};" \
289 "sete console ttyS0; run nfsargs addip addcons;bootm\0" \
290 "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \
291 "tftp ${fdt_addr_r} ${fdt_file}; " \
98e69567 292 "run nfsargs addip addcons addmtd; " \
e1f601b5 293 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
6abaee42 294 CUSTOM_ENV_SETTINGS \
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295 "load=tftp 200000 ${u-boot}\0" \
296 ENV_UPDT \
7e6bf358 297 ""
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298
299#define CONFIG_BOOTCOMMAND "run net_nfs"
300
301/*
302 * IPB Bus clocking configuration.
303 */
6d0f6bcf 304#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
56523f12 305
6d0f6bcf 306#if defined(CONFIG_SYS_IPBCLK_EQUALS_XLBCLK) && !defined(CONFIG_CAM5200)
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307/*
308 * PCI Bus clocking configuration
309 *
310 * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if
6d0f6bcf 311 * CONFIG_SYS_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock of
c99512d6 312 * 66 MHz yet hasn't been tested with a IPB Bus Clock of 66 MHz.
56523f12 313 */
6d0f6bcf 314#define CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2 /* define for 66MHz speed */
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315#endif
316
317/*
318 * I2C configuration
319 */
320#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
8f0b7cbe 321#ifdef CONFIG_TQM5200_REV100
6d0f6bcf 322#define CONFIG_SYS_I2C_MODULE 1 /* Select I2C module #1 for rev. 100 board */
56523f12 323#else
6d0f6bcf 324#define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #2 for all other revs */
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325#endif
326
327/*
328 * I2C clock frequency
329 *
330 * Please notice, that the resulting clock frequency could differ from the
331 * configured value. This is because the I2C clock is derived from system
a187559e 332 * clock over a frequency divider with only a few divider values. U-Boot
6d0f6bcf 333 * calculates the best approximation for CONFIG_SYS_I2C_SPEED. However the calculated
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334 * approximation allways lies below the configured value, never above.
335 */
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336#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */
337#define CONFIG_SYS_I2C_SLAVE 0x7F
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338
339/*
340 * EEPROM configuration for onboard EEPROM M24C32 (M24C64 should work
341 * also). For other EEPROMs configuration should be verified. On Mini-FAP the
342 * EEPROM (24C64) is on the same I2C address (but on other I2C bus), so the
343 * same configuration could be used.
344 */
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345#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */
346#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
347#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* =32 Bytes per write */
348#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20
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349
350/*
351 * HW-Monitor configuration on Mini-FAP
352 */
353#if defined (CONFIG_MINIFAP)
6d0f6bcf 354#define CONFIG_SYS_I2C_HWMON_ADDR 0x2C
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355#endif
356
357/* List of I2C addresses to be verified by POST */
56523f12 358#if defined (CONFIG_MINIFAP)
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359#undef CONFIG_SYS_POST_I2C_ADDRS
360#define CONFIG_SYS_POST_I2C_ADDRS {CONFIG_SYS_I2C_EEPROM_ADDR, \
361 CONFIG_SYS_I2C_HWMON_ADDR, \
362 CONFIG_SYS_I2C_SLAVE}
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363#endif
364
365/*
366 * Flash configuration
367 */
6d0f6bcf 368#define CONFIG_SYS_FLASH_BASE 0xFC000000
56523f12 369
d9384de2 370#if defined(CONFIG_CAM5200) && defined(CONFIG_CAM5200_NIOSFLASH)
6d0f6bcf 371#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max num of flash banks
7299712c 372 (= chip selects) */
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373#define CONFIG_SYS_FLASH_WORD_SIZE unsigned int /* main flash device with */
374#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
375#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
376
377#define CONFIG_SYS_FLASH_ADDR0 0x555
378#define CONFIG_SYS_FLASH_ADDR1 0x2AA
379#define CONFIG_SYS_FLASH_2ND_16BIT_DEV 1 /* NIOS flash is a 16bit device */
380#define CONFIG_SYS_MAX_FLASH_SECT 128
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381#else
382/* use CFI flash driver */
6d0f6bcf 383#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
00b1883a 384#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
085ecde1 385#define CONFIG_FLASH_CFI_MTD /* with MTD support */
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386#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_BOOTCS_START }
387#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks
d9384de2 388 (= chip selects) */
6d0f6bcf 389#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */
d9384de2 390#endif
7299712c 391
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392#define CONFIG_SYS_FLASH_EMPTY_INFO
393#define CONFIG_SYS_FLASH_SIZE 0x04000000 /* 64 MByte */
394#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
56523f12 395
135ae006 396#if defined (CONFIG_CAM5200)
6d0f6bcf 397# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00040000)
5078cce8 398#elif defined(CONFIG_TQM5200_B)
6d0f6bcf 399# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00080000)
45a212c4 400#else
6d0f6bcf 401# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00060000)
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402#endif
403
d534f5cc 404/* Dynamic MTD partition support */
68d7d651 405#define CONFIG_CMD_MTDPARTS
942556a9 406#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
259bff7c 407#define MTDIDS_DEFAULT "nor0=fc000000.flash"
5078cce8 408
5624d66a 409#if defined(CONFIG_STK52XX)
5078cce8 410# if defined(CONFIG_TQM5200_B)
6d0f6bcf 411# if defined(CONFIG_SYS_LOWBOOT)
259bff7c 412# define MTDPARTS_DEFAULT "mtdparts=fc000000.flash:1m(firmware)," \
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413 "256k(dtb)," \
414 "2304k(kernel)," \
415 "2560k(small-fs)," \
45a212c4 416 "2m(initrd)," \
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417 "8m(misc)," \
418 "16m(big-fs)"
419# else /* highboot */
259bff7c 420# define MTDPARTS_DEFAULT "mtdparts=fc000000.flash:2560k(kernel),"\
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421 "3584k(small-fs)," \
422 "2m(initrd)," \
423 "8m(misc)," \
424 "15m(big-fs)," \
425 "1m(firmware)"
6d0f6bcf 426# endif /* CONFIG_SYS_LOWBOOT */
5078cce8 427# else /* !CONFIG_TQM5200_B */
259bff7c 428# define MTDPARTS_DEFAULT "mtdparts=fc000000.flash:640k(firmware),"\
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429 "128k(dtb)," \
430 "2304k(kernel)," \
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431 "2m(initrd)," \
432 "4m(small-fs)," \
5078cce8 433 "8m(misc)," \
e1f601b5 434 "15m(big-fs)"
5078cce8 435# endif /* CONFIG_TQM5200_B */
135ae006 436#elif defined (CONFIG_CAM5200)
259bff7c 437# define MTDPARTS_DEFAULT "mtdparts=fc000000.flash:768k(firmware),"\
5078cce8 438 "1792k(kernel)," \
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439 "5632k(rootfs)," \
440 "24m(home)"
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441#elif defined (CONFIG_CHARON)
442# define MTDPARTS_DEFAULT "mtdparts=fc000000.flash:640k(firmware),"\
443 "1408k(kernel)," \
444 "2m(initrd)," \
445 "4m(small-fs)," \
446 "24320k(big-fs)," \
447 "256k(dts)"
6d3bc9b8 448#elif defined (CONFIG_FO300)
259bff7c 449# define MTDPARTS_DEFAULT "mtdparts=fc000000.flash:640k(firmware),"\
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450 "1408k(kernel)," \
451 "2m(initrd)," \
452 "4m(small-fs)," \
453 "8m(misc)," \
454 "16m(big-fs)"
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455#else
456# error "Unknown Carrier Board"
457#endif /* CONFIG_STK52XX */
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458
459/*
460 * Environment settings
461 */
5a1aceb0 462#define CONFIG_ENV_IS_IN_FLASH 1
0e8d1586 463#define CONFIG_ENV_SIZE 0x4000 /* 16 k - keep small for fast booting */
78d620eb 464#if defined(CONFIG_TQM5200_B) || defined (CONFIG_CAM5200)
0e8d1586 465#define CONFIG_ENV_SECT_SIZE 0x40000
45a212c4 466#else
0e8d1586 467#define CONFIG_ENV_SECT_SIZE 0x20000
5078cce8 468#endif /* CONFIG_TQM5200_B */
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469#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
470#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
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471
472/*
473 * Memory map
474 */
6d0f6bcf
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475#define CONFIG_SYS_MBAR 0xF0000000
476#define CONFIG_SYS_SDRAM_BASE 0x00000000
477#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
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478
479/* Use ON-Chip SRAM until RAM will be available */
6d0f6bcf 480#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
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481#ifdef CONFIG_POST
482/* preserve space for the post_word at end of on-chip SRAM */
553f0982 483#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_POST_SIZE
56523f12 484#else
553f0982 485#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE
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486#endif
487
488
25ddd1fb 489#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
6d0f6bcf 490#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
56523f12 491
14d0a02a 492#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
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493#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
494# define CONFIG_SYS_RAMBOOT 1
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495#endif
496
135ae006 497#if defined (CONFIG_CAM5200)
6d0f6bcf 498# define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
5078cce8 499#elif defined(CONFIG_TQM5200_B)
6d0f6bcf 500# define CONFIG_SYS_MONITOR_LEN (512 << 10) /* Reserve 512 kB for Monitor */
45a212c4 501#else
6d0f6bcf 502# define CONFIG_SYS_MONITOR_LEN (384 << 10) /* Reserve 384 kB for Monitor */
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503#endif
504
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505#define CONFIG_SYS_MALLOC_LEN (1024 << 10) /* Reserve 1024 kB for malloc() */
506#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
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507
508/*
509 * Ethernet configuration
510 */
511#define CONFIG_MPC5xxx_FEC 1
86321fc1 512#define CONFIG_MPC5xxx_FEC_MII100
56523f12 513/*
86321fc1 514 * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb
56523f12 515 */
86321fc1 516/* #define CONFIG_MPC5xxx_FEC_MII10 */
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517#define CONFIG_PHY_ADDR 0x00
518
519/*
520 * GPIO configuration
521 *
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522 * use CS1: Bit 0 (mask: 0x80000000):
523 * 1 -> Pin gpio_wkup_6 as second SDRAM chip select (mem_cs1).
56523f12 524 * use ALT CAN position: Bits 2-3 (mask: 0x30000000):
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525 * 00 -> No Alternatives, CAN1/2 on PSC2 according to PSC2 setting.
526 * SPI on PSC3 according to PSC3 setting. Use for CAM5200.
527 * 01 -> CAN1 on I2C1, CAN2 on Tmr0/1.
528 * Use for REV200 STK52XX boards and FO300 boards. Do not use
529 * with REV100 modules (because, there I2C1 is used as I2C bus).
530 * use ATA: Bits 6-7 (mask 0x03000000):
531 * 00 -> No ATA chip selects, csb_4/5 used as normal chip selects.
532 * Use for CAM5200 board.
533 * 01 -> ATA cs0/1 on csb_4/5. Use for the remaining boards.
534 * use PSC6: Bits 9-11 (mask 0x00700000):
535 * 000 -> use PSC6_0 to PSC6_3 as GPIO, PSC6 could not be used as
536 * UART, CODEC or IrDA.
537 * GPIO on PSC6_3 is used in post_hotkeys_pressed() to
538 * enable extended POST tests.
539 * Use for MINI-FAP and TQM5200_IB boards.
540 * 101 -> use PSC6 as UART. Pins PSC6_0 to PSC6_3 are used.
541 * Extended POST test is not available.
542 * Use for STK52xx, FO300 and CAM5200 boards.
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543 * WARNING: When the extended POST is enabled, these bits will
544 * be overridden by this code as GPIOs!
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545 * use PCI_DIS: Bit 16 (mask 0x00008000):
546 * 1 -> disable PCI controller (on CAM5200 board).
547 * use USB: Bits 18-19 (mask 0x00003000):
548 * 10 -> two UARTs (on FO300 and CAM5200).
549 * use PSC3: Bits 20-23 (mask: 0x00000f00):
550 * 0000 -> All PSC3 pins are GPIOs.
551 * 1100 -> UART/SPI (on FO300 board).
552 * 0100 -> UART (on CAM5200 board).
553 * use PSC2: Bits 25:27 (mask: 0x00000030):
554 * 000 -> All PSC2 pins are GPIOs.
555 * 100 -> UART (on CAM5200 board).
556 * 001 -> CAN1/2 on PSC2 pins.
95c44ec4 557 * Use for REV100 STK52xx boards
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558 * 01x -> Use AC97 (on FO300 board).
559 * use PSC1: Bits 29-31 (mask: 0x00000007):
560 * 100 -> UART (on all boards).
56523f12 561 */
98e69567 562#if !defined(CONFIG_SYS_GPS_PORT_CONFIG)
56523f12 563#if defined (CONFIG_MINIFAP)
6d0f6bcf 564# define CONFIG_SYS_GPS_PORT_CONFIG 0x91000004
7e6bf358 565#elif defined (CONFIG_STK52XX)
83e40ba7 566# if defined (CONFIG_STK52XX_REV100)
6d0f6bcf 567# define CONFIG_SYS_GPS_PORT_CONFIG 0x81500014
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568# else /* STK52xx REV200 and above */
569# if defined (CONFIG_TQM5200_REV100)
570# error TQM5200 REV100 not supported on STK52XX REV200 or above
571# else/* TQM5200 REV200 and above */
6d0f6bcf 572# define CONFIG_SYS_GPS_PORT_CONFIG 0x91500404
83e40ba7 573# endif
8f0b7cbe 574# endif
6d3bc9b8 575#elif defined (CONFIG_FO300)
6d0f6bcf 576# define CONFIG_SYS_GPS_PORT_CONFIG 0x91502c24
7299712c 577#elif defined (CONFIG_CAM5200)
6d0f6bcf 578# define CONFIG_SYS_GPS_PORT_CONFIG 0x8050A444
83e40ba7 579#else /* TMQ5200 Inbetriebnahme-Board */
6d0f6bcf 580# define CONFIG_SYS_GPS_PORT_CONFIG 0x81000004
56523f12 581#endif
98e69567 582#endif
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583
584/*
585 * RTC configuration
586 */
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587#if defined (CONFIG_STK52XX) && !defined (CONFIG_STK52XX_REV100)
588# define CONFIG_RTC_M41T11 1
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589# define CONFIG_SYS_I2C_RTC_ADDR 0x68
590# define CONFIG_SYS_M41T11_BASE_YEAR 1900 /* because Linux uses the same base
edd0b509 591 year */
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592#else
593# define CONFIG_RTC_MPC5200 1 /* use internal MPC5200 RTC */
594#endif
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595
596/*
597 * Miscellaneous configurable options
598 */
6d0f6bcf 599#define CONFIG_SYS_LONGHELP /* undef to save memory */
5078cce8 600
2751a95a 601#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
5078cce8 602
6d0f6bcf 603#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
2694690e 604#if defined(CONFIG_CMD_KGDB)
6d0f6bcf 605#define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
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606#endif
607
608#if defined(CONFIG_CMD_KGDB)
6d0f6bcf 609#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
56523f12 610#else
6d0f6bcf 611#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
56523f12 612#endif
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613#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
614#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
615#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
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616
617/* Enable an alternate, more extensive memory test */
6d0f6bcf 618#define CONFIG_SYS_ALT_MEMTEST
56523f12 619
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620#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
621#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
56523f12 622
6d0f6bcf 623#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
56523f12 624
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625/*
626 * Various low-level settings
627 */
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628#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
629#define CONFIG_SYS_HID0_FINAL HID0_ICE
56523f12 630
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631#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
632#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
633#ifdef CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2
634#define CONFIG_SYS_BOOTCS_CFG 0x0008DF30 /* for pci_clk = 66 MHz */
56523f12 635#else
6d0f6bcf 636#define CONFIG_SYS_BOOTCS_CFG 0x0004DF30 /* for pci_clk = 33 MHz */
56523f12 637#endif
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638#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
639#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
56523f12 640
7e6bf358 641#define CONFIG_LAST_STAGE_INIT
7e6bf358 642
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643/*
644 * SRAM - Do not map below 2 GB in address space, because this area is used
645 * for SDRAM autosizing.
646 */
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647#define CONFIG_SYS_CS2_START 0xE5000000
648#define CONFIG_SYS_CS2_SIZE 0x100000 /* 1 MByte */
649#define CONFIG_SYS_CS2_CFG 0x0004D930
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650
651/*
652 * Grafic controller - Do not map below 2 GB in address space, because this
653 * area is used for SDRAM autosizing.
654 */
8f0b7cbe 655#define SM501_FB_BASE 0xE0000000
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656#define CONFIG_SYS_CS1_START (SM501_FB_BASE)
657#define CONFIG_SYS_CS1_SIZE 0x4000000 /* 64 MByte */
658#define CONFIG_SYS_CS1_CFG 0x8F48FF70
659#define SM501_MMIO_BASE CONFIG_SYS_CS1_START + 0x03E00000
56523f12 660
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661#define CONFIG_SYS_CS_BURST 0x00000000
662#define CONFIG_SYS_CS_DEADCYCLE 0x33333311 /* 1 dead cycle for flash and SM501 */
56523f12 663
7299712c 664#if defined(CONFIG_CAM5200)
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665#define CONFIG_SYS_CS4_START 0xB0000000
666#define CONFIG_SYS_CS4_SIZE 0x00010000
667#define CONFIG_SYS_CS4_CFG 0x01019C10
7299712c 668
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669#define CONFIG_SYS_CS5_START 0xD0000000
670#define CONFIG_SYS_CS5_SIZE 0x01208000
671#define CONFIG_SYS_CS5_CFG 0x1414BF10
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672#endif
673
6d0f6bcf 674#define CONFIG_SYS_RESET_ADDRESS 0xff000000
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675
676/*-----------------------------------------------------------------------
677 * USB stuff
678 *-----------------------------------------------------------------------
679 */
680#define CONFIG_USB_CLOCK 0x0001BBBB
681#define CONFIG_USB_CONFIG 0x00001000
682
683/*-----------------------------------------------------------------------
684 * IDE/ATA stuff Supports IDE harddisk
685 *-----------------------------------------------------------------------
686 */
687
81050926 688#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
56523f12 689
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690#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
691#undef CONFIG_IDE_LED /* LED for ide not supported */
56523f12 692
81050926 693#define CONFIG_IDE_RESET /* reset for ide supported */
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694#define CONFIG_IDE_PREINIT
695
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696#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
697#define CONFIG_SYS_IDE_MAXDEVICE 2 /* max. 2 drives per IDE bus */
56523f12 698
6d0f6bcf 699#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
56523f12 700
6d0f6bcf 701#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA
56523f12 702
95c44ec4 703/* Offset for data I/O */
6d0f6bcf 704#define CONFIG_SYS_ATA_DATA_OFFSET (0x0060)
56523f12 705
95c44ec4 706/* Offset for normal register accesses */
6d0f6bcf 707#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET)
56523f12 708
95c44ec4 709/* Offset for alternate registers */
6d0f6bcf 710#define CONFIG_SYS_ATA_ALT_OFFSET (0x005C)
56523f12 711
95c44ec4 712/* Interval between registers */
6d0f6bcf 713#define CONFIG_SYS_ATA_STRIDE 4
56523f12 714
33af3e66 715/* Support ATAPI devices */
95c44ec4 716#define CONFIG_ATAPI 1
33af3e66 717
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718/*-----------------------------------------------------------------------
719 * Open firmware flat tree support
720 *-----------------------------------------------------------------------
721 */
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722#define OF_CPU "PowerPC,5200@0"
723#define OF_SOC "soc5200@f0000000"
724#define OF_TBCLK (bd->bi_busfreq / 4)
725#define OF_STDOUT_PATH "/soc5200@f0000000/serial@2000"
726
56523f12 727#endif /* __CONFIG_H */