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56523f12 1/*
69445d6c 2 * (C) Copyright 2003-2014
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3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
45a212c4 5 * (C) Copyright 2004-2006
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6 * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
7 *
3765b3e7 8 * SPDX-License-Identifier: GPL-2.0+
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9 */
10
11#ifndef __CONFIG_H
12#define __CONFIG_H
13
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14/*
15 * High Level Configuration Options
16 * (easy to change)
17 */
18
b2a6dfe4 19#define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */
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20#define CONFIG_TQM5200 1 /* ... on TQM5200 module */
21#undef CONFIG_TQM5200_REV100 /* define for revision 100 modules */
56523f12 22
2ae18241
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23/*
24 * Valid values for CONFIG_SYS_TEXT_BASE are:
25 * 0xFC000000 boot low (standard configuration with room for
26 * max 64 MByte Flash ROM)
27 * 0xFFF00000 boot high (for a backup copy of U-Boot)
28 * 0x00100000 boot from RAM (for testing only)
29 */
30#ifndef CONFIG_SYS_TEXT_BASE
31#define CONFIG_SYS_TEXT_BASE 0xFC000000
32#endif
33
5196a7a0 34/* On a Cameron or on a FO300 board or ... */
98e69567
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35#if !defined(CONFIG_CAM5200) && !defined(CONFIG_CHARON) \
36 && !defined(CONFIG_FO300)
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37#define CONFIG_STK52XX 1 /* ... on a STK52XX board */
38#endif
39
6d0f6bcf 40#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
56523f12 41
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42#define CONFIG_HIGH_BATS 1 /* High BATs supported */
43
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44/*
45 * Serial console configuration
46 */
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47#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
48#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
6d0f6bcf 49#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
bef92e21 50#define CONFIG_BOOTCOUNT_LIMIT 1
56523f12 51
6d3bc9b8 52#ifdef CONFIG_FO300
6d0f6bcf 53#define CONFIG_SYS_DEVICE_NULLDEV 1 /* enable null device */
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54#define CONFIG_SILENT_CONSOLE 1 /* enable silent startup */
55#define CONFIG_BOARD_EARLY_INIT_F 1 /* used to detect S1 switch position */
ddde6b7c 56#define CONFIG_USB_BIN_FIXUP 1 /* for a buggy USB device */
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57#if 0
58#define FO300_SILENT_CONSOLE_WHEN_S1_CLOSED 1 /* silent console on PSC1 when S1 */
59 /* switch is closed */
60#endif
61
62#undef FO300_SILENT_CONSOLE_WHEN_S1_CLOSED /* silent console on PSC1 when S1 */
63 /* switch is open */
5196a7a0 64#endif /* CONFIG_FO300 */
6d3bc9b8 65
98e69567 66#if defined(CONFIG_CHARON) || defined(CONFIG_STK52XX)
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67#define CONFIG_PS2KBD /* AT-PS/2 Keyboard */
68#define CONFIG_PS2MULT /* .. on PS/2 Multiplexer */
69#define CONFIG_PS2SERIAL 6 /* .. on PSC6 */
6d0f6bcf 70#define CONFIG_PS2MULT_DELAY (CONFIG_SYS_HZ/2) /* Initial delay */
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71#define CONFIG_BOARD_EARLY_INIT_R
72#endif /* CONFIG_STK52XX */
56523f12 73
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74/*
75 * PCI Mapping:
76 * 0x40000000 - 0x4fffffff - PCI Memory
77 * 0x50000000 - 0x50ffffff - PCI IO Space
78 */
98e69567 79#if defined(CONFIG_CHARON) || defined(CONFIG_STK52XX)
7e6bf358 80#define CONFIG_PCI 1
56523f12 81#define CONFIG_PCI_PNP 1
31a64923 82/* #define CONFIG_PCI_SCAN_SHOW 1 */
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83
84#define CONFIG_PCI_MEM_BUS 0x40000000
85#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
86#define CONFIG_PCI_MEM_SIZE 0x10000000
87
88#define CONFIG_PCI_IO_BUS 0x50000000
89#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
90#define CONFIG_PCI_IO_SIZE 0x01000000
91
cd65a3dc 92#define CONFIG_EEPRO100 1
6d0f6bcf 93#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
56523f12 94#define CONFIG_NS8382X 1
83e40ba7 95#endif /* CONFIG_STK52XX */
56523f12 96
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97/*
98 * Video console
99 */
5078cce8 100#ifndef CONFIG_TQM5200S /* No graphics controller on TQM5200S */
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101#define CONFIG_VIDEO
102#define CONFIG_VIDEO_SM501
103#define CONFIG_VIDEO_SM501_32BPP
104#define CONFIG_CFB_CONSOLE
105#define CONFIG_VIDEO_LOGO
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106
107#ifndef CONFIG_FO300
8f0b7cbe 108#define CONFIG_CONSOLE_EXTRA_INFO
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109#else
110#define CONFIG_VIDEO_BMP_LOGO
111#endif
112
113#define CONFIG_VGA_AS_SINGLE_DEVICE
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114#define CONFIG_VIDEO_SW_CURSOR
115#define CONFIG_SPLASH_SCREEN
6d0f6bcf 116#define CONFIG_SYS_CONSOLE_IS_IN_ENV
6d3bc9b8 117#endif /* #ifndef CONFIG_TQM5200S */
56523f12 118
56523f12 119/* Partitions */
89c02e2c 120#define CONFIG_MAC_PARTITION
56523f12 121#define CONFIG_DOS_PARTITION
8f0b7cbe 122#define CONFIG_ISO_PARTITION
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123
124/* USB */
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125#if defined(CONFIG_CHARON) || defined(CONFIG_FO300) || \
126 defined(CONFIG_STK52XX)
7b59b3c7 127#define CONFIG_USB_OHCI_NEW
6d0f6bcf 128#define CONFIG_SYS_OHCI_BE_CONTROLLER
53e336e9 129
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130#undef CONFIG_SYS_USB_OHCI_BOARD_INIT
131#define CONFIG_SYS_USB_OHCI_CPU_INIT
132#define CONFIG_SYS_USB_OHCI_REGS_BASE MPC5XXX_USB
133#define CONFIG_SYS_USB_OHCI_SLOT_NAME "mpc5200"
134#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
53e336e9 135
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136#endif
137
135ae006 138#ifndef CONFIG_CAM5200
56523f12 139/* POST support */
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140#define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \
141 CONFIG_SYS_POST_CPU | \
142 CONFIG_SYS_POST_I2C)
5078cce8 143#endif
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144
145#ifdef CONFIG_POST
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146/* preserve space for the post_word at end of on-chip SRAM */
147#define MPC5XXX_SRAM_POST_SIZE MPC5XXX_SRAM_SIZE-4
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148#endif
149
56523f12 150/*
a1aa0bb5 151 * BOOTP options
56523f12 152 */
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153#define CONFIG_BOOTP_BOOTFILESIZE
154#define CONFIG_BOOTP_BOOTPATH
155#define CONFIG_BOOTP_GATEWAY
156#define CONFIG_BOOTP_HOSTNAME
157
56523f12 158/*
2694690e 159 * Command line configuration.
56523f12 160 */
2694690e 161#define CONFIG_CMD_DATE
2694690e 162#define CONFIG_CMD_EEPROM
2694690e 163#define CONFIG_CMD_JFFS2
2694690e 164#define CONFIG_CMD_REGINFO
2694690e
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165#define CONFIG_CMD_BSP
166
167#ifdef CONFIG_VIDEO
168 #define CONFIG_CMD_BMP
169#endif
170
171#ifdef CONFIG_PCI
2b2a587d 172#define CONFIG_CMD_PCI
f33fca22 173#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
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174#endif
175
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176#if defined(CONFIG_CHARON) || defined(CONFIG_FO300) || \
177 defined(CONFIG_MINIFAP) || defined(CONFIG_STK52XX)
2694690e 178 #define CONFIG_CMD_IDE
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179#endif
180
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181#if defined(CONFIG_CHARON) || defined(CONFIG_FO300) || \
182 defined(CONFIG_STK52XX)
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183 #define CONFIG_CFG_USB
184 #define CONFIG_CFG_FAT
185#endif
186
af075ee9
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187#ifdef CONFIG_POST
188 #define CONFIG_CMD_DIAG
189#endif
190
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191#define CONFIG_TIMESTAMP /* display image timestamps */
192
14d0a02a 193#if (CONFIG_SYS_TEXT_BASE != 0xFFF00000)
6d0f6bcf 194# define CONFIG_SYS_LOWBOOT 1 /* Boot low */
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195#endif
196
197/*
198 * Autobooting
199 */
56523f12 200
81050926 201#define CONFIG_PREBOOT "echo;" \
4c4aca81 202 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
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203 "echo"
204
205#undef CONFIG_BOOTARGS
206
6d0f6bcf 207#if defined(CONFIG_TQM5200_B) && !defined(CONFIG_SYS_LOWBOOT)
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208# define ENV_UPDT \
209 "update=protect off FFF00000 +${filesize};" \
210 "erase FFF00000 +${filesize};" \
5078cce8 211 "cp.b 200000 FFF00000 ${filesize};" \
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212 "protect on FFF00000 +${filesize}\0"
213#else /* default lowboot configuration */
6d3bc9b8 214# define ENV_UPDT \
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215 "update=protect off FC000000 +${filesize};" \
216 "erase FC000000 +${filesize};" \
6d3bc9b8 217 "cp.b 200000 FC000000 ${filesize};" \
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218 "protect on FC000000 +${filesize}\0"
219#endif
5078cce8 220
e1f601b5 221#if defined(CONFIG_TQM5200)
6abaee42 222#define CUSTOM_ENV_SETTINGS \
e1f601b5 223 "hostname=tqm5200\0" \
6abaee42 224 "bootfile=/tftpboot/tqm5200/uImage\0" \
8f8416fa 225 "fdt_file=/tftpboot/tqm5200/tqm5200.dtb\0" \
6abaee42 226 "u-boot=/tftpboot/tqm5200/u-boot.bin\0"
e1f601b5 227#elif defined(CONFIG_CAM5200)
1636d1c8 228#define CUSTOM_ENV_SETTINGS \
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229 "bootfile=cam5200/uImage\0" \
230 "u-boot=cam5200/u-boot.bin\0" \
74de7aef 231 "setup=tftp 200000 cam5200/setup.img; source 200000\0"
6abaee42
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232#endif
233
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234#if defined(CONFIG_TQM5200_B)
235#define ENV_FLASH_LAYOUT \
236 "fdt_addr=FC100000\0" \
237 "kernel_addr=FC140000\0" \
238 "ramdisk_addr=FC600000\0"
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239#elif defined(CONFIG_CHARON)
240#define ENV_FLASH_LAYOUT \
241 "fdt_addr=FDFC0000\0" \
242 "kernel_addr=FC0A0000\0" \
243 "ramdisk_addr=FC200000\0"
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244#else /* !CONFIG_TQM5200_B */
245#define ENV_FLASH_LAYOUT \
246 "fdt_addr=FC0A0000\0" \
247 "kernel_addr=FC0C0000\0" \
248 "ramdisk_addr=FC300000\0"
249#endif
250
81050926 251#define CONFIG_EXTRA_ENV_SETTINGS \
56523f12 252 "netdev=eth0\0" \
e1f601b5 253 "console=ttyPSC0\0" \
a5cc5555 254 ENV_FLASH_LAYOUT \
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255 "kernel_addr_r=400000\0" \
256 "fdt_addr_r=600000\0" \
89c02e2c 257 "rootpath=/opt/eldk/ppc_6xx\0" \
56523f12 258 "ramargs=setenv bootargs root=/dev/ram rw\0" \
56523f12 259 "nfsargs=setenv bootargs root=/dev/nfs rw " \
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260 "nfsroot=${serverip}:${rootpath}\0" \
261 "addip=setenv bootargs ${bootargs} " \
262 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
263 ":${hostname}:${netdev}:off panic=1\0" \
5078cce8 264 "addcons=setenv bootargs ${bootargs} " \
8f8416fa 265 "console=${console},${baudrate}\0" \
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266 "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
267 "flash_self_old=sete console ttyS0; " \
268 "run ramargs addip addcons addmtd; " \
fe126d8b 269 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
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270 "flash_self=run ramargs addip addcons;" \
271 "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
272 "flash_nfs_old=sete console ttyS0; run nfsargs addip addcons;" \
fe126d8b 273 "bootm ${kernel_addr}\0" \
e1f601b5 274 "flash_nfs=run nfsargs addip addcons;" \
8f8416fa 275 "bootm ${kernel_addr} - ${fdt_addr}\0" \
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276 "net_nfs_old=tftp ${kernel_addr_r} ${bootfile};" \
277 "sete console ttyS0; run nfsargs addip addcons;bootm\0" \
278 "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \
279 "tftp ${fdt_addr_r} ${fdt_file}; " \
98e69567 280 "run nfsargs addip addcons addmtd; " \
e1f601b5 281 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
6abaee42 282 CUSTOM_ENV_SETTINGS \
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283 "load=tftp 200000 ${u-boot}\0" \
284 ENV_UPDT \
7e6bf358 285 ""
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286
287#define CONFIG_BOOTCOMMAND "run net_nfs"
288
289/*
290 * IPB Bus clocking configuration.
291 */
6d0f6bcf 292#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
56523f12 293
6d0f6bcf 294#if defined(CONFIG_SYS_IPBCLK_EQUALS_XLBCLK) && !defined(CONFIG_CAM5200)
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295/*
296 * PCI Bus clocking configuration
297 *
298 * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if
6d0f6bcf 299 * CONFIG_SYS_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock of
c99512d6 300 * 66 MHz yet hasn't been tested with a IPB Bus Clock of 66 MHz.
56523f12 301 */
6d0f6bcf 302#define CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2 /* define for 66MHz speed */
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303#endif
304
305/*
306 * I2C configuration
307 */
308#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
8f0b7cbe 309#ifdef CONFIG_TQM5200_REV100
6d0f6bcf 310#define CONFIG_SYS_I2C_MODULE 1 /* Select I2C module #1 for rev. 100 board */
56523f12 311#else
6d0f6bcf 312#define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #2 for all other revs */
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313#endif
314
315/*
316 * I2C clock frequency
317 *
318 * Please notice, that the resulting clock frequency could differ from the
319 * configured value. This is because the I2C clock is derived from system
a187559e 320 * clock over a frequency divider with only a few divider values. U-Boot
6d0f6bcf 321 * calculates the best approximation for CONFIG_SYS_I2C_SPEED. However the calculated
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322 * approximation allways lies below the configured value, never above.
323 */
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324#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */
325#define CONFIG_SYS_I2C_SLAVE 0x7F
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326
327/*
328 * EEPROM configuration for onboard EEPROM M24C32 (M24C64 should work
329 * also). For other EEPROMs configuration should be verified. On Mini-FAP the
330 * EEPROM (24C64) is on the same I2C address (but on other I2C bus), so the
331 * same configuration could be used.
332 */
6d0f6bcf
JCPV
333#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */
334#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
335#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* =32 Bytes per write */
336#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20
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337
338/*
339 * HW-Monitor configuration on Mini-FAP
340 */
341#if defined (CONFIG_MINIFAP)
6d0f6bcf 342#define CONFIG_SYS_I2C_HWMON_ADDR 0x2C
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343#endif
344
345/* List of I2C addresses to be verified by POST */
56523f12 346#if defined (CONFIG_MINIFAP)
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347#undef CONFIG_SYS_POST_I2C_ADDRS
348#define CONFIG_SYS_POST_I2C_ADDRS {CONFIG_SYS_I2C_EEPROM_ADDR, \
349 CONFIG_SYS_I2C_HWMON_ADDR, \
350 CONFIG_SYS_I2C_SLAVE}
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351#endif
352
353/*
354 * Flash configuration
355 */
6d0f6bcf 356#define CONFIG_SYS_FLASH_BASE 0xFC000000
56523f12 357
d9384de2 358#if defined(CONFIG_CAM5200) && defined(CONFIG_CAM5200_NIOSFLASH)
6d0f6bcf 359#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max num of flash banks
7299712c 360 (= chip selects) */
6d0f6bcf
JCPV
361#define CONFIG_SYS_FLASH_WORD_SIZE unsigned int /* main flash device with */
362#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
363#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
364
365#define CONFIG_SYS_FLASH_ADDR0 0x555
366#define CONFIG_SYS_FLASH_ADDR1 0x2AA
367#define CONFIG_SYS_FLASH_2ND_16BIT_DEV 1 /* NIOS flash is a 16bit device */
368#define CONFIG_SYS_MAX_FLASH_SECT 128
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369#else
370/* use CFI flash driver */
6d0f6bcf 371#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
00b1883a 372#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
085ecde1 373#define CONFIG_FLASH_CFI_MTD /* with MTD support */
6d0f6bcf
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374#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_BOOTCS_START }
375#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks
d9384de2 376 (= chip selects) */
6d0f6bcf 377#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */
d9384de2 378#endif
7299712c 379
6d0f6bcf
JCPV
380#define CONFIG_SYS_FLASH_EMPTY_INFO
381#define CONFIG_SYS_FLASH_SIZE 0x04000000 /* 64 MByte */
382#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
56523f12 383
135ae006 384#if defined (CONFIG_CAM5200)
6d0f6bcf 385# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00040000)
5078cce8 386#elif defined(CONFIG_TQM5200_B)
6d0f6bcf 387# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00080000)
45a212c4 388#else
6d0f6bcf 389# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00060000)
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390#endif
391
d534f5cc 392/* Dynamic MTD partition support */
68d7d651 393#define CONFIG_CMD_MTDPARTS
942556a9 394#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
259bff7c 395#define MTDIDS_DEFAULT "nor0=fc000000.flash"
5078cce8 396
5624d66a 397#if defined(CONFIG_STK52XX)
5078cce8 398# if defined(CONFIG_TQM5200_B)
6d0f6bcf 399# if defined(CONFIG_SYS_LOWBOOT)
259bff7c 400# define MTDPARTS_DEFAULT "mtdparts=fc000000.flash:1m(firmware)," \
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401 "256k(dtb)," \
402 "2304k(kernel)," \
403 "2560k(small-fs)," \
45a212c4 404 "2m(initrd)," \
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405 "8m(misc)," \
406 "16m(big-fs)"
407# else /* highboot */
259bff7c 408# define MTDPARTS_DEFAULT "mtdparts=fc000000.flash:2560k(kernel),"\
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409 "3584k(small-fs)," \
410 "2m(initrd)," \
411 "8m(misc)," \
412 "15m(big-fs)," \
413 "1m(firmware)"
6d0f6bcf 414# endif /* CONFIG_SYS_LOWBOOT */
5078cce8 415# else /* !CONFIG_TQM5200_B */
259bff7c 416# define MTDPARTS_DEFAULT "mtdparts=fc000000.flash:640k(firmware),"\
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417 "128k(dtb)," \
418 "2304k(kernel)," \
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419 "2m(initrd)," \
420 "4m(small-fs)," \
5078cce8 421 "8m(misc)," \
e1f601b5 422 "15m(big-fs)"
5078cce8 423# endif /* CONFIG_TQM5200_B */
135ae006 424#elif defined (CONFIG_CAM5200)
259bff7c 425# define MTDPARTS_DEFAULT "mtdparts=fc000000.flash:768k(firmware),"\
5078cce8 426 "1792k(kernel)," \
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427 "5632k(rootfs)," \
428 "24m(home)"
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429#elif defined (CONFIG_CHARON)
430# define MTDPARTS_DEFAULT "mtdparts=fc000000.flash:640k(firmware),"\
431 "1408k(kernel)," \
432 "2m(initrd)," \
433 "4m(small-fs)," \
434 "24320k(big-fs)," \
435 "256k(dts)"
6d3bc9b8 436#elif defined (CONFIG_FO300)
259bff7c 437# define MTDPARTS_DEFAULT "mtdparts=fc000000.flash:640k(firmware),"\
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438 "1408k(kernel)," \
439 "2m(initrd)," \
440 "4m(small-fs)," \
441 "8m(misc)," \
442 "16m(big-fs)"
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443#else
444# error "Unknown Carrier Board"
445#endif /* CONFIG_STK52XX */
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446
447/*
448 * Environment settings
449 */
5a1aceb0 450#define CONFIG_ENV_IS_IN_FLASH 1
0e8d1586 451#define CONFIG_ENV_SIZE 0x4000 /* 16 k - keep small for fast booting */
78d620eb 452#if defined(CONFIG_TQM5200_B) || defined (CONFIG_CAM5200)
0e8d1586 453#define CONFIG_ENV_SECT_SIZE 0x40000
45a212c4 454#else
0e8d1586 455#define CONFIG_ENV_SECT_SIZE 0x20000
5078cce8 456#endif /* CONFIG_TQM5200_B */
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JCPV
457#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
458#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
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459
460/*
461 * Memory map
462 */
6d0f6bcf
JCPV
463#define CONFIG_SYS_MBAR 0xF0000000
464#define CONFIG_SYS_SDRAM_BASE 0x00000000
465#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
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466
467/* Use ON-Chip SRAM until RAM will be available */
6d0f6bcf 468#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
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469#ifdef CONFIG_POST
470/* preserve space for the post_word at end of on-chip SRAM */
553f0982 471#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_POST_SIZE
56523f12 472#else
553f0982 473#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE
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474#endif
475
25ddd1fb 476#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
6d0f6bcf 477#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
56523f12 478
14d0a02a 479#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
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480#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
481# define CONFIG_SYS_RAMBOOT 1
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482#endif
483
135ae006 484#if defined (CONFIG_CAM5200)
6d0f6bcf 485# define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
5078cce8 486#elif defined(CONFIG_TQM5200_B)
6d0f6bcf 487# define CONFIG_SYS_MONITOR_LEN (512 << 10) /* Reserve 512 kB for Monitor */
45a212c4 488#else
6d0f6bcf 489# define CONFIG_SYS_MONITOR_LEN (384 << 10) /* Reserve 384 kB for Monitor */
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490#endif
491
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492#define CONFIG_SYS_MALLOC_LEN (1024 << 10) /* Reserve 1024 kB for malloc() */
493#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
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494
495/*
496 * Ethernet configuration
497 */
498#define CONFIG_MPC5xxx_FEC 1
86321fc1 499#define CONFIG_MPC5xxx_FEC_MII100
56523f12 500/*
86321fc1 501 * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb
56523f12 502 */
86321fc1 503/* #define CONFIG_MPC5xxx_FEC_MII10 */
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504#define CONFIG_PHY_ADDR 0x00
505
506/*
507 * GPIO configuration
508 *
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509 * use CS1: Bit 0 (mask: 0x80000000):
510 * 1 -> Pin gpio_wkup_6 as second SDRAM chip select (mem_cs1).
56523f12 511 * use ALT CAN position: Bits 2-3 (mask: 0x30000000):
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512 * 00 -> No Alternatives, CAN1/2 on PSC2 according to PSC2 setting.
513 * SPI on PSC3 according to PSC3 setting. Use for CAM5200.
514 * 01 -> CAN1 on I2C1, CAN2 on Tmr0/1.
515 * Use for REV200 STK52XX boards and FO300 boards. Do not use
516 * with REV100 modules (because, there I2C1 is used as I2C bus).
517 * use ATA: Bits 6-7 (mask 0x03000000):
518 * 00 -> No ATA chip selects, csb_4/5 used as normal chip selects.
519 * Use for CAM5200 board.
520 * 01 -> ATA cs0/1 on csb_4/5. Use for the remaining boards.
521 * use PSC6: Bits 9-11 (mask 0x00700000):
522 * 000 -> use PSC6_0 to PSC6_3 as GPIO, PSC6 could not be used as
523 * UART, CODEC or IrDA.
524 * GPIO on PSC6_3 is used in post_hotkeys_pressed() to
525 * enable extended POST tests.
526 * Use for MINI-FAP and TQM5200_IB boards.
527 * 101 -> use PSC6 as UART. Pins PSC6_0 to PSC6_3 are used.
528 * Extended POST test is not available.
529 * Use for STK52xx, FO300 and CAM5200 boards.
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530 * WARNING: When the extended POST is enabled, these bits will
531 * be overridden by this code as GPIOs!
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532 * use PCI_DIS: Bit 16 (mask 0x00008000):
533 * 1 -> disable PCI controller (on CAM5200 board).
534 * use USB: Bits 18-19 (mask 0x00003000):
535 * 10 -> two UARTs (on FO300 and CAM5200).
536 * use PSC3: Bits 20-23 (mask: 0x00000f00):
537 * 0000 -> All PSC3 pins are GPIOs.
538 * 1100 -> UART/SPI (on FO300 board).
539 * 0100 -> UART (on CAM5200 board).
540 * use PSC2: Bits 25:27 (mask: 0x00000030):
541 * 000 -> All PSC2 pins are GPIOs.
542 * 100 -> UART (on CAM5200 board).
543 * 001 -> CAN1/2 on PSC2 pins.
95c44ec4 544 * Use for REV100 STK52xx boards
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545 * 01x -> Use AC97 (on FO300 board).
546 * use PSC1: Bits 29-31 (mask: 0x00000007):
547 * 100 -> UART (on all boards).
56523f12 548 */
98e69567 549#if !defined(CONFIG_SYS_GPS_PORT_CONFIG)
56523f12 550#if defined (CONFIG_MINIFAP)
6d0f6bcf 551# define CONFIG_SYS_GPS_PORT_CONFIG 0x91000004
7e6bf358 552#elif defined (CONFIG_STK52XX)
83e40ba7 553# if defined (CONFIG_STK52XX_REV100)
6d0f6bcf 554# define CONFIG_SYS_GPS_PORT_CONFIG 0x81500014
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555# else /* STK52xx REV200 and above */
556# if defined (CONFIG_TQM5200_REV100)
557# error TQM5200 REV100 not supported on STK52XX REV200 or above
558# else/* TQM5200 REV200 and above */
6d0f6bcf 559# define CONFIG_SYS_GPS_PORT_CONFIG 0x91500404
83e40ba7 560# endif
8f0b7cbe 561# endif
6d3bc9b8 562#elif defined (CONFIG_FO300)
6d0f6bcf 563# define CONFIG_SYS_GPS_PORT_CONFIG 0x91502c24
7299712c 564#elif defined (CONFIG_CAM5200)
6d0f6bcf 565# define CONFIG_SYS_GPS_PORT_CONFIG 0x8050A444
83e40ba7 566#else /* TMQ5200 Inbetriebnahme-Board */
6d0f6bcf 567# define CONFIG_SYS_GPS_PORT_CONFIG 0x81000004
56523f12 568#endif
98e69567 569#endif
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570
571/*
572 * RTC configuration
573 */
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574#if defined (CONFIG_STK52XX) && !defined (CONFIG_STK52XX_REV100)
575# define CONFIG_RTC_M41T11 1
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576# define CONFIG_SYS_I2C_RTC_ADDR 0x68
577# define CONFIG_SYS_M41T11_BASE_YEAR 1900 /* because Linux uses the same base
edd0b509 578 year */
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579#else
580# define CONFIG_RTC_MPC5200 1 /* use internal MPC5200 RTC */
581#endif
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582
583/*
584 * Miscellaneous configurable options
585 */
6d0f6bcf 586#define CONFIG_SYS_LONGHELP /* undef to save memory */
5078cce8 587
2751a95a 588#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
5078cce8 589
6d0f6bcf 590#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
2694690e 591#if defined(CONFIG_CMD_KGDB)
6d0f6bcf 592#define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
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593#endif
594
595#if defined(CONFIG_CMD_KGDB)
6d0f6bcf 596#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
56523f12 597#else
6d0f6bcf 598#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
56523f12 599#endif
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600#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
601#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
602#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
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603
604/* Enable an alternate, more extensive memory test */
6d0f6bcf 605#define CONFIG_SYS_ALT_MEMTEST
56523f12 606
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607#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
608#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
56523f12 609
6d0f6bcf 610#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
56523f12 611
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612/*
613 * Various low-level settings
614 */
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615#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
616#define CONFIG_SYS_HID0_FINAL HID0_ICE
56523f12 617
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618#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
619#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
620#ifdef CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2
621#define CONFIG_SYS_BOOTCS_CFG 0x0008DF30 /* for pci_clk = 66 MHz */
56523f12 622#else
6d0f6bcf 623#define CONFIG_SYS_BOOTCS_CFG 0x0004DF30 /* for pci_clk = 33 MHz */
56523f12 624#endif
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625#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
626#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
56523f12 627
7e6bf358 628#define CONFIG_LAST_STAGE_INIT
7e6bf358 629
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630/*
631 * SRAM - Do not map below 2 GB in address space, because this area is used
632 * for SDRAM autosizing.
633 */
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634#define CONFIG_SYS_CS2_START 0xE5000000
635#define CONFIG_SYS_CS2_SIZE 0x100000 /* 1 MByte */
636#define CONFIG_SYS_CS2_CFG 0x0004D930
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637
638/*
639 * Grafic controller - Do not map below 2 GB in address space, because this
640 * area is used for SDRAM autosizing.
641 */
8f0b7cbe 642#define SM501_FB_BASE 0xE0000000
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643#define CONFIG_SYS_CS1_START (SM501_FB_BASE)
644#define CONFIG_SYS_CS1_SIZE 0x4000000 /* 64 MByte */
645#define CONFIG_SYS_CS1_CFG 0x8F48FF70
646#define SM501_MMIO_BASE CONFIG_SYS_CS1_START + 0x03E00000
56523f12 647
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648#define CONFIG_SYS_CS_BURST 0x00000000
649#define CONFIG_SYS_CS_DEADCYCLE 0x33333311 /* 1 dead cycle for flash and SM501 */
56523f12 650
7299712c 651#if defined(CONFIG_CAM5200)
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652#define CONFIG_SYS_CS4_START 0xB0000000
653#define CONFIG_SYS_CS4_SIZE 0x00010000
654#define CONFIG_SYS_CS4_CFG 0x01019C10
7299712c 655
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656#define CONFIG_SYS_CS5_START 0xD0000000
657#define CONFIG_SYS_CS5_SIZE 0x01208000
658#define CONFIG_SYS_CS5_CFG 0x1414BF10
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659#endif
660
6d0f6bcf 661#define CONFIG_SYS_RESET_ADDRESS 0xff000000
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662
663/*-----------------------------------------------------------------------
664 * USB stuff
665 *-----------------------------------------------------------------------
666 */
667#define CONFIG_USB_CLOCK 0x0001BBBB
668#define CONFIG_USB_CONFIG 0x00001000
669
670/*-----------------------------------------------------------------------
671 * IDE/ATA stuff Supports IDE harddisk
672 *-----------------------------------------------------------------------
673 */
674
81050926 675#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
56523f12 676
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677#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
678#undef CONFIG_IDE_LED /* LED for ide not supported */
56523f12 679
81050926 680#define CONFIG_IDE_RESET /* reset for ide supported */
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681#define CONFIG_IDE_PREINIT
682
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683#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
684#define CONFIG_SYS_IDE_MAXDEVICE 2 /* max. 2 drives per IDE bus */
56523f12 685
6d0f6bcf 686#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
56523f12 687
6d0f6bcf 688#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA
56523f12 689
95c44ec4 690/* Offset for data I/O */
6d0f6bcf 691#define CONFIG_SYS_ATA_DATA_OFFSET (0x0060)
56523f12 692
95c44ec4 693/* Offset for normal register accesses */
6d0f6bcf 694#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET)
56523f12 695
95c44ec4 696/* Offset for alternate registers */
6d0f6bcf 697#define CONFIG_SYS_ATA_ALT_OFFSET (0x005C)
56523f12 698
95c44ec4 699/* Interval between registers */
6d0f6bcf 700#define CONFIG_SYS_ATA_STRIDE 4
56523f12 701
33af3e66 702/* Support ATAPI devices */
95c44ec4 703#define CONFIG_ATAPI 1
33af3e66 704
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705/*-----------------------------------------------------------------------
706 * Open firmware flat tree support
707 *-----------------------------------------------------------------------
708 */
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709#define OF_CPU "PowerPC,5200@0"
710#define OF_SOC "soc5200@f0000000"
711#define OF_TBCLK (bd->bi_busfreq / 4)
712#define OF_STDOUT_PATH "/soc5200@f0000000/serial@2000"
713
56523f12 714#endif /* __CONFIG_H */