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56523f12 1/*
69445d6c 2 * (C) Copyright 2003-2014
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3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
45a212c4 5 * (C) Copyright 2004-2006
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6 * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
7 *
3765b3e7 8 * SPDX-License-Identifier: GPL-2.0+
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9 */
10
11#ifndef __CONFIG_H
12#define __CONFIG_H
13
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14/*
15 * High Level Configuration Options
16 * (easy to change)
17 */
18
b2a6dfe4 19#define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */
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20#define CONFIG_TQM5200 1 /* ... on TQM5200 module */
21#undef CONFIG_TQM5200_REV100 /* define for revision 100 modules */
69445d6c 22#define CONFIG_DISPLAY_BOARDINFO
56523f12 23
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24/*
25 * Valid values for CONFIG_SYS_TEXT_BASE are:
26 * 0xFC000000 boot low (standard configuration with room for
27 * max 64 MByte Flash ROM)
28 * 0xFFF00000 boot high (for a backup copy of U-Boot)
29 * 0x00100000 boot from RAM (for testing only)
30 */
31#ifndef CONFIG_SYS_TEXT_BASE
32#define CONFIG_SYS_TEXT_BASE 0xFC000000
33#endif
34
5196a7a0 35/* On a Cameron or on a FO300 board or ... */
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36#if !defined(CONFIG_CAM5200) && !defined(CONFIG_CHARON) \
37 && !defined(CONFIG_FO300)
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38#define CONFIG_STK52XX 1 /* ... on a STK52XX board */
39#endif
40
6d0f6bcf 41#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
56523f12 42
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43#define CONFIG_HIGH_BATS 1 /* High BATs supported */
44
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45/*
46 * Serial console configuration
47 */
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48#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
49#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
6d0f6bcf 50#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
bef92e21 51#define CONFIG_BOOTCOUNT_LIMIT 1
56523f12 52
6d3bc9b8 53#ifdef CONFIG_FO300
6d0f6bcf 54#define CONFIG_SYS_DEVICE_NULLDEV 1 /* enable null device */
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55#define CONFIG_SILENT_CONSOLE 1 /* enable silent startup */
56#define CONFIG_BOARD_EARLY_INIT_F 1 /* used to detect S1 switch position */
ddde6b7c 57#define CONFIG_USB_BIN_FIXUP 1 /* for a buggy USB device */
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58#if 0
59#define FO300_SILENT_CONSOLE_WHEN_S1_CLOSED 1 /* silent console on PSC1 when S1 */
60 /* switch is closed */
61#endif
62
63#undef FO300_SILENT_CONSOLE_WHEN_S1_CLOSED /* silent console on PSC1 when S1 */
64 /* switch is open */
5196a7a0 65#endif /* CONFIG_FO300 */
6d3bc9b8 66
98e69567 67#if defined(CONFIG_CHARON) || defined(CONFIG_STK52XX)
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68#define CONFIG_PS2KBD /* AT-PS/2 Keyboard */
69#define CONFIG_PS2MULT /* .. on PS/2 Multiplexer */
70#define CONFIG_PS2SERIAL 6 /* .. on PSC6 */
6d0f6bcf 71#define CONFIG_PS2MULT_DELAY (CONFIG_SYS_HZ/2) /* Initial delay */
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72#define CONFIG_BOARD_EARLY_INIT_R
73#endif /* CONFIG_STK52XX */
56523f12 74
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75/*
76 * PCI Mapping:
77 * 0x40000000 - 0x4fffffff - PCI Memory
78 * 0x50000000 - 0x50ffffff - PCI IO Space
79 */
98e69567 80#if defined(CONFIG_CHARON) || defined(CONFIG_STK52XX)
7e6bf358 81#define CONFIG_PCI 1
56523f12 82#define CONFIG_PCI_PNP 1
31a64923 83/* #define CONFIG_PCI_SCAN_SHOW 1 */
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84
85#define CONFIG_PCI_MEM_BUS 0x40000000
86#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
87#define CONFIG_PCI_MEM_SIZE 0x10000000
88
89#define CONFIG_PCI_IO_BUS 0x50000000
90#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
91#define CONFIG_PCI_IO_SIZE 0x01000000
92
cd65a3dc 93#define CONFIG_EEPRO100 1
6d0f6bcf 94#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
56523f12 95#define CONFIG_NS8382X 1
83e40ba7 96#endif /* CONFIG_STK52XX */
56523f12 97
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98/*
99 * Video console
100 */
5078cce8 101#ifndef CONFIG_TQM5200S /* No graphics controller on TQM5200S */
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102#define CONFIG_VIDEO
103#define CONFIG_VIDEO_SM501
104#define CONFIG_VIDEO_SM501_32BPP
105#define CONFIG_CFB_CONSOLE
106#define CONFIG_VIDEO_LOGO
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107
108#ifndef CONFIG_FO300
8f0b7cbe 109#define CONFIG_CONSOLE_EXTRA_INFO
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110#else
111#define CONFIG_VIDEO_BMP_LOGO
112#endif
113
114#define CONFIG_VGA_AS_SINGLE_DEVICE
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115#define CONFIG_VIDEO_SW_CURSOR
116#define CONFIG_SPLASH_SCREEN
6d0f6bcf 117#define CONFIG_SYS_CONSOLE_IS_IN_ENV
6d3bc9b8 118#endif /* #ifndef CONFIG_TQM5200S */
56523f12 119
56523f12 120/* Partitions */
89c02e2c 121#define CONFIG_MAC_PARTITION
56523f12 122#define CONFIG_DOS_PARTITION
8f0b7cbe 123#define CONFIG_ISO_PARTITION
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124
125/* USB */
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126#if defined(CONFIG_CHARON) || defined(CONFIG_FO300) || \
127 defined(CONFIG_STK52XX)
7b59b3c7 128#define CONFIG_USB_OHCI_NEW
6d0f6bcf 129#define CONFIG_SYS_OHCI_BE_CONTROLLER
56523f12 130#define CONFIG_USB_STORAGE
53e336e9 131
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132#undef CONFIG_SYS_USB_OHCI_BOARD_INIT
133#define CONFIG_SYS_USB_OHCI_CPU_INIT
134#define CONFIG_SYS_USB_OHCI_REGS_BASE MPC5XXX_USB
135#define CONFIG_SYS_USB_OHCI_SLOT_NAME "mpc5200"
136#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
53e336e9 137
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138#endif
139
135ae006 140#ifndef CONFIG_CAM5200
56523f12 141/* POST support */
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142#define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \
143 CONFIG_SYS_POST_CPU | \
144 CONFIG_SYS_POST_I2C)
5078cce8 145#endif
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146
147#ifdef CONFIG_POST
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148/* preserve space for the post_word at end of on-chip SRAM */
149#define MPC5XXX_SRAM_POST_SIZE MPC5XXX_SRAM_SIZE-4
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150#endif
151
56523f12 152/*
a1aa0bb5 153 * BOOTP options
56523f12 154 */
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155#define CONFIG_BOOTP_BOOTFILESIZE
156#define CONFIG_BOOTP_BOOTPATH
157#define CONFIG_BOOTP_GATEWAY
158#define CONFIG_BOOTP_HOSTNAME
159
56523f12 160/*
2694690e 161 * Command line configuration.
56523f12 162 */
2694690e 163#define CONFIG_CMD_DATE
2694690e 164#define CONFIG_CMD_EEPROM
2694690e 165#define CONFIG_CMD_JFFS2
2694690e 166#define CONFIG_CMD_REGINFO
2694690e
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167#define CONFIG_CMD_BSP
168
169#ifdef CONFIG_VIDEO
170 #define CONFIG_CMD_BMP
171#endif
172
173#ifdef CONFIG_PCI
2b2a587d 174#define CONFIG_CMD_PCI
f33fca22 175#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
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176#endif
177
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178#if defined(CONFIG_CHARON) || defined(CONFIG_FO300) || \
179 defined(CONFIG_MINIFAP) || defined(CONFIG_STK52XX)
2694690e 180 #define CONFIG_CMD_IDE
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181#endif
182
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183#if defined(CONFIG_CHARON) || defined(CONFIG_FO300) || \
184 defined(CONFIG_STK52XX)
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185 #define CONFIG_CFG_USB
186 #define CONFIG_CFG_FAT
187#endif
188
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189#ifdef CONFIG_POST
190 #define CONFIG_CMD_DIAG
191#endif
192
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193#define CONFIG_TIMESTAMP /* display image timestamps */
194
14d0a02a 195#if (CONFIG_SYS_TEXT_BASE != 0xFFF00000)
6d0f6bcf 196# define CONFIG_SYS_LOWBOOT 1 /* Boot low */
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197#endif
198
199/*
200 * Autobooting
201 */
202#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
203
81050926 204#define CONFIG_PREBOOT "echo;" \
4c4aca81 205 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
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206 "echo"
207
208#undef CONFIG_BOOTARGS
209
6d0f6bcf 210#if defined(CONFIG_TQM5200_B) && !defined(CONFIG_SYS_LOWBOOT)
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211# define ENV_UPDT \
212 "update=protect off FFF00000 +${filesize};" \
213 "erase FFF00000 +${filesize};" \
5078cce8 214 "cp.b 200000 FFF00000 ${filesize};" \
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215 "protect on FFF00000 +${filesize}\0"
216#else /* default lowboot configuration */
6d3bc9b8 217# define ENV_UPDT \
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218 "update=protect off FC000000 +${filesize};" \
219 "erase FC000000 +${filesize};" \
6d3bc9b8 220 "cp.b 200000 FC000000 ${filesize};" \
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221 "protect on FC000000 +${filesize}\0"
222#endif
5078cce8 223
e1f601b5 224#if defined(CONFIG_TQM5200)
6abaee42 225#define CUSTOM_ENV_SETTINGS \
e1f601b5 226 "hostname=tqm5200\0" \
6abaee42 227 "bootfile=/tftpboot/tqm5200/uImage\0" \
8f8416fa 228 "fdt_file=/tftpboot/tqm5200/tqm5200.dtb\0" \
6abaee42 229 "u-boot=/tftpboot/tqm5200/u-boot.bin\0"
e1f601b5 230#elif defined(CONFIG_CAM5200)
1636d1c8 231#define CUSTOM_ENV_SETTINGS \
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232 "bootfile=cam5200/uImage\0" \
233 "u-boot=cam5200/u-boot.bin\0" \
74de7aef 234 "setup=tftp 200000 cam5200/setup.img; source 200000\0"
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235#endif
236
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237#if defined(CONFIG_TQM5200_B)
238#define ENV_FLASH_LAYOUT \
239 "fdt_addr=FC100000\0" \
240 "kernel_addr=FC140000\0" \
241 "ramdisk_addr=FC600000\0"
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242#elif defined(CONFIG_CHARON)
243#define ENV_FLASH_LAYOUT \
244 "fdt_addr=FDFC0000\0" \
245 "kernel_addr=FC0A0000\0" \
246 "ramdisk_addr=FC200000\0"
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247#else /* !CONFIG_TQM5200_B */
248#define ENV_FLASH_LAYOUT \
249 "fdt_addr=FC0A0000\0" \
250 "kernel_addr=FC0C0000\0" \
251 "ramdisk_addr=FC300000\0"
252#endif
253
81050926 254#define CONFIG_EXTRA_ENV_SETTINGS \
56523f12 255 "netdev=eth0\0" \
e1f601b5 256 "console=ttyPSC0\0" \
a5cc5555 257 ENV_FLASH_LAYOUT \
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258 "kernel_addr_r=400000\0" \
259 "fdt_addr_r=600000\0" \
89c02e2c 260 "rootpath=/opt/eldk/ppc_6xx\0" \
56523f12 261 "ramargs=setenv bootargs root=/dev/ram rw\0" \
56523f12 262 "nfsargs=setenv bootargs root=/dev/nfs rw " \
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263 "nfsroot=${serverip}:${rootpath}\0" \
264 "addip=setenv bootargs ${bootargs} " \
265 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
266 ":${hostname}:${netdev}:off panic=1\0" \
5078cce8 267 "addcons=setenv bootargs ${bootargs} " \
8f8416fa 268 "console=${console},${baudrate}\0" \
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269 "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
270 "flash_self_old=sete console ttyS0; " \
271 "run ramargs addip addcons addmtd; " \
fe126d8b 272 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
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273 "flash_self=run ramargs addip addcons;" \
274 "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
275 "flash_nfs_old=sete console ttyS0; run nfsargs addip addcons;" \
fe126d8b 276 "bootm ${kernel_addr}\0" \
e1f601b5 277 "flash_nfs=run nfsargs addip addcons;" \
8f8416fa 278 "bootm ${kernel_addr} - ${fdt_addr}\0" \
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279 "net_nfs_old=tftp ${kernel_addr_r} ${bootfile};" \
280 "sete console ttyS0; run nfsargs addip addcons;bootm\0" \
281 "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \
282 "tftp ${fdt_addr_r} ${fdt_file}; " \
98e69567 283 "run nfsargs addip addcons addmtd; " \
e1f601b5 284 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
6abaee42 285 CUSTOM_ENV_SETTINGS \
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286 "load=tftp 200000 ${u-boot}\0" \
287 ENV_UPDT \
7e6bf358 288 ""
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289
290#define CONFIG_BOOTCOMMAND "run net_nfs"
291
292/*
293 * IPB Bus clocking configuration.
294 */
6d0f6bcf 295#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
56523f12 296
6d0f6bcf 297#if defined(CONFIG_SYS_IPBCLK_EQUALS_XLBCLK) && !defined(CONFIG_CAM5200)
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298/*
299 * PCI Bus clocking configuration
300 *
301 * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if
6d0f6bcf 302 * CONFIG_SYS_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock of
c99512d6 303 * 66 MHz yet hasn't been tested with a IPB Bus Clock of 66 MHz.
56523f12 304 */
6d0f6bcf 305#define CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2 /* define for 66MHz speed */
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306#endif
307
308/*
309 * I2C configuration
310 */
311#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
8f0b7cbe 312#ifdef CONFIG_TQM5200_REV100
6d0f6bcf 313#define CONFIG_SYS_I2C_MODULE 1 /* Select I2C module #1 for rev. 100 board */
56523f12 314#else
6d0f6bcf 315#define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #2 for all other revs */
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316#endif
317
318/*
319 * I2C clock frequency
320 *
321 * Please notice, that the resulting clock frequency could differ from the
322 * configured value. This is because the I2C clock is derived from system
a187559e 323 * clock over a frequency divider with only a few divider values. U-Boot
6d0f6bcf 324 * calculates the best approximation for CONFIG_SYS_I2C_SPEED. However the calculated
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325 * approximation allways lies below the configured value, never above.
326 */
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327#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */
328#define CONFIG_SYS_I2C_SLAVE 0x7F
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329
330/*
331 * EEPROM configuration for onboard EEPROM M24C32 (M24C64 should work
332 * also). For other EEPROMs configuration should be verified. On Mini-FAP the
333 * EEPROM (24C64) is on the same I2C address (but on other I2C bus), so the
334 * same configuration could be used.
335 */
6d0f6bcf
JCPV
336#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */
337#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
338#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* =32 Bytes per write */
339#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20
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340
341/*
342 * HW-Monitor configuration on Mini-FAP
343 */
344#if defined (CONFIG_MINIFAP)
6d0f6bcf 345#define CONFIG_SYS_I2C_HWMON_ADDR 0x2C
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346#endif
347
348/* List of I2C addresses to be verified by POST */
56523f12 349#if defined (CONFIG_MINIFAP)
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350#undef CONFIG_SYS_POST_I2C_ADDRS
351#define CONFIG_SYS_POST_I2C_ADDRS {CONFIG_SYS_I2C_EEPROM_ADDR, \
352 CONFIG_SYS_I2C_HWMON_ADDR, \
353 CONFIG_SYS_I2C_SLAVE}
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354#endif
355
356/*
357 * Flash configuration
358 */
6d0f6bcf 359#define CONFIG_SYS_FLASH_BASE 0xFC000000
56523f12 360
d9384de2 361#if defined(CONFIG_CAM5200) && defined(CONFIG_CAM5200_NIOSFLASH)
6d0f6bcf 362#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max num of flash banks
7299712c 363 (= chip selects) */
6d0f6bcf
JCPV
364#define CONFIG_SYS_FLASH_WORD_SIZE unsigned int /* main flash device with */
365#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
366#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
367
368#define CONFIG_SYS_FLASH_ADDR0 0x555
369#define CONFIG_SYS_FLASH_ADDR1 0x2AA
370#define CONFIG_SYS_FLASH_2ND_16BIT_DEV 1 /* NIOS flash is a 16bit device */
371#define CONFIG_SYS_MAX_FLASH_SECT 128
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372#else
373/* use CFI flash driver */
6d0f6bcf 374#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
00b1883a 375#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
085ecde1 376#define CONFIG_FLASH_CFI_MTD /* with MTD support */
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JCPV
377#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_BOOTCS_START }
378#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks
d9384de2 379 (= chip selects) */
6d0f6bcf 380#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */
d9384de2 381#endif
7299712c 382
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383#define CONFIG_SYS_FLASH_EMPTY_INFO
384#define CONFIG_SYS_FLASH_SIZE 0x04000000 /* 64 MByte */
385#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
56523f12 386
135ae006 387#if defined (CONFIG_CAM5200)
6d0f6bcf 388# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00040000)
5078cce8 389#elif defined(CONFIG_TQM5200_B)
6d0f6bcf 390# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00080000)
45a212c4 391#else
6d0f6bcf 392# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00060000)
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393#endif
394
d534f5cc 395/* Dynamic MTD partition support */
68d7d651 396#define CONFIG_CMD_MTDPARTS
942556a9 397#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
259bff7c 398#define MTDIDS_DEFAULT "nor0=fc000000.flash"
5078cce8 399
5624d66a 400#if defined(CONFIG_STK52XX)
5078cce8 401# if defined(CONFIG_TQM5200_B)
6d0f6bcf 402# if defined(CONFIG_SYS_LOWBOOT)
259bff7c 403# define MTDPARTS_DEFAULT "mtdparts=fc000000.flash:1m(firmware)," \
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404 "256k(dtb)," \
405 "2304k(kernel)," \
406 "2560k(small-fs)," \
45a212c4 407 "2m(initrd)," \
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408 "8m(misc)," \
409 "16m(big-fs)"
410# else /* highboot */
259bff7c 411# define MTDPARTS_DEFAULT "mtdparts=fc000000.flash:2560k(kernel),"\
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412 "3584k(small-fs)," \
413 "2m(initrd)," \
414 "8m(misc)," \
415 "15m(big-fs)," \
416 "1m(firmware)"
6d0f6bcf 417# endif /* CONFIG_SYS_LOWBOOT */
5078cce8 418# else /* !CONFIG_TQM5200_B */
259bff7c 419# define MTDPARTS_DEFAULT "mtdparts=fc000000.flash:640k(firmware),"\
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420 "128k(dtb)," \
421 "2304k(kernel)," \
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422 "2m(initrd)," \
423 "4m(small-fs)," \
5078cce8 424 "8m(misc)," \
e1f601b5 425 "15m(big-fs)"
5078cce8 426# endif /* CONFIG_TQM5200_B */
135ae006 427#elif defined (CONFIG_CAM5200)
259bff7c 428# define MTDPARTS_DEFAULT "mtdparts=fc000000.flash:768k(firmware),"\
5078cce8 429 "1792k(kernel)," \
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430 "5632k(rootfs)," \
431 "24m(home)"
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432#elif defined (CONFIG_CHARON)
433# define MTDPARTS_DEFAULT "mtdparts=fc000000.flash:640k(firmware),"\
434 "1408k(kernel)," \
435 "2m(initrd)," \
436 "4m(small-fs)," \
437 "24320k(big-fs)," \
438 "256k(dts)"
6d3bc9b8 439#elif defined (CONFIG_FO300)
259bff7c 440# define MTDPARTS_DEFAULT "mtdparts=fc000000.flash:640k(firmware),"\
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441 "1408k(kernel)," \
442 "2m(initrd)," \
443 "4m(small-fs)," \
444 "8m(misc)," \
445 "16m(big-fs)"
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446#else
447# error "Unknown Carrier Board"
448#endif /* CONFIG_STK52XX */
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449
450/*
451 * Environment settings
452 */
5a1aceb0 453#define CONFIG_ENV_IS_IN_FLASH 1
0e8d1586 454#define CONFIG_ENV_SIZE 0x4000 /* 16 k - keep small for fast booting */
78d620eb 455#if defined(CONFIG_TQM5200_B) || defined (CONFIG_CAM5200)
0e8d1586 456#define CONFIG_ENV_SECT_SIZE 0x40000
45a212c4 457#else
0e8d1586 458#define CONFIG_ENV_SECT_SIZE 0x20000
5078cce8 459#endif /* CONFIG_TQM5200_B */
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460#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
461#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
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462
463/*
464 * Memory map
465 */
6d0f6bcf
JCPV
466#define CONFIG_SYS_MBAR 0xF0000000
467#define CONFIG_SYS_SDRAM_BASE 0x00000000
468#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
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469
470/* Use ON-Chip SRAM until RAM will be available */
6d0f6bcf 471#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
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472#ifdef CONFIG_POST
473/* preserve space for the post_word at end of on-chip SRAM */
553f0982 474#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_POST_SIZE
56523f12 475#else
553f0982 476#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE
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477#endif
478
25ddd1fb 479#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
6d0f6bcf 480#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
56523f12 481
14d0a02a 482#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
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483#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
484# define CONFIG_SYS_RAMBOOT 1
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485#endif
486
135ae006 487#if defined (CONFIG_CAM5200)
6d0f6bcf 488# define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
5078cce8 489#elif defined(CONFIG_TQM5200_B)
6d0f6bcf 490# define CONFIG_SYS_MONITOR_LEN (512 << 10) /* Reserve 512 kB for Monitor */
45a212c4 491#else
6d0f6bcf 492# define CONFIG_SYS_MONITOR_LEN (384 << 10) /* Reserve 384 kB for Monitor */
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493#endif
494
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495#define CONFIG_SYS_MALLOC_LEN (1024 << 10) /* Reserve 1024 kB for malloc() */
496#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
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497
498/*
499 * Ethernet configuration
500 */
501#define CONFIG_MPC5xxx_FEC 1
86321fc1 502#define CONFIG_MPC5xxx_FEC_MII100
56523f12 503/*
86321fc1 504 * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb
56523f12 505 */
86321fc1 506/* #define CONFIG_MPC5xxx_FEC_MII10 */
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507#define CONFIG_PHY_ADDR 0x00
508
509/*
510 * GPIO configuration
511 *
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512 * use CS1: Bit 0 (mask: 0x80000000):
513 * 1 -> Pin gpio_wkup_6 as second SDRAM chip select (mem_cs1).
56523f12 514 * use ALT CAN position: Bits 2-3 (mask: 0x30000000):
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515 * 00 -> No Alternatives, CAN1/2 on PSC2 according to PSC2 setting.
516 * SPI on PSC3 according to PSC3 setting. Use for CAM5200.
517 * 01 -> CAN1 on I2C1, CAN2 on Tmr0/1.
518 * Use for REV200 STK52XX boards and FO300 boards. Do not use
519 * with REV100 modules (because, there I2C1 is used as I2C bus).
520 * use ATA: Bits 6-7 (mask 0x03000000):
521 * 00 -> No ATA chip selects, csb_4/5 used as normal chip selects.
522 * Use for CAM5200 board.
523 * 01 -> ATA cs0/1 on csb_4/5. Use for the remaining boards.
524 * use PSC6: Bits 9-11 (mask 0x00700000):
525 * 000 -> use PSC6_0 to PSC6_3 as GPIO, PSC6 could not be used as
526 * UART, CODEC or IrDA.
527 * GPIO on PSC6_3 is used in post_hotkeys_pressed() to
528 * enable extended POST tests.
529 * Use for MINI-FAP and TQM5200_IB boards.
530 * 101 -> use PSC6 as UART. Pins PSC6_0 to PSC6_3 are used.
531 * Extended POST test is not available.
532 * Use for STK52xx, FO300 and CAM5200 boards.
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533 * WARNING: When the extended POST is enabled, these bits will
534 * be overridden by this code as GPIOs!
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535 * use PCI_DIS: Bit 16 (mask 0x00008000):
536 * 1 -> disable PCI controller (on CAM5200 board).
537 * use USB: Bits 18-19 (mask 0x00003000):
538 * 10 -> two UARTs (on FO300 and CAM5200).
539 * use PSC3: Bits 20-23 (mask: 0x00000f00):
540 * 0000 -> All PSC3 pins are GPIOs.
541 * 1100 -> UART/SPI (on FO300 board).
542 * 0100 -> UART (on CAM5200 board).
543 * use PSC2: Bits 25:27 (mask: 0x00000030):
544 * 000 -> All PSC2 pins are GPIOs.
545 * 100 -> UART (on CAM5200 board).
546 * 001 -> CAN1/2 on PSC2 pins.
95c44ec4 547 * Use for REV100 STK52xx boards
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548 * 01x -> Use AC97 (on FO300 board).
549 * use PSC1: Bits 29-31 (mask: 0x00000007):
550 * 100 -> UART (on all boards).
56523f12 551 */
98e69567 552#if !defined(CONFIG_SYS_GPS_PORT_CONFIG)
56523f12 553#if defined (CONFIG_MINIFAP)
6d0f6bcf 554# define CONFIG_SYS_GPS_PORT_CONFIG 0x91000004
7e6bf358 555#elif defined (CONFIG_STK52XX)
83e40ba7 556# if defined (CONFIG_STK52XX_REV100)
6d0f6bcf 557# define CONFIG_SYS_GPS_PORT_CONFIG 0x81500014
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558# else /* STK52xx REV200 and above */
559# if defined (CONFIG_TQM5200_REV100)
560# error TQM5200 REV100 not supported on STK52XX REV200 or above
561# else/* TQM5200 REV200 and above */
6d0f6bcf 562# define CONFIG_SYS_GPS_PORT_CONFIG 0x91500404
83e40ba7 563# endif
8f0b7cbe 564# endif
6d3bc9b8 565#elif defined (CONFIG_FO300)
6d0f6bcf 566# define CONFIG_SYS_GPS_PORT_CONFIG 0x91502c24
7299712c 567#elif defined (CONFIG_CAM5200)
6d0f6bcf 568# define CONFIG_SYS_GPS_PORT_CONFIG 0x8050A444
83e40ba7 569#else /* TMQ5200 Inbetriebnahme-Board */
6d0f6bcf 570# define CONFIG_SYS_GPS_PORT_CONFIG 0x81000004
56523f12 571#endif
98e69567 572#endif
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573
574/*
575 * RTC configuration
576 */
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577#if defined (CONFIG_STK52XX) && !defined (CONFIG_STK52XX_REV100)
578# define CONFIG_RTC_M41T11 1
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579# define CONFIG_SYS_I2C_RTC_ADDR 0x68
580# define CONFIG_SYS_M41T11_BASE_YEAR 1900 /* because Linux uses the same base
edd0b509 581 year */
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582#else
583# define CONFIG_RTC_MPC5200 1 /* use internal MPC5200 RTC */
584#endif
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585
586/*
587 * Miscellaneous configurable options
588 */
6d0f6bcf 589#define CONFIG_SYS_LONGHELP /* undef to save memory */
5078cce8 590
2751a95a 591#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
5078cce8 592
6d0f6bcf 593#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
2694690e 594#if defined(CONFIG_CMD_KGDB)
6d0f6bcf 595#define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
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596#endif
597
598#if defined(CONFIG_CMD_KGDB)
6d0f6bcf 599#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
56523f12 600#else
6d0f6bcf 601#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
56523f12 602#endif
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603#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
604#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
605#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
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606
607/* Enable an alternate, more extensive memory test */
6d0f6bcf 608#define CONFIG_SYS_ALT_MEMTEST
56523f12 609
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610#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
611#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
56523f12 612
6d0f6bcf 613#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
56523f12 614
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615/*
616 * Various low-level settings
617 */
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618#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
619#define CONFIG_SYS_HID0_FINAL HID0_ICE
56523f12 620
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621#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
622#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
623#ifdef CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2
624#define CONFIG_SYS_BOOTCS_CFG 0x0008DF30 /* for pci_clk = 66 MHz */
56523f12 625#else
6d0f6bcf 626#define CONFIG_SYS_BOOTCS_CFG 0x0004DF30 /* for pci_clk = 33 MHz */
56523f12 627#endif
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628#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
629#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
56523f12 630
7e6bf358 631#define CONFIG_LAST_STAGE_INIT
7e6bf358 632
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633/*
634 * SRAM - Do not map below 2 GB in address space, because this area is used
635 * for SDRAM autosizing.
636 */
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637#define CONFIG_SYS_CS2_START 0xE5000000
638#define CONFIG_SYS_CS2_SIZE 0x100000 /* 1 MByte */
639#define CONFIG_SYS_CS2_CFG 0x0004D930
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640
641/*
642 * Grafic controller - Do not map below 2 GB in address space, because this
643 * area is used for SDRAM autosizing.
644 */
8f0b7cbe 645#define SM501_FB_BASE 0xE0000000
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646#define CONFIG_SYS_CS1_START (SM501_FB_BASE)
647#define CONFIG_SYS_CS1_SIZE 0x4000000 /* 64 MByte */
648#define CONFIG_SYS_CS1_CFG 0x8F48FF70
649#define SM501_MMIO_BASE CONFIG_SYS_CS1_START + 0x03E00000
56523f12 650
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651#define CONFIG_SYS_CS_BURST 0x00000000
652#define CONFIG_SYS_CS_DEADCYCLE 0x33333311 /* 1 dead cycle for flash and SM501 */
56523f12 653
7299712c 654#if defined(CONFIG_CAM5200)
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655#define CONFIG_SYS_CS4_START 0xB0000000
656#define CONFIG_SYS_CS4_SIZE 0x00010000
657#define CONFIG_SYS_CS4_CFG 0x01019C10
7299712c 658
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659#define CONFIG_SYS_CS5_START 0xD0000000
660#define CONFIG_SYS_CS5_SIZE 0x01208000
661#define CONFIG_SYS_CS5_CFG 0x1414BF10
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662#endif
663
6d0f6bcf 664#define CONFIG_SYS_RESET_ADDRESS 0xff000000
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665
666/*-----------------------------------------------------------------------
667 * USB stuff
668 *-----------------------------------------------------------------------
669 */
670#define CONFIG_USB_CLOCK 0x0001BBBB
671#define CONFIG_USB_CONFIG 0x00001000
672
673/*-----------------------------------------------------------------------
674 * IDE/ATA stuff Supports IDE harddisk
675 *-----------------------------------------------------------------------
676 */
677
81050926 678#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
56523f12 679
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680#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
681#undef CONFIG_IDE_LED /* LED for ide not supported */
56523f12 682
81050926 683#define CONFIG_IDE_RESET /* reset for ide supported */
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684#define CONFIG_IDE_PREINIT
685
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686#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
687#define CONFIG_SYS_IDE_MAXDEVICE 2 /* max. 2 drives per IDE bus */
56523f12 688
6d0f6bcf 689#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
56523f12 690
6d0f6bcf 691#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA
56523f12 692
95c44ec4 693/* Offset for data I/O */
6d0f6bcf 694#define CONFIG_SYS_ATA_DATA_OFFSET (0x0060)
56523f12 695
95c44ec4 696/* Offset for normal register accesses */
6d0f6bcf 697#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET)
56523f12 698
95c44ec4 699/* Offset for alternate registers */
6d0f6bcf 700#define CONFIG_SYS_ATA_ALT_OFFSET (0x005C)
56523f12 701
95c44ec4 702/* Interval between registers */
6d0f6bcf 703#define CONFIG_SYS_ATA_STRIDE 4
56523f12 704
33af3e66 705/* Support ATAPI devices */
95c44ec4 706#define CONFIG_ATAPI 1
33af3e66 707
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708/*-----------------------------------------------------------------------
709 * Open firmware flat tree support
710 *-----------------------------------------------------------------------
711 */
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712#define OF_CPU "PowerPC,5200@0"
713#define OF_SOC "soc5200@f0000000"
714#define OF_TBCLK (bd->bi_busfreq / 4)
715#define OF_STDOUT_PATH "/soc5200@f0000000/serial@2000"
716
56523f12 717#endif /* __CONFIG_H */