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56523f12 1/*
69445d6c 2 * (C) Copyright 2003-2014
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3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
45a212c4 5 * (C) Copyright 2004-2006
56523f12
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6 * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
7 *
3765b3e7 8 * SPDX-License-Identifier: GPL-2.0+
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9 */
10
11#ifndef __CONFIG_H
12#define __CONFIG_H
13
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14/*
15 * High Level Configuration Options
16 * (easy to change)
17 */
18
b2a6dfe4 19#define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */
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20#define CONFIG_TQM5200 1 /* ... on TQM5200 module */
21#undef CONFIG_TQM5200_REV100 /* define for revision 100 modules */
56523f12 22
2ae18241
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23/*
24 * Valid values for CONFIG_SYS_TEXT_BASE are:
25 * 0xFC000000 boot low (standard configuration with room for
26 * max 64 MByte Flash ROM)
27 * 0xFFF00000 boot high (for a backup copy of U-Boot)
28 * 0x00100000 boot from RAM (for testing only)
29 */
30#ifndef CONFIG_SYS_TEXT_BASE
31#define CONFIG_SYS_TEXT_BASE 0xFC000000
32#endif
33
5196a7a0 34/* On a Cameron or on a FO300 board or ... */
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35#if !defined(CONFIG_CAM5200) && !defined(CONFIG_CHARON) \
36 && !defined(CONFIG_FO300)
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37#define CONFIG_STK52XX 1 /* ... on a STK52XX board */
38#endif
39
6d0f6bcf 40#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
56523f12 41
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42#define CONFIG_HIGH_BATS 1 /* High BATs supported */
43
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44/*
45 * Serial console configuration
46 */
5078cce8 47#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
6d0f6bcf 48#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
bef92e21 49#define CONFIG_BOOTCOUNT_LIMIT 1
56523f12 50
6d3bc9b8 51#ifdef CONFIG_FO300
6d0f6bcf 52#define CONFIG_SYS_DEVICE_NULLDEV 1 /* enable null device */
ddde6b7c 53#define CONFIG_USB_BIN_FIXUP 1 /* for a buggy USB device */
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54#if 0
55#define FO300_SILENT_CONSOLE_WHEN_S1_CLOSED 1 /* silent console on PSC1 when S1 */
56 /* switch is closed */
57#endif
58
59#undef FO300_SILENT_CONSOLE_WHEN_S1_CLOSED /* silent console on PSC1 when S1 */
60 /* switch is open */
5196a7a0 61#endif /* CONFIG_FO300 */
6d3bc9b8 62
98e69567 63#if defined(CONFIG_CHARON) || defined(CONFIG_STK52XX)
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64#define CONFIG_PS2KBD /* AT-PS/2 Keyboard */
65#define CONFIG_PS2MULT /* .. on PS/2 Multiplexer */
66#define CONFIG_PS2SERIAL 6 /* .. on PSC6 */
6d0f6bcf 67#define CONFIG_PS2MULT_DELAY (CONFIG_SYS_HZ/2) /* Initial delay */
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68#define CONFIG_BOARD_EARLY_INIT_R
69#endif /* CONFIG_STK52XX */
56523f12 70
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71/*
72 * PCI Mapping:
73 * 0x40000000 - 0x4fffffff - PCI Memory
74 * 0x50000000 - 0x50ffffff - PCI IO Space
75 */
98e69567 76#if defined(CONFIG_CHARON) || defined(CONFIG_STK52XX)
31a64923 77/* #define CONFIG_PCI_SCAN_SHOW 1 */
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78
79#define CONFIG_PCI_MEM_BUS 0x40000000
80#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
81#define CONFIG_PCI_MEM_SIZE 0x10000000
82
83#define CONFIG_PCI_IO_BUS 0x50000000
84#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
85#define CONFIG_PCI_IO_SIZE 0x01000000
86
cd65a3dc 87#define CONFIG_EEPRO100 1
6d0f6bcf 88#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
56523f12 89#define CONFIG_NS8382X 1
83e40ba7 90#endif /* CONFIG_STK52XX */
56523f12 91
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92/*
93 * Video console
94 */
5078cce8 95#ifndef CONFIG_TQM5200S /* No graphics controller on TQM5200S */
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96#define CONFIG_VIDEO_SM501
97#define CONFIG_VIDEO_SM501_32BPP
8f0b7cbe 98#define CONFIG_VIDEO_LOGO
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99
100#ifndef CONFIG_FO300
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101#else
102#define CONFIG_VIDEO_BMP_LOGO
103#endif
104
8f0b7cbe 105#define CONFIG_SPLASH_SCREEN
6d3bc9b8 106#endif /* #ifndef CONFIG_TQM5200S */
56523f12 107
56523f12 108/* Partitions */
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109
110/* USB */
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111#if defined(CONFIG_CHARON) || defined(CONFIG_FO300) || \
112 defined(CONFIG_STK52XX)
7b59b3c7 113#define CONFIG_USB_OHCI_NEW
6d0f6bcf 114#define CONFIG_SYS_OHCI_BE_CONTROLLER
53e336e9 115
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116#undef CONFIG_SYS_USB_OHCI_BOARD_INIT
117#define CONFIG_SYS_USB_OHCI_CPU_INIT
118#define CONFIG_SYS_USB_OHCI_REGS_BASE MPC5XXX_USB
119#define CONFIG_SYS_USB_OHCI_SLOT_NAME "mpc5200"
120#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
53e336e9 121
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122#endif
123
135ae006 124#ifndef CONFIG_CAM5200
56523f12 125/* POST support */
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126#define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \
127 CONFIG_SYS_POST_CPU | \
128 CONFIG_SYS_POST_I2C)
5078cce8 129#endif
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130
131#ifdef CONFIG_POST
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132/* preserve space for the post_word at end of on-chip SRAM */
133#define MPC5XXX_SRAM_POST_SIZE MPC5XXX_SRAM_SIZE-4
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134#endif
135
56523f12 136/*
a1aa0bb5 137 * BOOTP options
56523f12 138 */
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139#define CONFIG_BOOTP_BOOTFILESIZE
140#define CONFIG_BOOTP_BOOTPATH
141#define CONFIG_BOOTP_GATEWAY
142#define CONFIG_BOOTP_HOSTNAME
143
56523f12 144/*
2694690e 145 * Command line configuration.
56523f12 146 */
2694690e 147#define CONFIG_CMD_EEPROM
2694690e 148#define CONFIG_CMD_JFFS2
2694690e 149#define CONFIG_CMD_REGINFO
2694690e 150
2694690e 151#ifdef CONFIG_PCI
2b2a587d 152#define CONFIG_CMD_PCI
f33fca22 153#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
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154#endif
155
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156#if defined(CONFIG_CHARON) || defined(CONFIG_FO300) || \
157 defined(CONFIG_MINIFAP) || defined(CONFIG_STK52XX)
2694690e 158 #define CONFIG_CMD_IDE
2694690e
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159#endif
160
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161#if defined(CONFIG_CHARON) || defined(CONFIG_FO300) || \
162 defined(CONFIG_STK52XX)
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163 #define CONFIG_CFG_USB
164 #define CONFIG_CFG_FAT
165#endif
166
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167#define CONFIG_TIMESTAMP /* display image timestamps */
168
14d0a02a 169#if (CONFIG_SYS_TEXT_BASE != 0xFFF00000)
6d0f6bcf 170# define CONFIG_SYS_LOWBOOT 1 /* Boot low */
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171#endif
172
173/*
174 * Autobooting
175 */
56523f12 176
81050926 177#define CONFIG_PREBOOT "echo;" \
4c4aca81 178 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
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179 "echo"
180
181#undef CONFIG_BOOTARGS
182
6d0f6bcf 183#if defined(CONFIG_TQM5200_B) && !defined(CONFIG_SYS_LOWBOOT)
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184# define ENV_UPDT \
185 "update=protect off FFF00000 +${filesize};" \
186 "erase FFF00000 +${filesize};" \
5078cce8 187 "cp.b 200000 FFF00000 ${filesize};" \
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188 "protect on FFF00000 +${filesize}\0"
189#else /* default lowboot configuration */
6d3bc9b8 190# define ENV_UPDT \
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191 "update=protect off FC000000 +${filesize};" \
192 "erase FC000000 +${filesize};" \
6d3bc9b8 193 "cp.b 200000 FC000000 ${filesize};" \
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194 "protect on FC000000 +${filesize}\0"
195#endif
5078cce8 196
e1f601b5 197#if defined(CONFIG_TQM5200)
6abaee42 198#define CUSTOM_ENV_SETTINGS \
e1f601b5 199 "hostname=tqm5200\0" \
6abaee42 200 "bootfile=/tftpboot/tqm5200/uImage\0" \
8f8416fa 201 "fdt_file=/tftpboot/tqm5200/tqm5200.dtb\0" \
6abaee42 202 "u-boot=/tftpboot/tqm5200/u-boot.bin\0"
e1f601b5 203#elif defined(CONFIG_CAM5200)
1636d1c8 204#define CUSTOM_ENV_SETTINGS \
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205 "bootfile=cam5200/uImage\0" \
206 "u-boot=cam5200/u-boot.bin\0" \
74de7aef 207 "setup=tftp 200000 cam5200/setup.img; source 200000\0"
6abaee42
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208#endif
209
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210#if defined(CONFIG_TQM5200_B)
211#define ENV_FLASH_LAYOUT \
212 "fdt_addr=FC100000\0" \
213 "kernel_addr=FC140000\0" \
214 "ramdisk_addr=FC600000\0"
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215#elif defined(CONFIG_CHARON)
216#define ENV_FLASH_LAYOUT \
217 "fdt_addr=FDFC0000\0" \
218 "kernel_addr=FC0A0000\0" \
219 "ramdisk_addr=FC200000\0"
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220#else /* !CONFIG_TQM5200_B */
221#define ENV_FLASH_LAYOUT \
222 "fdt_addr=FC0A0000\0" \
223 "kernel_addr=FC0C0000\0" \
224 "ramdisk_addr=FC300000\0"
225#endif
226
81050926 227#define CONFIG_EXTRA_ENV_SETTINGS \
56523f12 228 "netdev=eth0\0" \
e1f601b5 229 "console=ttyPSC0\0" \
a5cc5555 230 ENV_FLASH_LAYOUT \
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231 "kernel_addr_r=400000\0" \
232 "fdt_addr_r=600000\0" \
89c02e2c 233 "rootpath=/opt/eldk/ppc_6xx\0" \
56523f12 234 "ramargs=setenv bootargs root=/dev/ram rw\0" \
56523f12 235 "nfsargs=setenv bootargs root=/dev/nfs rw " \
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236 "nfsroot=${serverip}:${rootpath}\0" \
237 "addip=setenv bootargs ${bootargs} " \
238 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
239 ":${hostname}:${netdev}:off panic=1\0" \
5078cce8 240 "addcons=setenv bootargs ${bootargs} " \
8f8416fa 241 "console=${console},${baudrate}\0" \
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242 "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
243 "flash_self_old=sete console ttyS0; " \
244 "run ramargs addip addcons addmtd; " \
fe126d8b 245 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
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246 "flash_self=run ramargs addip addcons;" \
247 "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
248 "flash_nfs_old=sete console ttyS0; run nfsargs addip addcons;" \
fe126d8b 249 "bootm ${kernel_addr}\0" \
e1f601b5 250 "flash_nfs=run nfsargs addip addcons;" \
8f8416fa 251 "bootm ${kernel_addr} - ${fdt_addr}\0" \
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252 "net_nfs_old=tftp ${kernel_addr_r} ${bootfile};" \
253 "sete console ttyS0; run nfsargs addip addcons;bootm\0" \
254 "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \
255 "tftp ${fdt_addr_r} ${fdt_file}; " \
98e69567 256 "run nfsargs addip addcons addmtd; " \
e1f601b5 257 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
6abaee42 258 CUSTOM_ENV_SETTINGS \
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259 "load=tftp 200000 ${u-boot}\0" \
260 ENV_UPDT \
7e6bf358 261 ""
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262
263#define CONFIG_BOOTCOMMAND "run net_nfs"
264
265/*
266 * IPB Bus clocking configuration.
267 */
6d0f6bcf 268#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
56523f12 269
6d0f6bcf 270#if defined(CONFIG_SYS_IPBCLK_EQUALS_XLBCLK) && !defined(CONFIG_CAM5200)
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271/*
272 * PCI Bus clocking configuration
273 *
274 * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if
6d0f6bcf 275 * CONFIG_SYS_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock of
c99512d6 276 * 66 MHz yet hasn't been tested with a IPB Bus Clock of 66 MHz.
56523f12 277 */
6d0f6bcf 278#define CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2 /* define for 66MHz speed */
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279#endif
280
281/*
282 * I2C configuration
283 */
284#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
8f0b7cbe 285#ifdef CONFIG_TQM5200_REV100
6d0f6bcf 286#define CONFIG_SYS_I2C_MODULE 1 /* Select I2C module #1 for rev. 100 board */
56523f12 287#else
6d0f6bcf 288#define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #2 for all other revs */
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289#endif
290
291/*
292 * I2C clock frequency
293 *
294 * Please notice, that the resulting clock frequency could differ from the
295 * configured value. This is because the I2C clock is derived from system
a187559e 296 * clock over a frequency divider with only a few divider values. U-Boot
6d0f6bcf 297 * calculates the best approximation for CONFIG_SYS_I2C_SPEED. However the calculated
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298 * approximation allways lies below the configured value, never above.
299 */
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300#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */
301#define CONFIG_SYS_I2C_SLAVE 0x7F
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302
303/*
304 * EEPROM configuration for onboard EEPROM M24C32 (M24C64 should work
305 * also). For other EEPROMs configuration should be verified. On Mini-FAP the
306 * EEPROM (24C64) is on the same I2C address (but on other I2C bus), so the
307 * same configuration could be used.
308 */
6d0f6bcf
JCPV
309#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */
310#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
311#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* =32 Bytes per write */
312#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20
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313
314/*
315 * HW-Monitor configuration on Mini-FAP
316 */
317#if defined (CONFIG_MINIFAP)
6d0f6bcf 318#define CONFIG_SYS_I2C_HWMON_ADDR 0x2C
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319#endif
320
321/* List of I2C addresses to be verified by POST */
56523f12 322#if defined (CONFIG_MINIFAP)
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323#undef CONFIG_SYS_POST_I2C_ADDRS
324#define CONFIG_SYS_POST_I2C_ADDRS {CONFIG_SYS_I2C_EEPROM_ADDR, \
325 CONFIG_SYS_I2C_HWMON_ADDR, \
326 CONFIG_SYS_I2C_SLAVE}
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327#endif
328
329/*
330 * Flash configuration
331 */
6d0f6bcf 332#define CONFIG_SYS_FLASH_BASE 0xFC000000
56523f12 333
d9384de2 334#if defined(CONFIG_CAM5200) && defined(CONFIG_CAM5200_NIOSFLASH)
6d0f6bcf 335#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max num of flash banks
7299712c 336 (= chip selects) */
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JCPV
337#define CONFIG_SYS_FLASH_WORD_SIZE unsigned int /* main flash device with */
338#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
339#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
340
341#define CONFIG_SYS_FLASH_ADDR0 0x555
342#define CONFIG_SYS_FLASH_ADDR1 0x2AA
343#define CONFIG_SYS_FLASH_2ND_16BIT_DEV 1 /* NIOS flash is a 16bit device */
344#define CONFIG_SYS_MAX_FLASH_SECT 128
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345#else
346/* use CFI flash driver */
6d0f6bcf 347#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
00b1883a 348#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
085ecde1 349#define CONFIG_FLASH_CFI_MTD /* with MTD support */
6d0f6bcf
JCPV
350#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_BOOTCS_START }
351#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks
d9384de2 352 (= chip selects) */
6d0f6bcf 353#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */
d9384de2 354#endif
7299712c 355
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JCPV
356#define CONFIG_SYS_FLASH_EMPTY_INFO
357#define CONFIG_SYS_FLASH_SIZE 0x04000000 /* 64 MByte */
358#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
56523f12 359
135ae006 360#if defined (CONFIG_CAM5200)
6d0f6bcf 361# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00040000)
5078cce8 362#elif defined(CONFIG_TQM5200_B)
6d0f6bcf 363# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00080000)
45a212c4 364#else
6d0f6bcf 365# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00060000)
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366#endif
367
d534f5cc 368/* Dynamic MTD partition support */
68d7d651 369#define CONFIG_CMD_MTDPARTS
942556a9 370#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
259bff7c 371#define MTDIDS_DEFAULT "nor0=fc000000.flash"
5078cce8 372
5624d66a 373#if defined(CONFIG_STK52XX)
5078cce8 374# if defined(CONFIG_TQM5200_B)
6d0f6bcf 375# if defined(CONFIG_SYS_LOWBOOT)
259bff7c 376# define MTDPARTS_DEFAULT "mtdparts=fc000000.flash:1m(firmware)," \
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377 "256k(dtb)," \
378 "2304k(kernel)," \
379 "2560k(small-fs)," \
45a212c4 380 "2m(initrd)," \
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381 "8m(misc)," \
382 "16m(big-fs)"
383# else /* highboot */
259bff7c 384# define MTDPARTS_DEFAULT "mtdparts=fc000000.flash:2560k(kernel),"\
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385 "3584k(small-fs)," \
386 "2m(initrd)," \
387 "8m(misc)," \
388 "15m(big-fs)," \
389 "1m(firmware)"
6d0f6bcf 390# endif /* CONFIG_SYS_LOWBOOT */
5078cce8 391# else /* !CONFIG_TQM5200_B */
259bff7c 392# define MTDPARTS_DEFAULT "mtdparts=fc000000.flash:640k(firmware),"\
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393 "128k(dtb)," \
394 "2304k(kernel)," \
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395 "2m(initrd)," \
396 "4m(small-fs)," \
5078cce8 397 "8m(misc)," \
e1f601b5 398 "15m(big-fs)"
5078cce8 399# endif /* CONFIG_TQM5200_B */
135ae006 400#elif defined (CONFIG_CAM5200)
259bff7c 401# define MTDPARTS_DEFAULT "mtdparts=fc000000.flash:768k(firmware),"\
5078cce8 402 "1792k(kernel)," \
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403 "5632k(rootfs)," \
404 "24m(home)"
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HS
405#elif defined (CONFIG_CHARON)
406# define MTDPARTS_DEFAULT "mtdparts=fc000000.flash:640k(firmware),"\
407 "1408k(kernel)," \
408 "2m(initrd)," \
409 "4m(small-fs)," \
410 "24320k(big-fs)," \
411 "256k(dts)"
6d3bc9b8 412#elif defined (CONFIG_FO300)
259bff7c 413# define MTDPARTS_DEFAULT "mtdparts=fc000000.flash:640k(firmware),"\
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414 "1408k(kernel)," \
415 "2m(initrd)," \
416 "4m(small-fs)," \
417 "8m(misc)," \
418 "16m(big-fs)"
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419#else
420# error "Unknown Carrier Board"
421#endif /* CONFIG_STK52XX */
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422
423/*
424 * Environment settings
425 */
5a1aceb0 426#define CONFIG_ENV_IS_IN_FLASH 1
0e8d1586 427#define CONFIG_ENV_SIZE 0x4000 /* 16 k - keep small for fast booting */
78d620eb 428#if defined(CONFIG_TQM5200_B) || defined (CONFIG_CAM5200)
0e8d1586 429#define CONFIG_ENV_SECT_SIZE 0x40000
45a212c4 430#else
0e8d1586 431#define CONFIG_ENV_SECT_SIZE 0x20000
5078cce8 432#endif /* CONFIG_TQM5200_B */
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433#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
434#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
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435
436/*
437 * Memory map
438 */
6d0f6bcf
JCPV
439#define CONFIG_SYS_MBAR 0xF0000000
440#define CONFIG_SYS_SDRAM_BASE 0x00000000
441#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
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442
443/* Use ON-Chip SRAM until RAM will be available */
6d0f6bcf 444#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
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445#ifdef CONFIG_POST
446/* preserve space for the post_word at end of on-chip SRAM */
553f0982 447#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_POST_SIZE
56523f12 448#else
553f0982 449#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE
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450#endif
451
25ddd1fb 452#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
6d0f6bcf 453#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
56523f12 454
14d0a02a 455#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
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456#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
457# define CONFIG_SYS_RAMBOOT 1
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458#endif
459
135ae006 460#if defined (CONFIG_CAM5200)
6d0f6bcf 461# define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
5078cce8 462#elif defined(CONFIG_TQM5200_B)
6d0f6bcf 463# define CONFIG_SYS_MONITOR_LEN (512 << 10) /* Reserve 512 kB for Monitor */
45a212c4 464#else
6d0f6bcf 465# define CONFIG_SYS_MONITOR_LEN (384 << 10) /* Reserve 384 kB for Monitor */
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466#endif
467
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JCPV
468#define CONFIG_SYS_MALLOC_LEN (1024 << 10) /* Reserve 1024 kB for malloc() */
469#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
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470
471/*
472 * Ethernet configuration
473 */
474#define CONFIG_MPC5xxx_FEC 1
86321fc1 475#define CONFIG_MPC5xxx_FEC_MII100
56523f12 476/*
86321fc1 477 * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb
56523f12 478 */
86321fc1 479/* #define CONFIG_MPC5xxx_FEC_MII10 */
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480#define CONFIG_PHY_ADDR 0x00
481
482/*
483 * GPIO configuration
484 *
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485 * use CS1: Bit 0 (mask: 0x80000000):
486 * 1 -> Pin gpio_wkup_6 as second SDRAM chip select (mem_cs1).
56523f12 487 * use ALT CAN position: Bits 2-3 (mask: 0x30000000):
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488 * 00 -> No Alternatives, CAN1/2 on PSC2 according to PSC2 setting.
489 * SPI on PSC3 according to PSC3 setting. Use for CAM5200.
490 * 01 -> CAN1 on I2C1, CAN2 on Tmr0/1.
491 * Use for REV200 STK52XX boards and FO300 boards. Do not use
492 * with REV100 modules (because, there I2C1 is used as I2C bus).
493 * use ATA: Bits 6-7 (mask 0x03000000):
494 * 00 -> No ATA chip selects, csb_4/5 used as normal chip selects.
495 * Use for CAM5200 board.
496 * 01 -> ATA cs0/1 on csb_4/5. Use for the remaining boards.
497 * use PSC6: Bits 9-11 (mask 0x00700000):
498 * 000 -> use PSC6_0 to PSC6_3 as GPIO, PSC6 could not be used as
499 * UART, CODEC or IrDA.
500 * GPIO on PSC6_3 is used in post_hotkeys_pressed() to
501 * enable extended POST tests.
502 * Use for MINI-FAP and TQM5200_IB boards.
503 * 101 -> use PSC6 as UART. Pins PSC6_0 to PSC6_3 are used.
504 * Extended POST test is not available.
505 * Use for STK52xx, FO300 and CAM5200 boards.
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506 * WARNING: When the extended POST is enabled, these bits will
507 * be overridden by this code as GPIOs!
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508 * use PCI_DIS: Bit 16 (mask 0x00008000):
509 * 1 -> disable PCI controller (on CAM5200 board).
510 * use USB: Bits 18-19 (mask 0x00003000):
511 * 10 -> two UARTs (on FO300 and CAM5200).
512 * use PSC3: Bits 20-23 (mask: 0x00000f00):
513 * 0000 -> All PSC3 pins are GPIOs.
514 * 1100 -> UART/SPI (on FO300 board).
515 * 0100 -> UART (on CAM5200 board).
516 * use PSC2: Bits 25:27 (mask: 0x00000030):
517 * 000 -> All PSC2 pins are GPIOs.
518 * 100 -> UART (on CAM5200 board).
519 * 001 -> CAN1/2 on PSC2 pins.
95c44ec4 520 * Use for REV100 STK52xx boards
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521 * 01x -> Use AC97 (on FO300 board).
522 * use PSC1: Bits 29-31 (mask: 0x00000007):
523 * 100 -> UART (on all boards).
56523f12 524 */
98e69567 525#if !defined(CONFIG_SYS_GPS_PORT_CONFIG)
56523f12 526#if defined (CONFIG_MINIFAP)
6d0f6bcf 527# define CONFIG_SYS_GPS_PORT_CONFIG 0x91000004
7e6bf358 528#elif defined (CONFIG_STK52XX)
83e40ba7 529# if defined (CONFIG_STK52XX_REV100)
6d0f6bcf 530# define CONFIG_SYS_GPS_PORT_CONFIG 0x81500014
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531# else /* STK52xx REV200 and above */
532# if defined (CONFIG_TQM5200_REV100)
533# error TQM5200 REV100 not supported on STK52XX REV200 or above
534# else/* TQM5200 REV200 and above */
6d0f6bcf 535# define CONFIG_SYS_GPS_PORT_CONFIG 0x91500404
83e40ba7 536# endif
8f0b7cbe 537# endif
6d3bc9b8 538#elif defined (CONFIG_FO300)
6d0f6bcf 539# define CONFIG_SYS_GPS_PORT_CONFIG 0x91502c24
7299712c 540#elif defined (CONFIG_CAM5200)
6d0f6bcf 541# define CONFIG_SYS_GPS_PORT_CONFIG 0x8050A444
83e40ba7 542#else /* TMQ5200 Inbetriebnahme-Board */
6d0f6bcf 543# define CONFIG_SYS_GPS_PORT_CONFIG 0x81000004
56523f12 544#endif
98e69567 545#endif
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546
547/*
548 * RTC configuration
549 */
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550#if defined (CONFIG_STK52XX) && !defined (CONFIG_STK52XX_REV100)
551# define CONFIG_RTC_M41T11 1
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552# define CONFIG_SYS_I2C_RTC_ADDR 0x68
553# define CONFIG_SYS_M41T11_BASE_YEAR 1900 /* because Linux uses the same base
edd0b509 554 year */
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555#else
556# define CONFIG_RTC_MPC5200 1 /* use internal MPC5200 RTC */
557#endif
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558
559/*
560 * Miscellaneous configurable options
561 */
6d0f6bcf 562#define CONFIG_SYS_LONGHELP /* undef to save memory */
5078cce8 563
2751a95a 564#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
5078cce8 565
6d0f6bcf 566#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
2694690e 567#if defined(CONFIG_CMD_KGDB)
6d0f6bcf 568#define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
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569#endif
570
571#if defined(CONFIG_CMD_KGDB)
6d0f6bcf 572#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
56523f12 573#else
6d0f6bcf 574#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
56523f12 575#endif
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576#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
577#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
578#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
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579
580/* Enable an alternate, more extensive memory test */
6d0f6bcf 581#define CONFIG_SYS_ALT_MEMTEST
56523f12 582
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583#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
584#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
56523f12 585
6d0f6bcf 586#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
56523f12 587
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588/*
589 * Various low-level settings
590 */
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591#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
592#define CONFIG_SYS_HID0_FINAL HID0_ICE
56523f12 593
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594#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
595#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
596#ifdef CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2
597#define CONFIG_SYS_BOOTCS_CFG 0x0008DF30 /* for pci_clk = 66 MHz */
56523f12 598#else
6d0f6bcf 599#define CONFIG_SYS_BOOTCS_CFG 0x0004DF30 /* for pci_clk = 33 MHz */
56523f12 600#endif
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601#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
602#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
56523f12 603
7e6bf358 604#define CONFIG_LAST_STAGE_INIT
7e6bf358 605
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606/*
607 * SRAM - Do not map below 2 GB in address space, because this area is used
608 * for SDRAM autosizing.
609 */
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610#define CONFIG_SYS_CS2_START 0xE5000000
611#define CONFIG_SYS_CS2_SIZE 0x100000 /* 1 MByte */
612#define CONFIG_SYS_CS2_CFG 0x0004D930
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613
614/*
615 * Grafic controller - Do not map below 2 GB in address space, because this
616 * area is used for SDRAM autosizing.
617 */
8f0b7cbe 618#define SM501_FB_BASE 0xE0000000
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619#define CONFIG_SYS_CS1_START (SM501_FB_BASE)
620#define CONFIG_SYS_CS1_SIZE 0x4000000 /* 64 MByte */
621#define CONFIG_SYS_CS1_CFG 0x8F48FF70
622#define SM501_MMIO_BASE CONFIG_SYS_CS1_START + 0x03E00000
56523f12 623
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624#define CONFIG_SYS_CS_BURST 0x00000000
625#define CONFIG_SYS_CS_DEADCYCLE 0x33333311 /* 1 dead cycle for flash and SM501 */
56523f12 626
7299712c 627#if defined(CONFIG_CAM5200)
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628#define CONFIG_SYS_CS4_START 0xB0000000
629#define CONFIG_SYS_CS4_SIZE 0x00010000
630#define CONFIG_SYS_CS4_CFG 0x01019C10
7299712c 631
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632#define CONFIG_SYS_CS5_START 0xD0000000
633#define CONFIG_SYS_CS5_SIZE 0x01208000
634#define CONFIG_SYS_CS5_CFG 0x1414BF10
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635#endif
636
6d0f6bcf 637#define CONFIG_SYS_RESET_ADDRESS 0xff000000
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638
639/*-----------------------------------------------------------------------
640 * USB stuff
641 *-----------------------------------------------------------------------
642 */
643#define CONFIG_USB_CLOCK 0x0001BBBB
644#define CONFIG_USB_CONFIG 0x00001000
645
646/*-----------------------------------------------------------------------
647 * IDE/ATA stuff Supports IDE harddisk
648 *-----------------------------------------------------------------------
649 */
650
81050926 651#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
56523f12 652
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653#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
654#undef CONFIG_IDE_LED /* LED for ide not supported */
56523f12 655
81050926 656#define CONFIG_IDE_RESET /* reset for ide supported */
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657#define CONFIG_IDE_PREINIT
658
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659#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
660#define CONFIG_SYS_IDE_MAXDEVICE 2 /* max. 2 drives per IDE bus */
56523f12 661
6d0f6bcf 662#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
56523f12 663
6d0f6bcf 664#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA
56523f12 665
95c44ec4 666/* Offset for data I/O */
6d0f6bcf 667#define CONFIG_SYS_ATA_DATA_OFFSET (0x0060)
56523f12 668
95c44ec4 669/* Offset for normal register accesses */
6d0f6bcf 670#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET)
56523f12 671
95c44ec4 672/* Offset for alternate registers */
6d0f6bcf 673#define CONFIG_SYS_ATA_ALT_OFFSET (0x005C)
56523f12 674
95c44ec4 675/* Interval between registers */
6d0f6bcf 676#define CONFIG_SYS_ATA_STRIDE 4
56523f12 677
33af3e66 678/* Support ATAPI devices */
95c44ec4 679#define CONFIG_ATAPI 1
33af3e66 680
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681/*-----------------------------------------------------------------------
682 * Open firmware flat tree support
683 *-----------------------------------------------------------------------
684 */
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685#define OF_CPU "PowerPC,5200@0"
686#define OF_SOC "soc5200@f0000000"
687#define OF_TBCLK (bd->bi_busfreq / 4)
688#define OF_STDOUT_PATH "/soc5200@f0000000/serial@2000"
689
56523f12 690#endif /* __CONFIG_H */