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56523f12 1/*
69445d6c 2 * (C) Copyright 2003-2014
56523f12
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3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
45a212c4 5 * (C) Copyright 2004-2006
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6 * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
7 *
3765b3e7 8 * SPDX-License-Identifier: GPL-2.0+
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9 */
10
11#ifndef __CONFIG_H
12#define __CONFIG_H
13
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14/*
15 * High Level Configuration Options
16 * (easy to change)
17 */
18
b2a6dfe4 19#define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */
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20#define CONFIG_TQM5200 1 /* ... on TQM5200 module */
21#undef CONFIG_TQM5200_REV100 /* define for revision 100 modules */
69445d6c 22#define CONFIG_DISPLAY_BOARDINFO
56523f12 23
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24/*
25 * Valid values for CONFIG_SYS_TEXT_BASE are:
26 * 0xFC000000 boot low (standard configuration with room for
27 * max 64 MByte Flash ROM)
28 * 0xFFF00000 boot high (for a backup copy of U-Boot)
29 * 0x00100000 boot from RAM (for testing only)
30 */
31#ifndef CONFIG_SYS_TEXT_BASE
32#define CONFIG_SYS_TEXT_BASE 0xFC000000
33#endif
34
5196a7a0 35/* On a Cameron or on a FO300 board or ... */
98e69567
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36#if !defined(CONFIG_CAM5200) && !defined(CONFIG_CHARON) \
37 && !defined(CONFIG_FO300)
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38#define CONFIG_STK52XX 1 /* ... on a STK52XX board */
39#endif
40
6d0f6bcf 41#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
56523f12 42
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43#define CONFIG_HIGH_BATS 1 /* High BATs supported */
44
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45/*
46 * Serial console configuration
47 */
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48#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
49#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
6d0f6bcf 50#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
bef92e21 51#define CONFIG_BOOTCOUNT_LIMIT 1
56523f12 52
6d3bc9b8 53#ifdef CONFIG_FO300
6d0f6bcf 54#define CONFIG_SYS_DEVICE_NULLDEV 1 /* enable null device */
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55#define CONFIG_SILENT_CONSOLE 1 /* enable silent startup */
56#define CONFIG_BOARD_EARLY_INIT_F 1 /* used to detect S1 switch position */
ddde6b7c 57#define CONFIG_USB_BIN_FIXUP 1 /* for a buggy USB device */
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58#if 0
59#define FO300_SILENT_CONSOLE_WHEN_S1_CLOSED 1 /* silent console on PSC1 when S1 */
60 /* switch is closed */
61#endif
62
63#undef FO300_SILENT_CONSOLE_WHEN_S1_CLOSED /* silent console on PSC1 when S1 */
64 /* switch is open */
5196a7a0 65#endif /* CONFIG_FO300 */
6d3bc9b8 66
98e69567 67#if defined(CONFIG_CHARON) || defined(CONFIG_STK52XX)
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68#define CONFIG_PS2KBD /* AT-PS/2 Keyboard */
69#define CONFIG_PS2MULT /* .. on PS/2 Multiplexer */
70#define CONFIG_PS2SERIAL 6 /* .. on PSC6 */
6d0f6bcf 71#define CONFIG_PS2MULT_DELAY (CONFIG_SYS_HZ/2) /* Initial delay */
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72#define CONFIG_BOARD_EARLY_INIT_R
73#endif /* CONFIG_STK52XX */
56523f12 74
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75/*
76 * PCI Mapping:
77 * 0x40000000 - 0x4fffffff - PCI Memory
78 * 0x50000000 - 0x50ffffff - PCI IO Space
79 */
98e69567 80#if defined(CONFIG_CHARON) || defined(CONFIG_STK52XX)
7e6bf358 81#define CONFIG_PCI 1
56523f12 82#define CONFIG_PCI_PNP 1
31a64923 83/* #define CONFIG_PCI_SCAN_SHOW 1 */
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84
85#define CONFIG_PCI_MEM_BUS 0x40000000
86#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
87#define CONFIG_PCI_MEM_SIZE 0x10000000
88
89#define CONFIG_PCI_IO_BUS 0x50000000
90#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
91#define CONFIG_PCI_IO_SIZE 0x01000000
92
cd65a3dc 93#define CONFIG_EEPRO100 1
6d0f6bcf 94#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
56523f12 95#define CONFIG_NS8382X 1
83e40ba7 96#endif /* CONFIG_STK52XX */
56523f12 97
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98/*
99 * Video console
100 */
5078cce8 101#ifndef CONFIG_TQM5200S /* No graphics controller on TQM5200S */
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102#define CONFIG_VIDEO
103#define CONFIG_VIDEO_SM501
104#define CONFIG_VIDEO_SM501_32BPP
105#define CONFIG_CFB_CONSOLE
106#define CONFIG_VIDEO_LOGO
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107
108#ifndef CONFIG_FO300
8f0b7cbe 109#define CONFIG_CONSOLE_EXTRA_INFO
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110#else
111#define CONFIG_VIDEO_BMP_LOGO
112#endif
113
114#define CONFIG_VGA_AS_SINGLE_DEVICE
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115#define CONFIG_VIDEO_SW_CURSOR
116#define CONFIG_SPLASH_SCREEN
6d0f6bcf 117#define CONFIG_SYS_CONSOLE_IS_IN_ENV
6d3bc9b8 118#endif /* #ifndef CONFIG_TQM5200S */
56523f12 119
56523f12 120/* Partitions */
89c02e2c 121#define CONFIG_MAC_PARTITION
56523f12 122#define CONFIG_DOS_PARTITION
8f0b7cbe 123#define CONFIG_ISO_PARTITION
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124
125/* USB */
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126#if defined(CONFIG_CHARON) || defined(CONFIG_FO300) || \
127 defined(CONFIG_STK52XX)
7b59b3c7 128#define CONFIG_USB_OHCI_NEW
6d0f6bcf 129#define CONFIG_SYS_OHCI_BE_CONTROLLER
56523f12 130#define CONFIG_USB_STORAGE
afaac86f 131#define CONFIG_CMD_FAT
53e336e9 132
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133#undef CONFIG_SYS_USB_OHCI_BOARD_INIT
134#define CONFIG_SYS_USB_OHCI_CPU_INIT
135#define CONFIG_SYS_USB_OHCI_REGS_BASE MPC5XXX_USB
136#define CONFIG_SYS_USB_OHCI_SLOT_NAME "mpc5200"
137#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
53e336e9 138
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139#endif
140
135ae006 141#ifndef CONFIG_CAM5200
56523f12 142/* POST support */
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143#define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \
144 CONFIG_SYS_POST_CPU | \
145 CONFIG_SYS_POST_I2C)
5078cce8 146#endif
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147
148#ifdef CONFIG_POST
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149/* preserve space for the post_word at end of on-chip SRAM */
150#define MPC5XXX_SRAM_POST_SIZE MPC5XXX_SRAM_SIZE-4
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151#endif
152
56523f12 153/*
a1aa0bb5 154 * BOOTP options
56523f12 155 */
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156#define CONFIG_BOOTP_BOOTFILESIZE
157#define CONFIG_BOOTP_BOOTPATH
158#define CONFIG_BOOTP_GATEWAY
159#define CONFIG_BOOTP_HOSTNAME
160
56523f12 161/*
2694690e 162 * Command line configuration.
56523f12 163 */
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164#define CONFIG_CMD_ASKENV
165#define CONFIG_CMD_DATE
2694690e 166#define CONFIG_CMD_EEPROM
2694690e
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167#define CONFIG_CMD_JFFS2
168#define CONFIG_CMD_MII
2694690e 169#define CONFIG_CMD_REGINFO
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170#define CONFIG_CMD_BSP
171
172#ifdef CONFIG_VIDEO
173 #define CONFIG_CMD_BMP
174#endif
175
176#ifdef CONFIG_PCI
2b2a587d 177#define CONFIG_CMD_PCI
f33fca22 178#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
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179#endif
180
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181#if defined(CONFIG_CHARON) || defined(CONFIG_FO300) || \
182 defined(CONFIG_MINIFAP) || defined(CONFIG_STK52XX)
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183 #define CONFIG_CMD_IDE
184 #define CONFIG_CMD_FAT
185 #define CONFIG_CMD_EXT2
186#endif
187
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188#if defined(CONFIG_CHARON) || defined(CONFIG_FO300) || \
189 defined(CONFIG_STK52XX)
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190 #define CONFIG_CFG_USB
191 #define CONFIG_CFG_FAT
192#endif
193
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194#ifdef CONFIG_POST
195 #define CONFIG_CMD_DIAG
196#endif
197
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198#define CONFIG_TIMESTAMP /* display image timestamps */
199
14d0a02a 200#if (CONFIG_SYS_TEXT_BASE != 0xFFF00000)
6d0f6bcf 201# define CONFIG_SYS_LOWBOOT 1 /* Boot low */
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202#endif
203
204/*
205 * Autobooting
206 */
207#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
208
81050926 209#define CONFIG_PREBOOT "echo;" \
4c4aca81 210 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
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211 "echo"
212
213#undef CONFIG_BOOTARGS
214
6d0f6bcf 215#if defined(CONFIG_TQM5200_B) && !defined(CONFIG_SYS_LOWBOOT)
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216# define ENV_UPDT \
217 "update=protect off FFF00000 +${filesize};" \
218 "erase FFF00000 +${filesize};" \
5078cce8 219 "cp.b 200000 FFF00000 ${filesize};" \
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220 "protect on FFF00000 +${filesize}\0"
221#else /* default lowboot configuration */
6d3bc9b8 222# define ENV_UPDT \
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223 "update=protect off FC000000 +${filesize};" \
224 "erase FC000000 +${filesize};" \
6d3bc9b8 225 "cp.b 200000 FC000000 ${filesize};" \
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226 "protect on FC000000 +${filesize}\0"
227#endif
5078cce8 228
e1f601b5 229#if defined(CONFIG_TQM5200)
6abaee42 230#define CUSTOM_ENV_SETTINGS \
e1f601b5 231 "hostname=tqm5200\0" \
6abaee42 232 "bootfile=/tftpboot/tqm5200/uImage\0" \
8f8416fa 233 "fdt_file=/tftpboot/tqm5200/tqm5200.dtb\0" \
6abaee42 234 "u-boot=/tftpboot/tqm5200/u-boot.bin\0"
e1f601b5 235#elif defined(CONFIG_CAM5200)
1636d1c8 236#define CUSTOM_ENV_SETTINGS \
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237 "bootfile=cam5200/uImage\0" \
238 "u-boot=cam5200/u-boot.bin\0" \
74de7aef 239 "setup=tftp 200000 cam5200/setup.img; source 200000\0"
6abaee42
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240#endif
241
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242#if defined(CONFIG_TQM5200_B)
243#define ENV_FLASH_LAYOUT \
244 "fdt_addr=FC100000\0" \
245 "kernel_addr=FC140000\0" \
246 "ramdisk_addr=FC600000\0"
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247#elif defined(CONFIG_CHARON)
248#define ENV_FLASH_LAYOUT \
249 "fdt_addr=FDFC0000\0" \
250 "kernel_addr=FC0A0000\0" \
251 "ramdisk_addr=FC200000\0"
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252#else /* !CONFIG_TQM5200_B */
253#define ENV_FLASH_LAYOUT \
254 "fdt_addr=FC0A0000\0" \
255 "kernel_addr=FC0C0000\0" \
256 "ramdisk_addr=FC300000\0"
257#endif
258
81050926 259#define CONFIG_EXTRA_ENV_SETTINGS \
56523f12 260 "netdev=eth0\0" \
e1f601b5 261 "console=ttyPSC0\0" \
a5cc5555 262 ENV_FLASH_LAYOUT \
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263 "kernel_addr_r=400000\0" \
264 "fdt_addr_r=600000\0" \
89c02e2c 265 "rootpath=/opt/eldk/ppc_6xx\0" \
56523f12 266 "ramargs=setenv bootargs root=/dev/ram rw\0" \
56523f12 267 "nfsargs=setenv bootargs root=/dev/nfs rw " \
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268 "nfsroot=${serverip}:${rootpath}\0" \
269 "addip=setenv bootargs ${bootargs} " \
270 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
271 ":${hostname}:${netdev}:off panic=1\0" \
5078cce8 272 "addcons=setenv bootargs ${bootargs} " \
8f8416fa 273 "console=${console},${baudrate}\0" \
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274 "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
275 "flash_self_old=sete console ttyS0; " \
276 "run ramargs addip addcons addmtd; " \
fe126d8b 277 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
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278 "flash_self=run ramargs addip addcons;" \
279 "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
280 "flash_nfs_old=sete console ttyS0; run nfsargs addip addcons;" \
fe126d8b 281 "bootm ${kernel_addr}\0" \
e1f601b5 282 "flash_nfs=run nfsargs addip addcons;" \
8f8416fa 283 "bootm ${kernel_addr} - ${fdt_addr}\0" \
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284 "net_nfs_old=tftp ${kernel_addr_r} ${bootfile};" \
285 "sete console ttyS0; run nfsargs addip addcons;bootm\0" \
286 "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \
287 "tftp ${fdt_addr_r} ${fdt_file}; " \
98e69567 288 "run nfsargs addip addcons addmtd; " \
e1f601b5 289 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
6abaee42 290 CUSTOM_ENV_SETTINGS \
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291 "load=tftp 200000 ${u-boot}\0" \
292 ENV_UPDT \
7e6bf358 293 ""
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294
295#define CONFIG_BOOTCOMMAND "run net_nfs"
296
297/*
298 * IPB Bus clocking configuration.
299 */
6d0f6bcf 300#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
56523f12 301
6d0f6bcf 302#if defined(CONFIG_SYS_IPBCLK_EQUALS_XLBCLK) && !defined(CONFIG_CAM5200)
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303/*
304 * PCI Bus clocking configuration
305 *
306 * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if
6d0f6bcf 307 * CONFIG_SYS_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock of
c99512d6 308 * 66 MHz yet hasn't been tested with a IPB Bus Clock of 66 MHz.
56523f12 309 */
6d0f6bcf 310#define CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2 /* define for 66MHz speed */
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311#endif
312
313/*
314 * I2C configuration
315 */
316#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
8f0b7cbe 317#ifdef CONFIG_TQM5200_REV100
6d0f6bcf 318#define CONFIG_SYS_I2C_MODULE 1 /* Select I2C module #1 for rev. 100 board */
56523f12 319#else
6d0f6bcf 320#define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #2 for all other revs */
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321#endif
322
323/*
324 * I2C clock frequency
325 *
326 * Please notice, that the resulting clock frequency could differ from the
327 * configured value. This is because the I2C clock is derived from system
a187559e 328 * clock over a frequency divider with only a few divider values. U-Boot
6d0f6bcf 329 * calculates the best approximation for CONFIG_SYS_I2C_SPEED. However the calculated
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330 * approximation allways lies below the configured value, never above.
331 */
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JCPV
332#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */
333#define CONFIG_SYS_I2C_SLAVE 0x7F
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334
335/*
336 * EEPROM configuration for onboard EEPROM M24C32 (M24C64 should work
337 * also). For other EEPROMs configuration should be verified. On Mini-FAP the
338 * EEPROM (24C64) is on the same I2C address (but on other I2C bus), so the
339 * same configuration could be used.
340 */
6d0f6bcf
JCPV
341#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */
342#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
343#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* =32 Bytes per write */
344#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20
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345
346/*
347 * HW-Monitor configuration on Mini-FAP
348 */
349#if defined (CONFIG_MINIFAP)
6d0f6bcf 350#define CONFIG_SYS_I2C_HWMON_ADDR 0x2C
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351#endif
352
353/* List of I2C addresses to be verified by POST */
56523f12 354#if defined (CONFIG_MINIFAP)
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355#undef CONFIG_SYS_POST_I2C_ADDRS
356#define CONFIG_SYS_POST_I2C_ADDRS {CONFIG_SYS_I2C_EEPROM_ADDR, \
357 CONFIG_SYS_I2C_HWMON_ADDR, \
358 CONFIG_SYS_I2C_SLAVE}
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359#endif
360
361/*
362 * Flash configuration
363 */
6d0f6bcf 364#define CONFIG_SYS_FLASH_BASE 0xFC000000
56523f12 365
d9384de2 366#if defined(CONFIG_CAM5200) && defined(CONFIG_CAM5200_NIOSFLASH)
6d0f6bcf 367#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max num of flash banks
7299712c 368 (= chip selects) */
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369#define CONFIG_SYS_FLASH_WORD_SIZE unsigned int /* main flash device with */
370#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
371#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
372
373#define CONFIG_SYS_FLASH_ADDR0 0x555
374#define CONFIG_SYS_FLASH_ADDR1 0x2AA
375#define CONFIG_SYS_FLASH_2ND_16BIT_DEV 1 /* NIOS flash is a 16bit device */
376#define CONFIG_SYS_MAX_FLASH_SECT 128
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377#else
378/* use CFI flash driver */
6d0f6bcf 379#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
00b1883a 380#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
085ecde1 381#define CONFIG_FLASH_CFI_MTD /* with MTD support */
6d0f6bcf
JCPV
382#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_BOOTCS_START }
383#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks
d9384de2 384 (= chip selects) */
6d0f6bcf 385#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */
d9384de2 386#endif
7299712c 387
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388#define CONFIG_SYS_FLASH_EMPTY_INFO
389#define CONFIG_SYS_FLASH_SIZE 0x04000000 /* 64 MByte */
390#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
56523f12 391
135ae006 392#if defined (CONFIG_CAM5200)
6d0f6bcf 393# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00040000)
5078cce8 394#elif defined(CONFIG_TQM5200_B)
6d0f6bcf 395# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00080000)
45a212c4 396#else
6d0f6bcf 397# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00060000)
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398#endif
399
d534f5cc 400/* Dynamic MTD partition support */
68d7d651 401#define CONFIG_CMD_MTDPARTS
942556a9 402#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
259bff7c 403#define MTDIDS_DEFAULT "nor0=fc000000.flash"
5078cce8 404
5624d66a 405#if defined(CONFIG_STK52XX)
5078cce8 406# if defined(CONFIG_TQM5200_B)
6d0f6bcf 407# if defined(CONFIG_SYS_LOWBOOT)
259bff7c 408# define MTDPARTS_DEFAULT "mtdparts=fc000000.flash:1m(firmware)," \
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409 "256k(dtb)," \
410 "2304k(kernel)," \
411 "2560k(small-fs)," \
45a212c4 412 "2m(initrd)," \
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413 "8m(misc)," \
414 "16m(big-fs)"
415# else /* highboot */
259bff7c 416# define MTDPARTS_DEFAULT "mtdparts=fc000000.flash:2560k(kernel),"\
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417 "3584k(small-fs)," \
418 "2m(initrd)," \
419 "8m(misc)," \
420 "15m(big-fs)," \
421 "1m(firmware)"
6d0f6bcf 422# endif /* CONFIG_SYS_LOWBOOT */
5078cce8 423# else /* !CONFIG_TQM5200_B */
259bff7c 424# define MTDPARTS_DEFAULT "mtdparts=fc000000.flash:640k(firmware),"\
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425 "128k(dtb)," \
426 "2304k(kernel)," \
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427 "2m(initrd)," \
428 "4m(small-fs)," \
5078cce8 429 "8m(misc)," \
e1f601b5 430 "15m(big-fs)"
5078cce8 431# endif /* CONFIG_TQM5200_B */
135ae006 432#elif defined (CONFIG_CAM5200)
259bff7c 433# define MTDPARTS_DEFAULT "mtdparts=fc000000.flash:768k(firmware),"\
5078cce8 434 "1792k(kernel)," \
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435 "5632k(rootfs)," \
436 "24m(home)"
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HS
437#elif defined (CONFIG_CHARON)
438# define MTDPARTS_DEFAULT "mtdparts=fc000000.flash:640k(firmware),"\
439 "1408k(kernel)," \
440 "2m(initrd)," \
441 "4m(small-fs)," \
442 "24320k(big-fs)," \
443 "256k(dts)"
6d3bc9b8 444#elif defined (CONFIG_FO300)
259bff7c 445# define MTDPARTS_DEFAULT "mtdparts=fc000000.flash:640k(firmware),"\
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446 "1408k(kernel)," \
447 "2m(initrd)," \
448 "4m(small-fs)," \
449 "8m(misc)," \
450 "16m(big-fs)"
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451#else
452# error "Unknown Carrier Board"
453#endif /* CONFIG_STK52XX */
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454
455/*
456 * Environment settings
457 */
5a1aceb0 458#define CONFIG_ENV_IS_IN_FLASH 1
0e8d1586 459#define CONFIG_ENV_SIZE 0x4000 /* 16 k - keep small for fast booting */
78d620eb 460#if defined(CONFIG_TQM5200_B) || defined (CONFIG_CAM5200)
0e8d1586 461#define CONFIG_ENV_SECT_SIZE 0x40000
45a212c4 462#else
0e8d1586 463#define CONFIG_ENV_SECT_SIZE 0x20000
5078cce8 464#endif /* CONFIG_TQM5200_B */
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465#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
466#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
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467
468/*
469 * Memory map
470 */
6d0f6bcf
JCPV
471#define CONFIG_SYS_MBAR 0xF0000000
472#define CONFIG_SYS_SDRAM_BASE 0x00000000
473#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
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474
475/* Use ON-Chip SRAM until RAM will be available */
6d0f6bcf 476#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
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477#ifdef CONFIG_POST
478/* preserve space for the post_word at end of on-chip SRAM */
553f0982 479#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_POST_SIZE
56523f12 480#else
553f0982 481#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE
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482#endif
483
25ddd1fb 484#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
6d0f6bcf 485#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
56523f12 486
14d0a02a 487#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
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488#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
489# define CONFIG_SYS_RAMBOOT 1
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490#endif
491
135ae006 492#if defined (CONFIG_CAM5200)
6d0f6bcf 493# define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
5078cce8 494#elif defined(CONFIG_TQM5200_B)
6d0f6bcf 495# define CONFIG_SYS_MONITOR_LEN (512 << 10) /* Reserve 512 kB for Monitor */
45a212c4 496#else
6d0f6bcf 497# define CONFIG_SYS_MONITOR_LEN (384 << 10) /* Reserve 384 kB for Monitor */
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498#endif
499
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500#define CONFIG_SYS_MALLOC_LEN (1024 << 10) /* Reserve 1024 kB for malloc() */
501#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
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502
503/*
504 * Ethernet configuration
505 */
506#define CONFIG_MPC5xxx_FEC 1
86321fc1 507#define CONFIG_MPC5xxx_FEC_MII100
56523f12 508/*
86321fc1 509 * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb
56523f12 510 */
86321fc1 511/* #define CONFIG_MPC5xxx_FEC_MII10 */
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512#define CONFIG_PHY_ADDR 0x00
513
514/*
515 * GPIO configuration
516 *
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517 * use CS1: Bit 0 (mask: 0x80000000):
518 * 1 -> Pin gpio_wkup_6 as second SDRAM chip select (mem_cs1).
56523f12 519 * use ALT CAN position: Bits 2-3 (mask: 0x30000000):
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520 * 00 -> No Alternatives, CAN1/2 on PSC2 according to PSC2 setting.
521 * SPI on PSC3 according to PSC3 setting. Use for CAM5200.
522 * 01 -> CAN1 on I2C1, CAN2 on Tmr0/1.
523 * Use for REV200 STK52XX boards and FO300 boards. Do not use
524 * with REV100 modules (because, there I2C1 is used as I2C bus).
525 * use ATA: Bits 6-7 (mask 0x03000000):
526 * 00 -> No ATA chip selects, csb_4/5 used as normal chip selects.
527 * Use for CAM5200 board.
528 * 01 -> ATA cs0/1 on csb_4/5. Use for the remaining boards.
529 * use PSC6: Bits 9-11 (mask 0x00700000):
530 * 000 -> use PSC6_0 to PSC6_3 as GPIO, PSC6 could not be used as
531 * UART, CODEC or IrDA.
532 * GPIO on PSC6_3 is used in post_hotkeys_pressed() to
533 * enable extended POST tests.
534 * Use for MINI-FAP and TQM5200_IB boards.
535 * 101 -> use PSC6 as UART. Pins PSC6_0 to PSC6_3 are used.
536 * Extended POST test is not available.
537 * Use for STK52xx, FO300 and CAM5200 boards.
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538 * WARNING: When the extended POST is enabled, these bits will
539 * be overridden by this code as GPIOs!
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540 * use PCI_DIS: Bit 16 (mask 0x00008000):
541 * 1 -> disable PCI controller (on CAM5200 board).
542 * use USB: Bits 18-19 (mask 0x00003000):
543 * 10 -> two UARTs (on FO300 and CAM5200).
544 * use PSC3: Bits 20-23 (mask: 0x00000f00):
545 * 0000 -> All PSC3 pins are GPIOs.
546 * 1100 -> UART/SPI (on FO300 board).
547 * 0100 -> UART (on CAM5200 board).
548 * use PSC2: Bits 25:27 (mask: 0x00000030):
549 * 000 -> All PSC2 pins are GPIOs.
550 * 100 -> UART (on CAM5200 board).
551 * 001 -> CAN1/2 on PSC2 pins.
95c44ec4 552 * Use for REV100 STK52xx boards
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553 * 01x -> Use AC97 (on FO300 board).
554 * use PSC1: Bits 29-31 (mask: 0x00000007):
555 * 100 -> UART (on all boards).
56523f12 556 */
98e69567 557#if !defined(CONFIG_SYS_GPS_PORT_CONFIG)
56523f12 558#if defined (CONFIG_MINIFAP)
6d0f6bcf 559# define CONFIG_SYS_GPS_PORT_CONFIG 0x91000004
7e6bf358 560#elif defined (CONFIG_STK52XX)
83e40ba7 561# if defined (CONFIG_STK52XX_REV100)
6d0f6bcf 562# define CONFIG_SYS_GPS_PORT_CONFIG 0x81500014
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563# else /* STK52xx REV200 and above */
564# if defined (CONFIG_TQM5200_REV100)
565# error TQM5200 REV100 not supported on STK52XX REV200 or above
566# else/* TQM5200 REV200 and above */
6d0f6bcf 567# define CONFIG_SYS_GPS_PORT_CONFIG 0x91500404
83e40ba7 568# endif
8f0b7cbe 569# endif
6d3bc9b8 570#elif defined (CONFIG_FO300)
6d0f6bcf 571# define CONFIG_SYS_GPS_PORT_CONFIG 0x91502c24
7299712c 572#elif defined (CONFIG_CAM5200)
6d0f6bcf 573# define CONFIG_SYS_GPS_PORT_CONFIG 0x8050A444
83e40ba7 574#else /* TMQ5200 Inbetriebnahme-Board */
6d0f6bcf 575# define CONFIG_SYS_GPS_PORT_CONFIG 0x81000004
56523f12 576#endif
98e69567 577#endif
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578
579/*
580 * RTC configuration
581 */
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582#if defined (CONFIG_STK52XX) && !defined (CONFIG_STK52XX_REV100)
583# define CONFIG_RTC_M41T11 1
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584# define CONFIG_SYS_I2C_RTC_ADDR 0x68
585# define CONFIG_SYS_M41T11_BASE_YEAR 1900 /* because Linux uses the same base
edd0b509 586 year */
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587#else
588# define CONFIG_RTC_MPC5200 1 /* use internal MPC5200 RTC */
589#endif
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590
591/*
592 * Miscellaneous configurable options
593 */
6d0f6bcf 594#define CONFIG_SYS_LONGHELP /* undef to save memory */
5078cce8 595
2751a95a 596#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
5078cce8 597
6d0f6bcf 598#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
2694690e 599#if defined(CONFIG_CMD_KGDB)
6d0f6bcf 600#define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
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601#endif
602
603#if defined(CONFIG_CMD_KGDB)
6d0f6bcf 604#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
56523f12 605#else
6d0f6bcf 606#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
56523f12 607#endif
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608#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
609#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
610#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
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611
612/* Enable an alternate, more extensive memory test */
6d0f6bcf 613#define CONFIG_SYS_ALT_MEMTEST
56523f12 614
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615#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
616#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
56523f12 617
6d0f6bcf 618#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
56523f12 619
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620/*
621 * Various low-level settings
622 */
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623#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
624#define CONFIG_SYS_HID0_FINAL HID0_ICE
56523f12 625
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626#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
627#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
628#ifdef CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2
629#define CONFIG_SYS_BOOTCS_CFG 0x0008DF30 /* for pci_clk = 66 MHz */
56523f12 630#else
6d0f6bcf 631#define CONFIG_SYS_BOOTCS_CFG 0x0004DF30 /* for pci_clk = 33 MHz */
56523f12 632#endif
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633#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
634#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
56523f12 635
7e6bf358 636#define CONFIG_LAST_STAGE_INIT
7e6bf358 637
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638/*
639 * SRAM - Do not map below 2 GB in address space, because this area is used
640 * for SDRAM autosizing.
641 */
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642#define CONFIG_SYS_CS2_START 0xE5000000
643#define CONFIG_SYS_CS2_SIZE 0x100000 /* 1 MByte */
644#define CONFIG_SYS_CS2_CFG 0x0004D930
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645
646/*
647 * Grafic controller - Do not map below 2 GB in address space, because this
648 * area is used for SDRAM autosizing.
649 */
8f0b7cbe 650#define SM501_FB_BASE 0xE0000000
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651#define CONFIG_SYS_CS1_START (SM501_FB_BASE)
652#define CONFIG_SYS_CS1_SIZE 0x4000000 /* 64 MByte */
653#define CONFIG_SYS_CS1_CFG 0x8F48FF70
654#define SM501_MMIO_BASE CONFIG_SYS_CS1_START + 0x03E00000
56523f12 655
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656#define CONFIG_SYS_CS_BURST 0x00000000
657#define CONFIG_SYS_CS_DEADCYCLE 0x33333311 /* 1 dead cycle for flash and SM501 */
56523f12 658
7299712c 659#if defined(CONFIG_CAM5200)
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660#define CONFIG_SYS_CS4_START 0xB0000000
661#define CONFIG_SYS_CS4_SIZE 0x00010000
662#define CONFIG_SYS_CS4_CFG 0x01019C10
7299712c 663
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664#define CONFIG_SYS_CS5_START 0xD0000000
665#define CONFIG_SYS_CS5_SIZE 0x01208000
666#define CONFIG_SYS_CS5_CFG 0x1414BF10
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667#endif
668
6d0f6bcf 669#define CONFIG_SYS_RESET_ADDRESS 0xff000000
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670
671/*-----------------------------------------------------------------------
672 * USB stuff
673 *-----------------------------------------------------------------------
674 */
675#define CONFIG_USB_CLOCK 0x0001BBBB
676#define CONFIG_USB_CONFIG 0x00001000
677
678/*-----------------------------------------------------------------------
679 * IDE/ATA stuff Supports IDE harddisk
680 *-----------------------------------------------------------------------
681 */
682
81050926 683#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
56523f12 684
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685#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
686#undef CONFIG_IDE_LED /* LED for ide not supported */
56523f12 687
81050926 688#define CONFIG_IDE_RESET /* reset for ide supported */
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689#define CONFIG_IDE_PREINIT
690
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691#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
692#define CONFIG_SYS_IDE_MAXDEVICE 2 /* max. 2 drives per IDE bus */
56523f12 693
6d0f6bcf 694#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
56523f12 695
6d0f6bcf 696#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA
56523f12 697
95c44ec4 698/* Offset for data I/O */
6d0f6bcf 699#define CONFIG_SYS_ATA_DATA_OFFSET (0x0060)
56523f12 700
95c44ec4 701/* Offset for normal register accesses */
6d0f6bcf 702#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET)
56523f12 703
95c44ec4 704/* Offset for alternate registers */
6d0f6bcf 705#define CONFIG_SYS_ATA_ALT_OFFSET (0x005C)
56523f12 706
95c44ec4 707/* Interval between registers */
6d0f6bcf 708#define CONFIG_SYS_ATA_STRIDE 4
56523f12 709
33af3e66 710/* Support ATAPI devices */
95c44ec4 711#define CONFIG_ATAPI 1
33af3e66 712
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713/*-----------------------------------------------------------------------
714 * Open firmware flat tree support
715 *-----------------------------------------------------------------------
716 */
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717#define OF_CPU "PowerPC,5200@0"
718#define OF_SOC "soc5200@f0000000"
719#define OF_TBCLK (bd->bi_busfreq / 4)
720#define OF_STDOUT_PATH "/soc5200@f0000000/serial@2000"
721
56523f12 722#endif /* __CONFIG_H */