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Commit | Line | Data |
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56523f12 | 1 | /* |
69445d6c | 2 | * (C) Copyright 2003-2014 |
56523f12 WD |
3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
4 | * | |
45a212c4 | 5 | * (C) Copyright 2004-2006 |
56523f12 WD |
6 | * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de |
7 | * | |
3765b3e7 | 8 | * SPDX-License-Identifier: GPL-2.0+ |
56523f12 WD |
9 | */ |
10 | ||
11 | #ifndef __CONFIG_H | |
12 | #define __CONFIG_H | |
13 | ||
56523f12 WD |
14 | /* |
15 | * High Level Configuration Options | |
16 | * (easy to change) | |
17 | */ | |
18 | ||
b2a6dfe4 | 19 | #define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */ |
5078cce8 WD |
20 | #define CONFIG_TQM5200 1 /* ... on TQM5200 module */ |
21 | #undef CONFIG_TQM5200_REV100 /* define for revision 100 modules */ | |
56523f12 | 22 | |
2ae18241 WD |
23 | /* |
24 | * Valid values for CONFIG_SYS_TEXT_BASE are: | |
25 | * 0xFC000000 boot low (standard configuration with room for | |
26 | * max 64 MByte Flash ROM) | |
27 | * 0xFFF00000 boot high (for a backup copy of U-Boot) | |
28 | * 0x00100000 boot from RAM (for testing only) | |
29 | */ | |
30 | #ifndef CONFIG_SYS_TEXT_BASE | |
31 | #define CONFIG_SYS_TEXT_BASE 0xFC000000 | |
32 | #endif | |
33 | ||
5196a7a0 | 34 | /* On a Cameron or on a FO300 board or ... */ |
98e69567 HS |
35 | #if !defined(CONFIG_CAM5200) && !defined(CONFIG_CHARON) \ |
36 | && !defined(CONFIG_FO300) | |
5078cce8 WD |
37 | #define CONFIG_STK52XX 1 /* ... on a STK52XX board */ |
38 | #endif | |
39 | ||
6d0f6bcf | 40 | #define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */ |
56523f12 | 41 | |
31d82672 BB |
42 | #define CONFIG_HIGH_BATS 1 /* High BATs supported */ |
43 | ||
56523f12 WD |
44 | /* |
45 | * Serial console configuration | |
46 | */ | |
5078cce8 WD |
47 | #define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ |
48 | #define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */ | |
6d0f6bcf | 49 | #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } |
bef92e21 | 50 | #define CONFIG_BOOTCOUNT_LIMIT 1 |
56523f12 | 51 | |
6d3bc9b8 | 52 | #ifdef CONFIG_FO300 |
6d0f6bcf | 53 | #define CONFIG_SYS_DEVICE_NULLDEV 1 /* enable null device */ |
6d3bc9b8 | 54 | #define CONFIG_BOARD_EARLY_INIT_F 1 /* used to detect S1 switch position */ |
ddde6b7c | 55 | #define CONFIG_USB_BIN_FIXUP 1 /* for a buggy USB device */ |
6d3bc9b8 MB |
56 | #if 0 |
57 | #define FO300_SILENT_CONSOLE_WHEN_S1_CLOSED 1 /* silent console on PSC1 when S1 */ | |
58 | /* switch is closed */ | |
59 | #endif | |
60 | ||
61 | #undef FO300_SILENT_CONSOLE_WHEN_S1_CLOSED /* silent console on PSC1 when S1 */ | |
62 | /* switch is open */ | |
5196a7a0 | 63 | #endif /* CONFIG_FO300 */ |
6d3bc9b8 | 64 | |
98e69567 | 65 | #if defined(CONFIG_CHARON) || defined(CONFIG_STK52XX) |
7e6bf358 WD |
66 | #define CONFIG_PS2KBD /* AT-PS/2 Keyboard */ |
67 | #define CONFIG_PS2MULT /* .. on PS/2 Multiplexer */ | |
68 | #define CONFIG_PS2SERIAL 6 /* .. on PSC6 */ | |
6d0f6bcf | 69 | #define CONFIG_PS2MULT_DELAY (CONFIG_SYS_HZ/2) /* Initial delay */ |
7e6bf358 WD |
70 | #define CONFIG_BOARD_EARLY_INIT_R |
71 | #endif /* CONFIG_STK52XX */ | |
56523f12 | 72 | |
56523f12 WD |
73 | /* |
74 | * PCI Mapping: | |
75 | * 0x40000000 - 0x4fffffff - PCI Memory | |
76 | * 0x50000000 - 0x50ffffff - PCI IO Space | |
77 | */ | |
98e69567 | 78 | #if defined(CONFIG_CHARON) || defined(CONFIG_STK52XX) |
7e6bf358 | 79 | #define CONFIG_PCI 1 |
56523f12 | 80 | #define CONFIG_PCI_PNP 1 |
31a64923 | 81 | /* #define CONFIG_PCI_SCAN_SHOW 1 */ |
56523f12 WD |
82 | |
83 | #define CONFIG_PCI_MEM_BUS 0x40000000 | |
84 | #define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS | |
85 | #define CONFIG_PCI_MEM_SIZE 0x10000000 | |
86 | ||
87 | #define CONFIG_PCI_IO_BUS 0x50000000 | |
88 | #define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS | |
89 | #define CONFIG_PCI_IO_SIZE 0x01000000 | |
90 | ||
cd65a3dc | 91 | #define CONFIG_EEPRO100 1 |
6d0f6bcf | 92 | #define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ |
56523f12 | 93 | #define CONFIG_NS8382X 1 |
83e40ba7 | 94 | #endif /* CONFIG_STK52XX */ |
56523f12 | 95 | |
8f0b7cbe WD |
96 | /* |
97 | * Video console | |
98 | */ | |
5078cce8 | 99 | #ifndef CONFIG_TQM5200S /* No graphics controller on TQM5200S */ |
8f0b7cbe WD |
100 | #define CONFIG_VIDEO_SM501 |
101 | #define CONFIG_VIDEO_SM501_32BPP | |
102 | #define CONFIG_CFB_CONSOLE | |
103 | #define CONFIG_VIDEO_LOGO | |
6d3bc9b8 MB |
104 | |
105 | #ifndef CONFIG_FO300 | |
8f0b7cbe | 106 | #define CONFIG_CONSOLE_EXTRA_INFO |
6d3bc9b8 MB |
107 | #else |
108 | #define CONFIG_VIDEO_BMP_LOGO | |
109 | #endif | |
110 | ||
111 | #define CONFIG_VGA_AS_SINGLE_DEVICE | |
8f0b7cbe WD |
112 | #define CONFIG_VIDEO_SW_CURSOR |
113 | #define CONFIG_SPLASH_SCREEN | |
6d3bc9b8 | 114 | #endif /* #ifndef CONFIG_TQM5200S */ |
56523f12 | 115 | |
56523f12 | 116 | /* Partitions */ |
89c02e2c | 117 | #define CONFIG_MAC_PARTITION |
56523f12 | 118 | #define CONFIG_DOS_PARTITION |
8f0b7cbe | 119 | #define CONFIG_ISO_PARTITION |
56523f12 WD |
120 | |
121 | /* USB */ | |
98e69567 HS |
122 | #if defined(CONFIG_CHARON) || defined(CONFIG_FO300) || \ |
123 | defined(CONFIG_STK52XX) | |
7b59b3c7 | 124 | #define CONFIG_USB_OHCI_NEW |
6d0f6bcf | 125 | #define CONFIG_SYS_OHCI_BE_CONTROLLER |
53e336e9 | 126 | |
6d0f6bcf JCPV |
127 | #undef CONFIG_SYS_USB_OHCI_BOARD_INIT |
128 | #define CONFIG_SYS_USB_OHCI_CPU_INIT | |
129 | #define CONFIG_SYS_USB_OHCI_REGS_BASE MPC5XXX_USB | |
130 | #define CONFIG_SYS_USB_OHCI_SLOT_NAME "mpc5200" | |
131 | #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15 | |
53e336e9 | 132 | |
56523f12 WD |
133 | #endif |
134 | ||
135ae006 | 135 | #ifndef CONFIG_CAM5200 |
56523f12 | 136 | /* POST support */ |
6d0f6bcf JCPV |
137 | #define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \ |
138 | CONFIG_SYS_POST_CPU | \ | |
139 | CONFIG_SYS_POST_I2C) | |
5078cce8 | 140 | #endif |
56523f12 WD |
141 | |
142 | #ifdef CONFIG_POST | |
56523f12 WD |
143 | /* preserve space for the post_word at end of on-chip SRAM */ |
144 | #define MPC5XXX_SRAM_POST_SIZE MPC5XXX_SRAM_SIZE-4 | |
56523f12 WD |
145 | #endif |
146 | ||
56523f12 | 147 | /* |
a1aa0bb5 | 148 | * BOOTP options |
56523f12 | 149 | */ |
a1aa0bb5 JL |
150 | #define CONFIG_BOOTP_BOOTFILESIZE |
151 | #define CONFIG_BOOTP_BOOTPATH | |
152 | #define CONFIG_BOOTP_GATEWAY | |
153 | #define CONFIG_BOOTP_HOSTNAME | |
154 | ||
56523f12 | 155 | /* |
2694690e | 156 | * Command line configuration. |
56523f12 | 157 | */ |
2694690e | 158 | #define CONFIG_CMD_DATE |
2694690e | 159 | #define CONFIG_CMD_EEPROM |
2694690e | 160 | #define CONFIG_CMD_JFFS2 |
2694690e | 161 | #define CONFIG_CMD_REGINFO |
2694690e JL |
162 | #define CONFIG_CMD_BSP |
163 | ||
164 | #ifdef CONFIG_VIDEO | |
165 | #define CONFIG_CMD_BMP | |
166 | #endif | |
167 | ||
168 | #ifdef CONFIG_PCI | |
2b2a587d | 169 | #define CONFIG_CMD_PCI |
f33fca22 | 170 | #define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1 |
2694690e JL |
171 | #endif |
172 | ||
98e69567 HS |
173 | #if defined(CONFIG_CHARON) || defined(CONFIG_FO300) || \ |
174 | defined(CONFIG_MINIFAP) || defined(CONFIG_STK52XX) | |
2694690e | 175 | #define CONFIG_CMD_IDE |
2694690e JL |
176 | #endif |
177 | ||
98e69567 HS |
178 | #if defined(CONFIG_CHARON) || defined(CONFIG_FO300) || \ |
179 | defined(CONFIG_STK52XX) | |
2694690e JL |
180 | #define CONFIG_CFG_USB |
181 | #define CONFIG_CFG_FAT | |
182 | #endif | |
183 | ||
af075ee9 JL |
184 | #ifdef CONFIG_POST |
185 | #define CONFIG_CMD_DIAG | |
186 | #endif | |
187 | ||
151ab83a WD |
188 | #define CONFIG_TIMESTAMP /* display image timestamps */ |
189 | ||
14d0a02a | 190 | #if (CONFIG_SYS_TEXT_BASE != 0xFFF00000) |
6d0f6bcf | 191 | # define CONFIG_SYS_LOWBOOT 1 /* Boot low */ |
56523f12 WD |
192 | #endif |
193 | ||
194 | /* | |
195 | * Autobooting | |
196 | */ | |
56523f12 | 197 | |
81050926 | 198 | #define CONFIG_PREBOOT "echo;" \ |
4c4aca81 | 199 | "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ |
56523f12 WD |
200 | "echo" |
201 | ||
202 | #undef CONFIG_BOOTARGS | |
203 | ||
6d0f6bcf | 204 | #if defined(CONFIG_TQM5200_B) && !defined(CONFIG_SYS_LOWBOOT) |
78d620eb WD |
205 | # define ENV_UPDT \ |
206 | "update=protect off FFF00000 +${filesize};" \ | |
207 | "erase FFF00000 +${filesize};" \ | |
5078cce8 | 208 | "cp.b 200000 FFF00000 ${filesize};" \ |
78d620eb WD |
209 | "protect on FFF00000 +${filesize}\0" |
210 | #else /* default lowboot configuration */ | |
6d3bc9b8 | 211 | # define ENV_UPDT \ |
78d620eb WD |
212 | "update=protect off FC000000 +${filesize};" \ |
213 | "erase FC000000 +${filesize};" \ | |
6d3bc9b8 | 214 | "cp.b 200000 FC000000 ${filesize};" \ |
78d620eb WD |
215 | "protect on FC000000 +${filesize}\0" |
216 | #endif | |
5078cce8 | 217 | |
e1f601b5 | 218 | #if defined(CONFIG_TQM5200) |
6abaee42 | 219 | #define CUSTOM_ENV_SETTINGS \ |
e1f601b5 | 220 | "hostname=tqm5200\0" \ |
6abaee42 | 221 | "bootfile=/tftpboot/tqm5200/uImage\0" \ |
8f8416fa | 222 | "fdt_file=/tftpboot/tqm5200/tqm5200.dtb\0" \ |
6abaee42 | 223 | "u-boot=/tftpboot/tqm5200/u-boot.bin\0" |
e1f601b5 | 224 | #elif defined(CONFIG_CAM5200) |
1636d1c8 | 225 | #define CUSTOM_ENV_SETTINGS \ |
6abaee42 RT |
226 | "bootfile=cam5200/uImage\0" \ |
227 | "u-boot=cam5200/u-boot.bin\0" \ | |
74de7aef | 228 | "setup=tftp 200000 cam5200/setup.img; source 200000\0" |
6abaee42 RT |
229 | #endif |
230 | ||
a5cc5555 MK |
231 | #if defined(CONFIG_TQM5200_B) |
232 | #define ENV_FLASH_LAYOUT \ | |
233 | "fdt_addr=FC100000\0" \ | |
234 | "kernel_addr=FC140000\0" \ | |
235 | "ramdisk_addr=FC600000\0" | |
5624d66a HS |
236 | #elif defined(CONFIG_CHARON) |
237 | #define ENV_FLASH_LAYOUT \ | |
238 | "fdt_addr=FDFC0000\0" \ | |
239 | "kernel_addr=FC0A0000\0" \ | |
240 | "ramdisk_addr=FC200000\0" | |
a5cc5555 MK |
241 | #else /* !CONFIG_TQM5200_B */ |
242 | #define ENV_FLASH_LAYOUT \ | |
243 | "fdt_addr=FC0A0000\0" \ | |
244 | "kernel_addr=FC0C0000\0" \ | |
245 | "ramdisk_addr=FC300000\0" | |
246 | #endif | |
247 | ||
81050926 | 248 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
56523f12 | 249 | "netdev=eth0\0" \ |
e1f601b5 | 250 | "console=ttyPSC0\0" \ |
a5cc5555 | 251 | ENV_FLASH_LAYOUT \ |
d78791ae BS |
252 | "kernel_addr_r=400000\0" \ |
253 | "fdt_addr_r=600000\0" \ | |
89c02e2c | 254 | "rootpath=/opt/eldk/ppc_6xx\0" \ |
56523f12 | 255 | "ramargs=setenv bootargs root=/dev/ram rw\0" \ |
56523f12 | 256 | "nfsargs=setenv bootargs root=/dev/nfs rw " \ |
fe126d8b WD |
257 | "nfsroot=${serverip}:${rootpath}\0" \ |
258 | "addip=setenv bootargs ${bootargs} " \ | |
259 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ | |
260 | ":${hostname}:${netdev}:off panic=1\0" \ | |
5078cce8 | 261 | "addcons=setenv bootargs ${bootargs} " \ |
8f8416fa | 262 | "console=${console},${baudrate}\0" \ |
98e69567 HS |
263 | "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ |
264 | "flash_self_old=sete console ttyS0; " \ | |
265 | "run ramargs addip addcons addmtd; " \ | |
fe126d8b | 266 | "bootm ${kernel_addr} ${ramdisk_addr}\0" \ |
e1f601b5 BS |
267 | "flash_self=run ramargs addip addcons;" \ |
268 | "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \ | |
269 | "flash_nfs_old=sete console ttyS0; run nfsargs addip addcons;" \ | |
fe126d8b | 270 | "bootm ${kernel_addr}\0" \ |
e1f601b5 | 271 | "flash_nfs=run nfsargs addip addcons;" \ |
8f8416fa | 272 | "bootm ${kernel_addr} - ${fdt_addr}\0" \ |
e1f601b5 BS |
273 | "net_nfs_old=tftp ${kernel_addr_r} ${bootfile};" \ |
274 | "sete console ttyS0; run nfsargs addip addcons;bootm\0" \ | |
275 | "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \ | |
276 | "tftp ${fdt_addr_r} ${fdt_file}; " \ | |
98e69567 | 277 | "run nfsargs addip addcons addmtd; " \ |
e1f601b5 | 278 | "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \ |
6abaee42 | 279 | CUSTOM_ENV_SETTINGS \ |
5078cce8 WD |
280 | "load=tftp 200000 ${u-boot}\0" \ |
281 | ENV_UPDT \ | |
7e6bf358 | 282 | "" |
56523f12 WD |
283 | |
284 | #define CONFIG_BOOTCOMMAND "run net_nfs" | |
285 | ||
286 | /* | |
287 | * IPB Bus clocking configuration. | |
288 | */ | |
6d0f6bcf | 289 | #define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ |
56523f12 | 290 | |
6d0f6bcf | 291 | #if defined(CONFIG_SYS_IPBCLK_EQUALS_XLBCLK) && !defined(CONFIG_CAM5200) |
56523f12 WD |
292 | /* |
293 | * PCI Bus clocking configuration | |
294 | * | |
295 | * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if | |
6d0f6bcf | 296 | * CONFIG_SYS_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock of |
c99512d6 | 297 | * 66 MHz yet hasn't been tested with a IPB Bus Clock of 66 MHz. |
56523f12 | 298 | */ |
6d0f6bcf | 299 | #define CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2 /* define for 66MHz speed */ |
56523f12 WD |
300 | #endif |
301 | ||
302 | /* | |
303 | * I2C configuration | |
304 | */ | |
305 | #define CONFIG_HARD_I2C 1 /* I2C with hardware support */ | |
8f0b7cbe | 306 | #ifdef CONFIG_TQM5200_REV100 |
6d0f6bcf | 307 | #define CONFIG_SYS_I2C_MODULE 1 /* Select I2C module #1 for rev. 100 board */ |
56523f12 | 308 | #else |
6d0f6bcf | 309 | #define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #2 for all other revs */ |
56523f12 WD |
310 | #endif |
311 | ||
312 | /* | |
313 | * I2C clock frequency | |
314 | * | |
315 | * Please notice, that the resulting clock frequency could differ from the | |
316 | * configured value. This is because the I2C clock is derived from system | |
a187559e | 317 | * clock over a frequency divider with only a few divider values. U-Boot |
6d0f6bcf | 318 | * calculates the best approximation for CONFIG_SYS_I2C_SPEED. However the calculated |
56523f12 WD |
319 | * approximation allways lies below the configured value, never above. |
320 | */ | |
6d0f6bcf JCPV |
321 | #define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */ |
322 | #define CONFIG_SYS_I2C_SLAVE 0x7F | |
56523f12 WD |
323 | |
324 | /* | |
325 | * EEPROM configuration for onboard EEPROM M24C32 (M24C64 should work | |
326 | * also). For other EEPROMs configuration should be verified. On Mini-FAP the | |
327 | * EEPROM (24C64) is on the same I2C address (but on other I2C bus), so the | |
328 | * same configuration could be used. | |
329 | */ | |
6d0f6bcf JCPV |
330 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */ |
331 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 | |
332 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* =32 Bytes per write */ | |
333 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20 | |
56523f12 WD |
334 | |
335 | /* | |
336 | * HW-Monitor configuration on Mini-FAP | |
337 | */ | |
338 | #if defined (CONFIG_MINIFAP) | |
6d0f6bcf | 339 | #define CONFIG_SYS_I2C_HWMON_ADDR 0x2C |
56523f12 WD |
340 | #endif |
341 | ||
342 | /* List of I2C addresses to be verified by POST */ | |
56523f12 | 343 | #if defined (CONFIG_MINIFAP) |
60aaaa07 PT |
344 | #undef CONFIG_SYS_POST_I2C_ADDRS |
345 | #define CONFIG_SYS_POST_I2C_ADDRS {CONFIG_SYS_I2C_EEPROM_ADDR, \ | |
346 | CONFIG_SYS_I2C_HWMON_ADDR, \ | |
347 | CONFIG_SYS_I2C_SLAVE} | |
56523f12 WD |
348 | #endif |
349 | ||
350 | /* | |
351 | * Flash configuration | |
352 | */ | |
6d0f6bcf | 353 | #define CONFIG_SYS_FLASH_BASE 0xFC000000 |
56523f12 | 354 | |
d9384de2 | 355 | #if defined(CONFIG_CAM5200) && defined(CONFIG_CAM5200_NIOSFLASH) |
6d0f6bcf | 356 | #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max num of flash banks |
7299712c | 357 | (= chip selects) */ |
6d0f6bcf JCPV |
358 | #define CONFIG_SYS_FLASH_WORD_SIZE unsigned int /* main flash device with */ |
359 | #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ | |
360 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ | |
361 | ||
362 | #define CONFIG_SYS_FLASH_ADDR0 0x555 | |
363 | #define CONFIG_SYS_FLASH_ADDR1 0x2AA | |
364 | #define CONFIG_SYS_FLASH_2ND_16BIT_DEV 1 /* NIOS flash is a 16bit device */ | |
365 | #define CONFIG_SYS_MAX_FLASH_SECT 128 | |
d9384de2 MB |
366 | #else |
367 | /* use CFI flash driver */ | |
6d0f6bcf | 368 | #define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ |
00b1883a | 369 | #define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ |
085ecde1 | 370 | #define CONFIG_FLASH_CFI_MTD /* with MTD support */ |
6d0f6bcf JCPV |
371 | #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_BOOTCS_START } |
372 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks | |
d9384de2 | 373 | (= chip selects) */ |
6d0f6bcf | 374 | #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */ |
d9384de2 | 375 | #endif |
7299712c | 376 | |
6d0f6bcf JCPV |
377 | #define CONFIG_SYS_FLASH_EMPTY_INFO |
378 | #define CONFIG_SYS_FLASH_SIZE 0x04000000 /* 64 MByte */ | |
379 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 | |
56523f12 | 380 | |
135ae006 | 381 | #if defined (CONFIG_CAM5200) |
6d0f6bcf | 382 | # define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00040000) |
5078cce8 | 383 | #elif defined(CONFIG_TQM5200_B) |
6d0f6bcf | 384 | # define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00080000) |
45a212c4 | 385 | #else |
6d0f6bcf | 386 | # define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00060000) |
5078cce8 WD |
387 | #endif |
388 | ||
d534f5cc | 389 | /* Dynamic MTD partition support */ |
68d7d651 | 390 | #define CONFIG_CMD_MTDPARTS |
942556a9 | 391 | #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ |
259bff7c | 392 | #define MTDIDS_DEFAULT "nor0=fc000000.flash" |
5078cce8 | 393 | |
5624d66a | 394 | #if defined(CONFIG_STK52XX) |
5078cce8 | 395 | # if defined(CONFIG_TQM5200_B) |
6d0f6bcf | 396 | # if defined(CONFIG_SYS_LOWBOOT) |
259bff7c | 397 | # define MTDPARTS_DEFAULT "mtdparts=fc000000.flash:1m(firmware)," \ |
a5cc5555 MK |
398 | "256k(dtb)," \ |
399 | "2304k(kernel)," \ | |
400 | "2560k(small-fs)," \ | |
45a212c4 | 401 | "2m(initrd)," \ |
5078cce8 WD |
402 | "8m(misc)," \ |
403 | "16m(big-fs)" | |
404 | # else /* highboot */ | |
259bff7c | 405 | # define MTDPARTS_DEFAULT "mtdparts=fc000000.flash:2560k(kernel),"\ |
5078cce8 WD |
406 | "3584k(small-fs)," \ |
407 | "2m(initrd)," \ | |
408 | "8m(misc)," \ | |
409 | "15m(big-fs)," \ | |
410 | "1m(firmware)" | |
6d0f6bcf | 411 | # endif /* CONFIG_SYS_LOWBOOT */ |
5078cce8 | 412 | # else /* !CONFIG_TQM5200_B */ |
259bff7c | 413 | # define MTDPARTS_DEFAULT "mtdparts=fc000000.flash:640k(firmware),"\ |
e1f601b5 BS |
414 | "128k(dtb)," \ |
415 | "2304k(kernel)," \ | |
d534f5cc WD |
416 | "2m(initrd)," \ |
417 | "4m(small-fs)," \ | |
5078cce8 | 418 | "8m(misc)," \ |
e1f601b5 | 419 | "15m(big-fs)" |
5078cce8 | 420 | # endif /* CONFIG_TQM5200_B */ |
135ae006 | 421 | #elif defined (CONFIG_CAM5200) |
259bff7c | 422 | # define MTDPARTS_DEFAULT "mtdparts=fc000000.flash:768k(firmware),"\ |
5078cce8 | 423 | "1792k(kernel)," \ |
7299712c MB |
424 | "5632k(rootfs)," \ |
425 | "24m(home)" | |
5624d66a HS |
426 | #elif defined (CONFIG_CHARON) |
427 | # define MTDPARTS_DEFAULT "mtdparts=fc000000.flash:640k(firmware),"\ | |
428 | "1408k(kernel)," \ | |
429 | "2m(initrd)," \ | |
430 | "4m(small-fs)," \ | |
431 | "24320k(big-fs)," \ | |
432 | "256k(dts)" | |
6d3bc9b8 | 433 | #elif defined (CONFIG_FO300) |
259bff7c | 434 | # define MTDPARTS_DEFAULT "mtdparts=fc000000.flash:640k(firmware),"\ |
6d3bc9b8 MB |
435 | "1408k(kernel)," \ |
436 | "2m(initrd)," \ | |
437 | "4m(small-fs)," \ | |
438 | "8m(misc)," \ | |
439 | "16m(big-fs)" | |
5078cce8 WD |
440 | #else |
441 | # error "Unknown Carrier Board" | |
442 | #endif /* CONFIG_STK52XX */ | |
56523f12 WD |
443 | |
444 | /* | |
445 | * Environment settings | |
446 | */ | |
5a1aceb0 | 447 | #define CONFIG_ENV_IS_IN_FLASH 1 |
0e8d1586 | 448 | #define CONFIG_ENV_SIZE 0x4000 /* 16 k - keep small for fast booting */ |
78d620eb | 449 | #if defined(CONFIG_TQM5200_B) || defined (CONFIG_CAM5200) |
0e8d1586 | 450 | #define CONFIG_ENV_SECT_SIZE 0x40000 |
45a212c4 | 451 | #else |
0e8d1586 | 452 | #define CONFIG_ENV_SECT_SIZE 0x20000 |
5078cce8 | 453 | #endif /* CONFIG_TQM5200_B */ |
0e8d1586 JCPV |
454 | #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) |
455 | #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) | |
56523f12 WD |
456 | |
457 | /* | |
458 | * Memory map | |
459 | */ | |
6d0f6bcf JCPV |
460 | #define CONFIG_SYS_MBAR 0xF0000000 |
461 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 | |
462 | #define CONFIG_SYS_DEFAULT_MBAR 0x80000000 | |
56523f12 WD |
463 | |
464 | /* Use ON-Chip SRAM until RAM will be available */ | |
6d0f6bcf | 465 | #define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM |
56523f12 WD |
466 | #ifdef CONFIG_POST |
467 | /* preserve space for the post_word at end of on-chip SRAM */ | |
553f0982 | 468 | #define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_POST_SIZE |
56523f12 | 469 | #else |
553f0982 | 470 | #define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE |
56523f12 WD |
471 | #endif |
472 | ||
25ddd1fb | 473 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
6d0f6bcf | 474 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
56523f12 | 475 | |
14d0a02a | 476 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE |
6d0f6bcf JCPV |
477 | #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) |
478 | # define CONFIG_SYS_RAMBOOT 1 | |
56523f12 WD |
479 | #endif |
480 | ||
135ae006 | 481 | #if defined (CONFIG_CAM5200) |
6d0f6bcf | 482 | # define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ |
5078cce8 | 483 | #elif defined(CONFIG_TQM5200_B) |
6d0f6bcf | 484 | # define CONFIG_SYS_MONITOR_LEN (512 << 10) /* Reserve 512 kB for Monitor */ |
45a212c4 | 485 | #else |
6d0f6bcf | 486 | # define CONFIG_SYS_MONITOR_LEN (384 << 10) /* Reserve 384 kB for Monitor */ |
5078cce8 WD |
487 | #endif |
488 | ||
6d0f6bcf JCPV |
489 | #define CONFIG_SYS_MALLOC_LEN (1024 << 10) /* Reserve 1024 kB for malloc() */ |
490 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ | |
56523f12 WD |
491 | |
492 | /* | |
493 | * Ethernet configuration | |
494 | */ | |
495 | #define CONFIG_MPC5xxx_FEC 1 | |
86321fc1 | 496 | #define CONFIG_MPC5xxx_FEC_MII100 |
56523f12 | 497 | /* |
86321fc1 | 498 | * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb |
56523f12 | 499 | */ |
86321fc1 | 500 | /* #define CONFIG_MPC5xxx_FEC_MII10 */ |
56523f12 WD |
501 | #define CONFIG_PHY_ADDR 0x00 |
502 | ||
503 | /* | |
504 | * GPIO configuration | |
505 | * | |
7299712c MB |
506 | * use CS1: Bit 0 (mask: 0x80000000): |
507 | * 1 -> Pin gpio_wkup_6 as second SDRAM chip select (mem_cs1). | |
56523f12 | 508 | * use ALT CAN position: Bits 2-3 (mask: 0x30000000): |
7299712c MB |
509 | * 00 -> No Alternatives, CAN1/2 on PSC2 according to PSC2 setting. |
510 | * SPI on PSC3 according to PSC3 setting. Use for CAM5200. | |
511 | * 01 -> CAN1 on I2C1, CAN2 on Tmr0/1. | |
512 | * Use for REV200 STK52XX boards and FO300 boards. Do not use | |
513 | * with REV100 modules (because, there I2C1 is used as I2C bus). | |
514 | * use ATA: Bits 6-7 (mask 0x03000000): | |
515 | * 00 -> No ATA chip selects, csb_4/5 used as normal chip selects. | |
516 | * Use for CAM5200 board. | |
517 | * 01 -> ATA cs0/1 on csb_4/5. Use for the remaining boards. | |
518 | * use PSC6: Bits 9-11 (mask 0x00700000): | |
519 | * 000 -> use PSC6_0 to PSC6_3 as GPIO, PSC6 could not be used as | |
520 | * UART, CODEC or IrDA. | |
521 | * GPIO on PSC6_3 is used in post_hotkeys_pressed() to | |
522 | * enable extended POST tests. | |
523 | * Use for MINI-FAP and TQM5200_IB boards. | |
524 | * 101 -> use PSC6 as UART. Pins PSC6_0 to PSC6_3 are used. | |
525 | * Extended POST test is not available. | |
526 | * Use for STK52xx, FO300 and CAM5200 boards. | |
95c44ec4 DZ |
527 | * WARNING: When the extended POST is enabled, these bits will |
528 | * be overridden by this code as GPIOs! | |
7299712c MB |
529 | * use PCI_DIS: Bit 16 (mask 0x00008000): |
530 | * 1 -> disable PCI controller (on CAM5200 board). | |
531 | * use USB: Bits 18-19 (mask 0x00003000): | |
532 | * 10 -> two UARTs (on FO300 and CAM5200). | |
533 | * use PSC3: Bits 20-23 (mask: 0x00000f00): | |
534 | * 0000 -> All PSC3 pins are GPIOs. | |
535 | * 1100 -> UART/SPI (on FO300 board). | |
536 | * 0100 -> UART (on CAM5200 board). | |
537 | * use PSC2: Bits 25:27 (mask: 0x00000030): | |
538 | * 000 -> All PSC2 pins are GPIOs. | |
539 | * 100 -> UART (on CAM5200 board). | |
540 | * 001 -> CAN1/2 on PSC2 pins. | |
95c44ec4 | 541 | * Use for REV100 STK52xx boards |
7299712c MB |
542 | * 01x -> Use AC97 (on FO300 board). |
543 | * use PSC1: Bits 29-31 (mask: 0x00000007): | |
544 | * 100 -> UART (on all boards). | |
56523f12 | 545 | */ |
98e69567 | 546 | #if !defined(CONFIG_SYS_GPS_PORT_CONFIG) |
56523f12 | 547 | #if defined (CONFIG_MINIFAP) |
6d0f6bcf | 548 | # define CONFIG_SYS_GPS_PORT_CONFIG 0x91000004 |
7e6bf358 | 549 | #elif defined (CONFIG_STK52XX) |
83e40ba7 | 550 | # if defined (CONFIG_STK52XX_REV100) |
6d0f6bcf | 551 | # define CONFIG_SYS_GPS_PORT_CONFIG 0x81500014 |
83e40ba7 WD |
552 | # else /* STK52xx REV200 and above */ |
553 | # if defined (CONFIG_TQM5200_REV100) | |
554 | # error TQM5200 REV100 not supported on STK52XX REV200 or above | |
555 | # else/* TQM5200 REV200 and above */ | |
6d0f6bcf | 556 | # define CONFIG_SYS_GPS_PORT_CONFIG 0x91500404 |
83e40ba7 | 557 | # endif |
8f0b7cbe | 558 | # endif |
6d3bc9b8 | 559 | #elif defined (CONFIG_FO300) |
6d0f6bcf | 560 | # define CONFIG_SYS_GPS_PORT_CONFIG 0x91502c24 |
7299712c | 561 | #elif defined (CONFIG_CAM5200) |
6d0f6bcf | 562 | # define CONFIG_SYS_GPS_PORT_CONFIG 0x8050A444 |
83e40ba7 | 563 | #else /* TMQ5200 Inbetriebnahme-Board */ |
6d0f6bcf | 564 | # define CONFIG_SYS_GPS_PORT_CONFIG 0x81000004 |
56523f12 | 565 | #endif |
98e69567 | 566 | #endif |
56523f12 WD |
567 | |
568 | /* | |
569 | * RTC configuration | |
570 | */ | |
4f562f14 WD |
571 | #if defined (CONFIG_STK52XX) && !defined (CONFIG_STK52XX_REV100) |
572 | # define CONFIG_RTC_M41T11 1 | |
6d0f6bcf JCPV |
573 | # define CONFIG_SYS_I2C_RTC_ADDR 0x68 |
574 | # define CONFIG_SYS_M41T11_BASE_YEAR 1900 /* because Linux uses the same base | |
edd0b509 | 575 | year */ |
4f562f14 WD |
576 | #else |
577 | # define CONFIG_RTC_MPC5200 1 /* use internal MPC5200 RTC */ | |
578 | #endif | |
56523f12 WD |
579 | |
580 | /* | |
581 | * Miscellaneous configurable options | |
582 | */ | |
6d0f6bcf | 583 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
5078cce8 | 584 | |
2751a95a | 585 | #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ |
5078cce8 | 586 | |
6d0f6bcf | 587 | #define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ |
2694690e | 588 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 589 | #define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ |
2694690e JL |
590 | #endif |
591 | ||
592 | #if defined(CONFIG_CMD_KGDB) | |
6d0f6bcf | 593 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
56523f12 | 594 | #else |
6d0f6bcf | 595 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
56523f12 | 596 | #endif |
6d0f6bcf JCPV |
597 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
598 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
599 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
56523f12 WD |
600 | |
601 | /* Enable an alternate, more extensive memory test */ | |
6d0f6bcf | 602 | #define CONFIG_SYS_ALT_MEMTEST |
56523f12 | 603 | |
6d0f6bcf JCPV |
604 | #define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ |
605 | #define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ | |
56523f12 | 606 | |
6d0f6bcf | 607 | #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ |
56523f12 | 608 | |
56523f12 WD |
609 | /* |
610 | * Various low-level settings | |
611 | */ | |
6d0f6bcf JCPV |
612 | #define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI |
613 | #define CONFIG_SYS_HID0_FINAL HID0_ICE | |
56523f12 | 614 | |
6d0f6bcf JCPV |
615 | #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE |
616 | #define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE | |
617 | #ifdef CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2 | |
618 | #define CONFIG_SYS_BOOTCS_CFG 0x0008DF30 /* for pci_clk = 66 MHz */ | |
56523f12 | 619 | #else |
6d0f6bcf | 620 | #define CONFIG_SYS_BOOTCS_CFG 0x0004DF30 /* for pci_clk = 33 MHz */ |
56523f12 | 621 | #endif |
6d0f6bcf JCPV |
622 | #define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE |
623 | #define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE | |
56523f12 | 624 | |
7e6bf358 | 625 | #define CONFIG_LAST_STAGE_INIT |
7e6bf358 | 626 | |
56523f12 WD |
627 | /* |
628 | * SRAM - Do not map below 2 GB in address space, because this area is used | |
629 | * for SDRAM autosizing. | |
630 | */ | |
6d0f6bcf JCPV |
631 | #define CONFIG_SYS_CS2_START 0xE5000000 |
632 | #define CONFIG_SYS_CS2_SIZE 0x100000 /* 1 MByte */ | |
633 | #define CONFIG_SYS_CS2_CFG 0x0004D930 | |
56523f12 WD |
634 | |
635 | /* | |
636 | * Grafic controller - Do not map below 2 GB in address space, because this | |
637 | * area is used for SDRAM autosizing. | |
638 | */ | |
8f0b7cbe | 639 | #define SM501_FB_BASE 0xE0000000 |
6d0f6bcf JCPV |
640 | #define CONFIG_SYS_CS1_START (SM501_FB_BASE) |
641 | #define CONFIG_SYS_CS1_SIZE 0x4000000 /* 64 MByte */ | |
642 | #define CONFIG_SYS_CS1_CFG 0x8F48FF70 | |
643 | #define SM501_MMIO_BASE CONFIG_SYS_CS1_START + 0x03E00000 | |
56523f12 | 644 | |
6d0f6bcf JCPV |
645 | #define CONFIG_SYS_CS_BURST 0x00000000 |
646 | #define CONFIG_SYS_CS_DEADCYCLE 0x33333311 /* 1 dead cycle for flash and SM501 */ | |
56523f12 | 647 | |
7299712c | 648 | #if defined(CONFIG_CAM5200) |
6d0f6bcf JCPV |
649 | #define CONFIG_SYS_CS4_START 0xB0000000 |
650 | #define CONFIG_SYS_CS4_SIZE 0x00010000 | |
651 | #define CONFIG_SYS_CS4_CFG 0x01019C10 | |
7299712c | 652 | |
6d0f6bcf JCPV |
653 | #define CONFIG_SYS_CS5_START 0xD0000000 |
654 | #define CONFIG_SYS_CS5_SIZE 0x01208000 | |
655 | #define CONFIG_SYS_CS5_CFG 0x1414BF10 | |
7299712c MB |
656 | #endif |
657 | ||
6d0f6bcf | 658 | #define CONFIG_SYS_RESET_ADDRESS 0xff000000 |
56523f12 WD |
659 | |
660 | /*----------------------------------------------------------------------- | |
661 | * USB stuff | |
662 | *----------------------------------------------------------------------- | |
663 | */ | |
664 | #define CONFIG_USB_CLOCK 0x0001BBBB | |
665 | #define CONFIG_USB_CONFIG 0x00001000 | |
666 | ||
667 | /*----------------------------------------------------------------------- | |
668 | * IDE/ATA stuff Supports IDE harddisk | |
669 | *----------------------------------------------------------------------- | |
670 | */ | |
671 | ||
81050926 | 672 | #undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */ |
56523f12 | 673 | |
81050926 WD |
674 | #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ |
675 | #undef CONFIG_IDE_LED /* LED for ide not supported */ | |
56523f12 | 676 | |
81050926 | 677 | #define CONFIG_IDE_RESET /* reset for ide supported */ |
56523f12 WD |
678 | #define CONFIG_IDE_PREINIT |
679 | ||
6d0f6bcf JCPV |
680 | #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ |
681 | #define CONFIG_SYS_IDE_MAXDEVICE 2 /* max. 2 drives per IDE bus */ | |
56523f12 | 682 | |
6d0f6bcf | 683 | #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 |
56523f12 | 684 | |
6d0f6bcf | 685 | #define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA |
56523f12 | 686 | |
95c44ec4 | 687 | /* Offset for data I/O */ |
6d0f6bcf | 688 | #define CONFIG_SYS_ATA_DATA_OFFSET (0x0060) |
56523f12 | 689 | |
95c44ec4 | 690 | /* Offset for normal register accesses */ |
6d0f6bcf | 691 | #define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET) |
56523f12 | 692 | |
95c44ec4 | 693 | /* Offset for alternate registers */ |
6d0f6bcf | 694 | #define CONFIG_SYS_ATA_ALT_OFFSET (0x005C) |
56523f12 | 695 | |
95c44ec4 | 696 | /* Interval between registers */ |
6d0f6bcf | 697 | #define CONFIG_SYS_ATA_STRIDE 4 |
56523f12 | 698 | |
33af3e66 | 699 | /* Support ATAPI devices */ |
95c44ec4 | 700 | #define CONFIG_ATAPI 1 |
33af3e66 | 701 | |
8f8416fa BS |
702 | /*----------------------------------------------------------------------- |
703 | * Open firmware flat tree support | |
704 | *----------------------------------------------------------------------- | |
705 | */ | |
8f8416fa BS |
706 | #define OF_CPU "PowerPC,5200@0" |
707 | #define OF_SOC "soc5200@f0000000" | |
708 | #define OF_TBCLK (bd->bi_busfreq / 4) | |
709 | #define OF_STDOUT_PATH "/soc5200@f0000000/serial@2000" | |
710 | ||
56523f12 | 711 | #endif /* __CONFIG_H */ |