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89b765c7 SR |
1 | /* |
2 | * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ | |
3 | * | |
4 | * Based on davinci_dvevm.h. Original Copyrights follow: | |
5 | * | |
6 | * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> | |
7 | * | |
1a459660 | 8 | * SPDX-License-Identifier: GPL-2.0+ |
89b765c7 SR |
9 | */ |
10 | ||
11 | #ifndef __CONFIG_H | |
12 | #define __CONFIG_H | |
13 | ||
14 | /* | |
15 | * Board | |
16 | */ | |
3d248d37 | 17 | #define CONFIG_DRIVER_TI_EMAC |
63777665 LP |
18 | /* check if direct NOR boot config is used */ |
19 | #ifndef CONFIG_DIRECT_NOR_BOOT | |
d73a8a1b | 20 | #define CONFIG_USE_SPIFLASH |
63777665 | 21 | #endif |
89b765c7 | 22 | |
a4670f8e AF |
23 | /* |
24 | * Disable DM_* for SPL build and can be re-enabled after adding | |
25 | * DM support in SPL | |
26 | */ | |
27 | #ifdef CONFIG_SPL_BUILD | |
28 | #undef CONFIG_DM_SPI | |
29 | #undef CONFIG_DM_SPI_FLASH | |
30 | #undef CONFIG_DM_I2C | |
31 | #undef CONFIG_DM_I2C_COMPAT | |
32 | #endif | |
89b765c7 SR |
33 | /* |
34 | * SoC Configuration | |
35 | */ | |
36 | #define CONFIG_MACH_DAVINCI_DA850_EVM | |
89b765c7 | 37 | #define CONFIG_SOC_DA8XX /* TI DA8xx SoC */ |
52b0f877 | 38 | #define CONFIG_SOC_DA850 /* TI DA850 SoC */ |
b67d8816 | 39 | #define CONFIG_SYS_EXCEPTION_VECTORS_HIGH |
89b765c7 SR |
40 | #define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID) |
41 | #define CONFIG_SYS_OSCIN_FREQ 24000000 | |
42 | #define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE | |
43 | #define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID) | |
89b765c7 | 44 | |
63777665 LP |
45 | #ifdef CONFIG_DIRECT_NOR_BOOT |
46 | #define CONFIG_ARCH_CPU_INIT | |
47 | #define CONFIG_DA8XX_GPIO | |
48 | #define CONFIG_SYS_TEXT_BASE 0x60000000 | |
49 | #define CONFIG_SYS_DV_NOR_BOOT_CFG (0x11) | |
50 | #define CONFIG_DA850_LOWLEVEL | |
51 | #else | |
52 | #define CONFIG_SYS_TEXT_BASE 0xc1080000 | |
53 | #endif | |
54 | ||
89b765c7 SR |
55 | /* |
56 | * Memory Info | |
57 | */ | |
58 | #define CONFIG_SYS_MALLOC_LEN (0x10000 + 1*1024*1024) /* malloc() len */ | |
89b765c7 SR |
59 | #define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */ |
60 | #define PHYS_SDRAM_1_SIZE (64 << 20) /* SDRAM size 64MB */ | |
97003756 | 61 | #define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/ |
89b765c7 SR |
62 | |
63 | /* memtest start addr */ | |
64 | #define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM_1 + 0x2000000) | |
65 | ||
66 | /* memtest will be run on 16MB */ | |
67 | #define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + 0x2000000 + 16*1024*1024) | |
68 | ||
69 | #define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ | |
89b765c7 | 70 | |
3d2c8e6c CR |
71 | #define CONFIG_SYS_DA850_SYSCFG_SUSPSRC ( \ |
72 | DAVINCI_SYSCFG_SUSPSRC_TIMER0 | \ | |
73 | DAVINCI_SYSCFG_SUSPSRC_SPI1 | \ | |
74 | DAVINCI_SYSCFG_SUSPSRC_UART2 | \ | |
75 | DAVINCI_SYSCFG_SUSPSRC_EMAC | \ | |
76 | DAVINCI_SYSCFG_SUSPSRC_I2C) | |
77 | ||
78 | /* | |
79 | * PLL configuration | |
80 | */ | |
81 | #define CONFIG_SYS_DV_CLKMODE 0 | |
82 | #define CONFIG_SYS_DA850_PLL0_POSTDIV 1 | |
83 | #define CONFIG_SYS_DA850_PLL0_PLLDIV1 0x8000 | |
84 | #define CONFIG_SYS_DA850_PLL0_PLLDIV2 0x8001 | |
85 | #define CONFIG_SYS_DA850_PLL0_PLLDIV3 0x8002 | |
86 | #define CONFIG_SYS_DA850_PLL0_PLLDIV4 0x8003 | |
87 | #define CONFIG_SYS_DA850_PLL0_PLLDIV5 0x8002 | |
88 | #define CONFIG_SYS_DA850_PLL0_PLLDIV6 CONFIG_SYS_DA850_PLL0_PLLDIV1 | |
89 | #define CONFIG_SYS_DA850_PLL0_PLLDIV7 0x8005 | |
90 | ||
91 | #define CONFIG_SYS_DA850_PLL1_POSTDIV 1 | |
92 | #define CONFIG_SYS_DA850_PLL1_PLLDIV1 0x8000 | |
93 | #define CONFIG_SYS_DA850_PLL1_PLLDIV2 0x8001 | |
94 | #define CONFIG_SYS_DA850_PLL1_PLLDIV3 0x8002 | |
95 | ||
96 | #define CONFIG_SYS_DA850_PLL0_PLLM 24 | |
97 | #define CONFIG_SYS_DA850_PLL1_PLLM 21 | |
98 | ||
99 | /* | |
100 | * DDR2 memory configuration | |
101 | */ | |
102 | #define CONFIG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \ | |
103 | DV_DDR_PHY_EXT_STRBEN | \ | |
104 | (0x4 << DV_DDR_PHY_RD_LATENCY_SHIFT)) | |
105 | ||
106 | #define CONFIG_SYS_DA850_DDR2_SDBCR ( \ | |
107 | (1 << DV_DDR_SDCR_MSDRAMEN_SHIFT) | \ | |
108 | (1 << DV_DDR_SDCR_DDREN_SHIFT) | \ | |
109 | (1 << DV_DDR_SDCR_SDRAMEN_SHIFT) | \ | |
110 | (1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT) | \ | |
111 | (0x3 << DV_DDR_SDCR_CL_SHIFT) | \ | |
112 | (0x2 << DV_DDR_SDCR_IBANK_SHIFT) | \ | |
113 | (0x2 << DV_DDR_SDCR_PAGESIZE_SHIFT)) | |
114 | ||
115 | /* SDBCR2 is only used if IBANK_POS bit in SDBCR is set */ | |
116 | #define CONFIG_SYS_DA850_DDR2_SDBCR2 0 | |
117 | ||
118 | #define CONFIG_SYS_DA850_DDR2_SDTIMR ( \ | |
119 | (14 << DV_DDR_SDTMR1_RFC_SHIFT) | \ | |
120 | (2 << DV_DDR_SDTMR1_RP_SHIFT) | \ | |
121 | (2 << DV_DDR_SDTMR1_RCD_SHIFT) | \ | |
122 | (1 << DV_DDR_SDTMR1_WR_SHIFT) | \ | |
123 | (5 << DV_DDR_SDTMR1_RAS_SHIFT) | \ | |
124 | (8 << DV_DDR_SDTMR1_RC_SHIFT) | \ | |
125 | (1 << DV_DDR_SDTMR1_RRD_SHIFT) | \ | |
126 | (0 << DV_DDR_SDTMR1_WTR_SHIFT)) | |
127 | ||
128 | #define CONFIG_SYS_DA850_DDR2_SDTIMR2 ( \ | |
129 | (7 << DV_DDR_SDTMR2_RASMAX_SHIFT) | \ | |
130 | (0 << DV_DDR_SDTMR2_XP_SHIFT) | \ | |
131 | (0 << DV_DDR_SDTMR2_ODT_SHIFT) | \ | |
132 | (17 << DV_DDR_SDTMR2_XSNR_SHIFT) | \ | |
133 | (199 << DV_DDR_SDTMR2_XSRD_SHIFT) | \ | |
134 | (0 << DV_DDR_SDTMR2_RTP_SHIFT) | \ | |
135 | (0 << DV_DDR_SDTMR2_CKE_SHIFT)) | |
136 | ||
137 | #define CONFIG_SYS_DA850_DDR2_SDRCR 0x00000494 | |
138 | #define CONFIG_SYS_DA850_DDR2_PBBPR 0x30 | |
139 | ||
89b765c7 SR |
140 | /* |
141 | * Serial Driver info | |
142 | */ | |
a4670f8e AF |
143 | |
144 | #if defined(CONFIG_SPL_BUILD) || defined(CONFIG_DIRECT_NOR_BOOT) | |
89b765c7 SR |
145 | #define CONFIG_SYS_NS16550_SERIAL |
146 | #define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size */ | |
147 | #define CONFIG_SYS_NS16550_COM1 DAVINCI_UART2_BASE /* Base address of UART2 */ | |
a4670f8e | 148 | #endif |
89b765c7 SR |
149 | #define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID) |
150 | #define CONFIG_CONS_INDEX 1 /* use UART0 for console */ | |
89b765c7 | 151 | |
d73a8a1b | 152 | #define CONFIG_SPI |
d73a8a1b | 153 | #define CONFIG_DAVINCI_SPI |
d73a8a1b | 154 | #define CONFIG_SYS_SPI_CLK clk_get(DAVINCI_SPI1_CLKID) |
a4670f8e AF |
155 | #ifdef CONFIG_SPL_BUILD |
156 | #define CONFIG_SYS_SPI_BASE DAVINCI_SPI1_BASE | |
d73a8a1b SB |
157 | #define CONFIG_SF_DEFAULT_SPEED 30000000 |
158 | #define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED | |
a4670f8e | 159 | #endif |
d73a8a1b | 160 | |
42612104 | 161 | #ifdef CONFIG_USE_SPIFLASH |
42612104 | 162 | #define CONFIG_SPL_SPI_LOAD |
42612104 | 163 | #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x8000 |
2a10f8b9 | 164 | #define CONFIG_SYS_SPI_U_BOOT_SIZE 0x40000 |
42612104 LP |
165 | #endif |
166 | ||
89b765c7 SR |
167 | /* |
168 | * I2C Configuration | |
169 | */ | |
e8459dcc VA |
170 | #define CONFIG_SYS_I2C |
171 | #define CONFIG_SYS_I2C_DAVINCI | |
172 | #define CONFIG_SYS_DAVINCI_I2C_SPEED 25000 | |
173 | #define CONFIG_SYS_DAVINCI_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */ | |
d2607401 | 174 | #define CONFIG_SYS_I2C_EXPANDER_ADDR 0x20 |
89b765c7 | 175 | |
6b2c6468 BG |
176 | /* |
177 | * Flash & Environment | |
178 | */ | |
179 | #ifdef CONFIG_USE_NAND | |
6b2c6468 | 180 | #define CONFIG_NAND_DAVINCI |
6b2c6468 BG |
181 | #define CONFIG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */ |
182 | #define CONFIG_ENV_SIZE (128 << 10) | |
183 | #define CONFIG_SYS_NAND_USE_FLASH_BBT | |
184 | #define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST | |
185 | #define CONFIG_SYS_NAND_PAGE_2K | |
186 | #define CONFIG_SYS_NAND_CS 3 | |
187 | #define CONFIG_SYS_NAND_BASE DAVINCI_ASYNC_EMIF_DATA_CE3_BASE | |
34fa0706 EB |
188 | #define CONFIG_SYS_NAND_MASK_CLE 0x10 |
189 | #define CONFIG_SYS_NAND_MASK_ALE 0x8 | |
6b2c6468 BG |
190 | #undef CONFIG_SYS_NAND_HW_ECC |
191 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ | |
122f9c9b LP |
192 | #define CONFIG_SYS_NAND_HW_ECC_OOBFIRST |
193 | #define CONFIG_SYS_NAND_5_ADDR_CYCLE | |
194 | #define CONFIG_SYS_NAND_PAGE_SIZE (2 << 10) | |
195 | #define CONFIG_SYS_NAND_BLOCK_SIZE (128 << 10) | |
196 | #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x28000 | |
197 | #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x60000 | |
198 | #define CONFIG_SYS_NAND_U_BOOT_DST 0xc1080000 | |
199 | #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST | |
200 | #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_DST - \ | |
201 | CONFIG_SYS_NAND_U_BOOT_SIZE - \ | |
202 | CONFIG_SYS_MALLOC_LEN - \ | |
203 | GENERATED_GBL_DATA_SIZE) | |
204 | #define CONFIG_SYS_NAND_ECCPOS { \ | |
205 | 24, 25, 26, 27, 28, \ | |
206 | 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, \ | |
207 | 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, \ | |
208 | 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, \ | |
209 | 59, 60, 61, 62, 63 } | |
210 | #define CONFIG_SYS_NAND_PAGE_COUNT 64 | |
211 | #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 | |
212 | #define CONFIG_SYS_NAND_ECCSIZE 512 | |
213 | #define CONFIG_SYS_NAND_ECCBYTES 10 | |
214 | #define CONFIG_SYS_NAND_OOBSIZE 64 | |
6f2f01b9 SW |
215 | #define CONFIG_SPL_NAND_BASE |
216 | #define CONFIG_SPL_NAND_DRIVERS | |
217 | #define CONFIG_SPL_NAND_ECC | |
122f9c9b LP |
218 | #define CONFIG_SPL_NAND_SIMPLE |
219 | #define CONFIG_SPL_NAND_LOAD | |
6b2c6468 BG |
220 | #endif |
221 | ||
3d248d37 BG |
222 | /* |
223 | * Network & Ethernet Configuration | |
224 | */ | |
225 | #ifdef CONFIG_DRIVER_TI_EMAC | |
3d248d37 | 226 | #define CONFIG_MII |
3d248d37 BG |
227 | #define CONFIG_BOOTP_DNS |
228 | #define CONFIG_BOOTP_DNS2 | |
229 | #define CONFIG_BOOTP_SEND_HOSTNAME | |
230 | #define CONFIG_NET_RETRY_COUNT 10 | |
3d248d37 BG |
231 | #endif |
232 | ||
1506b0a8 | 233 | #ifdef CONFIG_USE_NOR |
1506b0a8 NN |
234 | #define CONFIG_FLASH_CFI_DRIVER |
235 | #define CONFIG_SYS_FLASH_CFI | |
236 | #define CONFIG_SYS_FLASH_PROTECTION | |
237 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of flash banks */ | |
238 | #define CONFIG_SYS_FLASH_SECT_SZ (128 << 10) /* 128KB */ | |
239 | #define CONFIG_ENV_OFFSET (CONFIG_SYS_FLASH_SECT_SZ * 3) | |
240 | #define CONFIG_ENV_SIZE (10 << 10) /* 10KB */ | |
241 | #define CONFIG_SYS_FLASH_BASE DAVINCI_ASYNC_EMIF_DATA_CE2_BASE | |
242 | #define PHYS_FLASH_SIZE (8 << 20) /* Flash size 8MB */ | |
243 | #define CONFIG_SYS_MAX_FLASH_SECT ((PHYS_FLASH_SIZE/CONFIG_SYS_FLASH_SECT_SZ)\ | |
244 | + 3) | |
245 | #define CONFIG_ENV_SECT_SIZE CONFIG_SYS_FLASH_SECT_SZ | |
246 | #endif | |
247 | ||
d73a8a1b | 248 | #ifdef CONFIG_USE_SPIFLASH |
d73a8a1b | 249 | #define CONFIG_ENV_SIZE (64 << 10) |
2a10f8b9 | 250 | #define CONFIG_ENV_OFFSET (512 << 10) |
d73a8a1b | 251 | #define CONFIG_ENV_SECT_SIZE (64 << 10) |
f4fad716 AF |
252 | #ifdef CONFIG_SPL_BUILD |
253 | #undef CONFIG_SPI_FLASH_MTD | |
254 | #endif | |
255 | #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ | |
256 | #define CONFIG_MTD_PARTITIONS /* required for UBI partition support */ | |
257 | #define MTDIDS_DEFAULT "nor0=spi0.0" | |
258 | #define MTDPARTS_DEFAULT "mtdparts=spi0.0:"\ | |
259 | "512k(u-boot.ais),"\ | |
260 | "64k(u-boot-env),"\ | |
261 | "7552k(kernel-spare),"\ | |
262 | "64k(MAC-Address)" | |
d73a8a1b SB |
263 | #endif |
264 | ||
89b765c7 SR |
265 | /* |
266 | * U-Boot general configuration | |
267 | */ | |
cf2c24e3 | 268 | #define CONFIG_MISC_INIT_R |
89b765c7 | 269 | #define CONFIG_BOOTFILE "uImage" /* Boot file name */ |
89b765c7 | 270 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
89b765c7 SR |
271 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */ |
272 | #define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x700000) | |
89b765c7 | 273 | #define CONFIG_AUTO_COMPLETE |
89b765c7 SR |
274 | #define CONFIG_CMDLINE_EDITING |
275 | #define CONFIG_SYS_LONGHELP | |
89b765c7 SR |
276 | #define CONFIG_MX_CYCLIC |
277 | ||
278 | /* | |
279 | * Linux Information | |
280 | */ | |
59e0d611 | 281 | #define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100) |
cf2c24e3 | 282 | #define CONFIG_HWCONFIG /* enable hwconfig */ |
89b765c7 | 283 | #define CONFIG_CMDLINE_TAG |
4f6fc15b | 284 | #define CONFIG_REVISION_TAG |
89b765c7 | 285 | #define CONFIG_SETUP_MEMORY_TAGS |
a4670f8e AF |
286 | |
287 | #define CONFIG_BOOTCOMMAND \ | |
288 | "run envboot; " \ | |
289 | "run mmcboot; " | |
290 | ||
291 | #define DEFAULT_LINUX_BOOT_ENV \ | |
292 | "loadaddr=0xc0700000\0" \ | |
293 | "fdtaddr=0xc0600000\0" \ | |
294 | "scriptaddr=0xc0600000\0" | |
295 | ||
296 | #include <environment/ti/mmc.h> | |
297 | ||
298 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
299 | DEFAULT_LINUX_BOOT_ENV \ | |
300 | DEFAULT_MMC_TI_ARGS \ | |
301 | "bootpart=0:2\0" \ | |
302 | "bootdir=/boot\0" \ | |
303 | "bootfile=zImage\0" \ | |
304 | "fdtfile=da850-evm.dtb\0" \ | |
305 | "boot_fdt=yes\0" \ | |
306 | "boot_fit=0\0" \ | |
307 | "console=ttyS2,115200n8\0" \ | |
308 | "hwconfig=dsp:wake=yes" | |
89b765c7 | 309 | |
8f5d4687 HM |
310 | #ifdef CONFIG_CMD_BDI |
311 | #define CONFIG_CLOCKS | |
312 | #endif | |
313 | ||
89b765c7 | 314 | #ifndef CONFIG_DRIVER_TI_EMAC |
89b765c7 SR |
315 | #endif |
316 | ||
6b2c6468 | 317 | #ifdef CONFIG_USE_NAND |
771d028a BG |
318 | #define CONFIG_MTD_DEVICE |
319 | #define CONFIG_MTD_PARTITIONS | |
6b2c6468 BG |
320 | #endif |
321 | ||
d73a8a1b | 322 | #ifdef CONFIG_USE_SPIFLASH |
d73a8a1b SB |
323 | #endif |
324 | ||
89b765c7 SR |
325 | #if !defined(CONFIG_USE_NAND) && \ |
326 | !defined(CONFIG_USE_NOR) && \ | |
327 | !defined(CONFIG_USE_SPIFLASH) | |
89b765c7 | 328 | #define CONFIG_ENV_SIZE (16 << 10) |
89b765c7 SR |
329 | #endif |
330 | ||
63777665 | 331 | #ifndef CONFIG_DIRECT_NOR_BOOT |
3d2c8e6c | 332 | /* defines for SPL */ |
3f7f2414 | 333 | #define CONFIG_SPL_FRAMEWORK |
3f7f2414 TR |
334 | #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE - \ |
335 | CONFIG_SYS_MALLOC_LEN) | |
336 | #define CONFIG_SYS_SPL_MALLOC_SIZE CONFIG_SYS_MALLOC_LEN | |
3f7f2414 | 337 | #define CONFIG_SPL_SPI_LOAD |
3d2c8e6c CR |
338 | #define CONFIG_SPL_STACK 0x8001ff00 |
339 | #define CONFIG_SPL_TEXT_BASE 0x80000000 | |
b7b5f1a1 | 340 | #define CONFIG_SPL_MAX_FOOTPRINT 32768 |
532d5318 | 341 | #define CONFIG_SPL_PAD_TO 32768 |
63777665 | 342 | #endif |
0d986e61 LP |
343 | |
344 | /* Load U-Boot Image From MMC */ | |
345 | #ifdef CONFIG_SPL_MMC_LOAD | |
0d986e61 LP |
346 | #undef CONFIG_SPL_SPI_LOAD |
347 | #endif | |
348 | ||
ab86f72c | 349 | /* additions for new relocation code, must added to all boards */ |
ab86f72c | 350 | #define CONFIG_SYS_SDRAM_BASE 0xc0000000 |
63777665 LP |
351 | |
352 | #ifdef CONFIG_DIRECT_NOR_BOOT | |
353 | #define CONFIG_SYS_INIT_SP_ADDR 0x8001ff00 | |
354 | #else | |
ab86f72c | 355 | #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - /* Fix this */ \ |
25ddd1fb | 356 | GENERATED_GBL_DATA_SIZE) |
63777665 | 357 | #endif /* CONFIG_DIRECT_NOR_BOOT */ |
89f5eaa1 SG |
358 | |
359 | #include <asm/arch/hardware.h> | |
360 | ||
89b765c7 | 361 | #endif /* __CONFIG_H */ |