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5da627a4 WD |
1 | /* |
2 | * (C) Copyright 2003 | |
3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. | |
4 | * | |
1a459660 | 5 | * SPDX-License-Identifier: GPL-2.0+ |
5da627a4 WD |
6 | */ |
7 | ||
8 | /* | |
9 | * This file contains the configuration parameters for the dbau1x00 board. | |
10 | */ | |
11 | ||
12 | #ifndef __CONFIG_H | |
13 | #define __CONFIG_H | |
14 | ||
15 | #define CONFIG_MIPS32 1 /* MIPS32 CPU core */ | |
16 | #define CONFIG_DBAU1X00 1 | |
8bde63eb | 17 | #define CONFIG_SOC_AU1X00 1 /* alchemy series cpu */ |
5da627a4 | 18 | |
a2663ea4 | 19 | #ifdef CONFIG_DBAU1000 |
5da627a4 | 20 | /* Also known as Merlot */ |
8bde63eb | 21 | #define CONFIG_SOC_AU1000 1 |
a2663ea4 WD |
22 | #else |
23 | #ifdef CONFIG_DBAU1100 | |
8bde63eb | 24 | #define CONFIG_SOC_AU1100 1 |
a2663ea4 WD |
25 | #else |
26 | #ifdef CONFIG_DBAU1500 | |
8bde63eb | 27 | #define CONFIG_SOC_AU1500 1 |
d4ca31c4 | 28 | #else |
ff36fd85 WD |
29 | #ifdef CONFIG_DBAU1550 |
30 | /* Cabernet */ | |
8bde63eb | 31 | #define CONFIG_SOC_AU1550 1 |
ff36fd85 | 32 | #else |
a2663ea4 WD |
33 | #error "No valid board set" |
34 | #endif | |
35 | #endif | |
36 | #endif | |
ff36fd85 | 37 | #endif |
5da627a4 | 38 | |
d4ca31c4 | 39 | #define CONFIG_ETHADDR DE:AD:BE:EF:01:01 /* Ethernet address */ |
5da627a4 WD |
40 | |
41 | #define CONFIG_BOOTDELAY 2 /* autoboot after 2 seconds */ | |
42 | ||
43 | #define CONFIG_BAUDRATE 115200 | |
44 | ||
45 | /* valid baudrates */ | |
5da627a4 WD |
46 | |
47 | #define CONFIG_TIMESTAMP /* Print image info with timestamp */ | |
48 | #undef CONFIG_BOOTARGS | |
49 | ||
50 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
fe126d8b WD |
51 | "addmisc=setenv bootargs ${bootargs} " \ |
52 | "console=ttyS0,${baudrate} " \ | |
5da627a4 WD |
53 | "panic=1\0" \ |
54 | "bootfile=/tftpboot/vmlinux.srec\0" \ | |
fe126d8b | 55 | "load=tftp 80500000 ${u-boot}\0" \ |
5da627a4 | 56 | "" |
ff36fd85 WD |
57 | |
58 | #ifdef CONFIG_DBAU1550 | |
59 | /* Boot from flash by default, revert to bootp */ | |
60 | #define CONFIG_BOOTCOMMAND "bootm 0xbfc20000; bootp; bootm" | |
ff36fd85 | 61 | #else /* CONFIG_DBAU1550 */ |
ad88297e | 62 | #define CONFIG_BOOTCOMMAND "bootp;bootm" |
ff36fd85 WD |
63 | #endif /* CONFIG_DBAU1550 */ |
64 | ||
ab999ba1 | 65 | |
80ff4f99 JL |
66 | /* |
67 | * BOOTP options | |
68 | */ | |
69 | #define CONFIG_BOOTP_BOOTFILESIZE | |
70 | #define CONFIG_BOOTP_BOOTPATH | |
71 | #define CONFIG_BOOTP_GATEWAY | |
72 | #define CONFIG_BOOTP_HOSTNAME | |
73 | ||
74 | ||
ab999ba1 JL |
75 | /* |
76 | * Command line configuration. | |
77 | */ | |
78 | #include <config_cmd_default.h> | |
79 | ||
80 | #undef CONFIG_CMD_BDI | |
81 | #undef CONFIG_CMD_BEDBUG | |
82 | #undef CONFIG_CMD_ELF | |
bdab39d3 | 83 | #undef CONFIG_CMD_SAVEENV |
ab999ba1 JL |
84 | #undef CONFIG_CMD_FAT |
85 | #undef CONFIG_CMD_FPGA | |
86 | #undef CONFIG_CMD_MII | |
87 | #undef CONFIG_CMD_RUN | |
88 | ||
89 | ||
90 | #ifdef CONFIG_DBAU1550 | |
91 | ||
92 | #define CONFIG_CMD_FLASH | |
93 | #define CONFIG_CMD_LOADB | |
94 | #define CONFIG_CMD_NET | |
95 | ||
96 | #undef CONFIG_CMD_I2C | |
97 | #undef CONFIG_CMD_IDE | |
98 | #undef CONFIG_CMD_NFS | |
99 | #undef CONFIG_CMD_PCMCIA | |
100 | ||
101 | #else | |
102 | ||
103 | #define CONFIG_CMD_IDE | |
104 | #define CONFIG_CMD_DHCP | |
105 | ||
106 | #undef CONFIG_CMD_FLASH | |
107 | #undef CONFIG_CMD_LOADB | |
108 | #undef CONFIG_CMD_LOADS | |
109 | ||
110 | #endif | |
111 | ||
5da627a4 WD |
112 | |
113 | /* | |
114 | * Miscellaneous configurable options | |
115 | */ | |
6d0f6bcf | 116 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
ff36fd85 | 117 | |
6d0f6bcf | 118 | #define CONFIG_SYS_PROMPT "DbAu1xx0 # " /* Monitor Command Prompt */ |
ff36fd85 | 119 | |
6d0f6bcf JCPV |
120 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
121 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ | |
122 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args*/ | |
5da627a4 | 123 | |
6d0f6bcf | 124 | #define CONFIG_SYS_MALLOC_LEN 128*1024 |
5da627a4 | 125 | |
6d0f6bcf | 126 | #define CONFIG_SYS_BOOTPARAMS_LEN 128*1024 |
5da627a4 | 127 | |
6d0f6bcf | 128 | #define CONFIG_SYS_MHZ 396 |
ff36fd85 | 129 | |
6d0f6bcf | 130 | #if (CONFIG_SYS_MHZ % 12) != 0 |
ff36fd85 WD |
131 | #error "Invalid CPU frequency - must be multiple of 12!" |
132 | #endif | |
133 | ||
6d0f6bcf | 134 | #define CONFIG_SYS_MIPS_TIMER_FREQ (CONFIG_SYS_MHZ * 1000000) |
a55d4817 | 135 | |
6d0f6bcf | 136 | #define CONFIG_SYS_SDRAM_BASE 0x80000000 /* Cached addr */ |
5da627a4 | 137 | |
6d0f6bcf | 138 | #define CONFIG_SYS_LOAD_ADDR 0x81000000 /* default load address */ |
5da627a4 | 139 | |
6d0f6bcf JCPV |
140 | #define CONFIG_SYS_MEMTEST_START 0x80100000 |
141 | #define CONFIG_SYS_MEMTEST_END 0x80800000 | |
5da627a4 WD |
142 | |
143 | /*----------------------------------------------------------------------- | |
144 | * FLASH and environment organization | |
145 | */ | |
ff36fd85 WD |
146 | #ifdef CONFIG_DBAU1550 |
147 | ||
6d0f6bcf JCPV |
148 | #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ |
149 | #define CONFIG_SYS_MAX_FLASH_SECT (512) /* max number of sectors on one chip */ | |
ff36fd85 WD |
150 | |
151 | #define PHYS_FLASH_1 0xb8000000 /* Flash Bank #1 */ | |
152 | #define PHYS_FLASH_2 0xbc000000 /* Flash Bank #2 */ | |
153 | ||
ff36fd85 WD |
154 | #else /* CONFIG_DBAU1550 */ |
155 | ||
6d0f6bcf JCPV |
156 | #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ |
157 | #define CONFIG_SYS_MAX_FLASH_SECT (128) /* max number of sectors on one chip */ | |
5da627a4 WD |
158 | |
159 | #define PHYS_FLASH_1 0xbec00000 /* Flash Bank #1 */ | |
160 | #define PHYS_FLASH_2 0xbfc00000 /* Flash Bank #2 */ | |
161 | ||
ff36fd85 WD |
162 | #endif /* CONFIG_DBAU1550 */ |
163 | ||
6d0f6bcf | 164 | #define CONFIG_SYS_FLASH_BANKS_LIST {PHYS_FLASH_1, PHYS_FLASH_2} |
ad88297e | 165 | |
6d0f6bcf | 166 | #define CONFIG_SYS_FLASH_CFI 1 |
00b1883a | 167 | #define CONFIG_FLASH_CFI_DRIVER 1 |
ff36fd85 | 168 | |
5da627a4 | 169 | /* The following #defines are needed to get flash environment right */ |
14d0a02a | 170 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE |
6d0f6bcf | 171 | #define CONFIG_SYS_MONITOR_LEN (192 << 10) |
5da627a4 | 172 | |
6d0f6bcf | 173 | #define CONFIG_SYS_INIT_SP_OFFSET 0x400000 |
5da627a4 WD |
174 | |
175 | /* We boot from this flash, selected with dip switch */ | |
6d0f6bcf | 176 | #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_2 |
5da627a4 WD |
177 | |
178 | /* timeout values are in ticks */ | |
6d0f6bcf JCPV |
179 | #define CONFIG_SYS_FLASH_ERASE_TOUT (2 * CONFIG_SYS_HZ) /* Timeout for Flash Erase */ |
180 | #define CONFIG_SYS_FLASH_WRITE_TOUT (2 * CONFIG_SYS_HZ) /* Timeout for Flash Write */ | |
5da627a4 | 181 | |
93f6d725 | 182 | #define CONFIG_ENV_IS_NOWHERE 1 |
5da627a4 WD |
183 | |
184 | /* Address and size of Primary Environment Sector */ | |
0e8d1586 JCPV |
185 | #define CONFIG_ENV_ADDR 0xB0030000 |
186 | #define CONFIG_ENV_SIZE 0x10000 | |
5da627a4 WD |
187 | |
188 | #define CONFIG_FLASH_16BIT | |
189 | ||
190 | #define CONFIG_NR_DRAM_BANKS 2 | |
191 | ||
5da627a4 | 192 | |
ff36fd85 WD |
193 | #ifdef CONFIG_DBAU1550 |
194 | #define MEM_SIZE 192 | |
195 | #else | |
196 | #define MEM_SIZE 64 | |
197 | #endif | |
198 | ||
5da627a4 WD |
199 | #define CONFIG_MEMSIZE_IN_BYTES |
200 | ||
ff36fd85 | 201 | #ifndef CONFIG_DBAU1550 |
5da627a4 | 202 | /*---ATA PCMCIA ------------------------------------*/ |
6d0f6bcf JCPV |
203 | #define CONFIG_SYS_PCMCIA_MEM_SIZE 0x4000000 /* Offset to slot 1 FIXME!!! */ |
204 | #define CONFIG_SYS_PCMCIA_MEM_ADDR 0x20000000 | |
5da627a4 WD |
205 | #define CONFIG_PCMCIA_SLOT_A |
206 | ||
207 | #define CONFIG_ATAPI 1 | |
208 | #define CONFIG_MAC_PARTITION 1 | |
209 | ||
210 | /* We run CF in "true ide" mode or a harddrive via pcmcia */ | |
211 | #define CONFIG_IDE_PCMCIA 1 | |
212 | ||
213 | /* We only support one slot for now */ | |
6d0f6bcf JCPV |
214 | #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ |
215 | #define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ | |
5da627a4 WD |
216 | |
217 | #undef CONFIG_IDE_LED /* LED for ide not supported */ | |
218 | #undef CONFIG_IDE_RESET /* reset for ide not supported */ | |
219 | ||
6d0f6bcf | 220 | #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 |
5da627a4 | 221 | |
6d0f6bcf | 222 | #define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR |
5da627a4 | 223 | |
d4ca31c4 | 224 | /* Offset for data I/O */ |
6d0f6bcf | 225 | #define CONFIG_SYS_ATA_DATA_OFFSET 8 |
5da627a4 WD |
226 | |
227 | /* Offset for normal register accesses */ | |
6d0f6bcf | 228 | #define CONFIG_SYS_ATA_REG_OFFSET 0 |
5da627a4 WD |
229 | |
230 | /* Offset for alternate registers */ | |
6d0f6bcf | 231 | #define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 |
ff36fd85 | 232 | #endif /* CONFIG_DBAU1550 */ |
5da627a4 WD |
233 | |
234 | /*----------------------------------------------------------------------- | |
235 | * Cache Configuration | |
236 | */ | |
6d0f6bcf JCPV |
237 | #define CONFIG_SYS_DCACHE_SIZE 16384 |
238 | #define CONFIG_SYS_ICACHE_SIZE 16384 | |
239 | #define CONFIG_SYS_CACHELINE_SIZE 32 | |
5da627a4 | 240 | |
5da627a4 | 241 | #endif /* __CONFIG_H */ |