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a87589da WD |
1 | /* |
2 | * (C) Copyright 2003-2005 | |
3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. | |
4 | * | |
3765b3e7 | 5 | * SPDX-License-Identifier: GPL-2.0+ |
a87589da WD |
6 | */ |
7 | ||
8 | #ifndef __CONFIG_H | |
9 | #define __CONFIG_H | |
10 | ||
11 | /* | |
12 | * High Level Configuration Options | |
13 | * (easy to change) | |
14 | */ | |
15 | ||
16 | #define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ | |
17 | #define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */ | |
18 | #define CONFIG_HMI1001 1 /* HMI1001 board */ | |
19 | ||
2ae18241 WD |
20 | #ifndef CONFIG_SYS_TEXT_BASE |
21 | #define CONFIG_SYS_TEXT_BASE 0xFFF00000 | |
22 | #endif | |
23 | ||
6d0f6bcf | 24 | #define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */ |
a87589da | 25 | |
a87589da WD |
26 | #define CONFIG_BOARD_EARLY_INIT_R |
27 | ||
31d82672 BB |
28 | #define CONFIG_HIGH_BATS 1 /* High BATs supported */ |
29 | ||
a87589da WD |
30 | /* |
31 | * Serial console configuration | |
32 | */ | |
33 | #define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ | |
34 | #define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */ | |
6d0f6bcf | 35 | #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } |
a87589da | 36 | |
08abe158 WD |
37 | /* Partitions */ |
38 | #define CONFIG_DOS_PARTITION | |
39 | ||
48d5d102 | 40 | |
7f5c0157 JL |
41 | /* |
42 | * BOOTP options | |
43 | */ | |
44 | #define CONFIG_BOOTP_BOOTFILESIZE | |
45 | #define CONFIG_BOOTP_BOOTPATH | |
46 | #define CONFIG_BOOTP_GATEWAY | |
47 | #define CONFIG_BOOTP_HOSTNAME | |
48 | ||
49 | ||
a87589da | 50 | /* |
48d5d102 | 51 | * Command line configuration. |
a87589da | 52 | */ |
48d5d102 JL |
53 | #include <config_cmd_default.h> |
54 | ||
55 | #define CONFIG_CMD_DATE | |
56 | #define CONFIG_CMD_DISPLAY | |
57 | #define CONFIG_CMD_DHCP | |
58 | #define CONFIG_CMD_EEPROM | |
59 | #define CONFIG_CMD_I2C | |
60 | #define CONFIG_CMD_IDE | |
61 | #define CONFIG_CMD_NFS | |
62 | #define CONFIG_CMD_PCI | |
63 | #define CONFIG_CMD_SNTP | |
64 | ||
a87589da WD |
65 | |
66 | #define CONFIG_TIMESTAMP 1 /* Print image info with timestamp */ | |
67 | ||
14d0a02a | 68 | #if (CONFIG_SYS_TEXT_BASE == 0xFFF00000) /* Boot low */ |
6d0f6bcf | 69 | # define CONFIG_SYS_LOWBOOT 1 |
a87589da WD |
70 | #endif |
71 | ||
72 | /* | |
73 | * Autobooting | |
74 | */ | |
75 | #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ | |
76 | ||
77 | #define CONFIG_PREBOOT "echo;" \ | |
32bf3d14 | 78 | "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ |
a87589da WD |
79 | "echo" |
80 | ||
81 | #undef CONFIG_BOOTARGS | |
82 | ||
83 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
84 | "netdev=eth0\0" \ | |
85 | "nfsargs=setenv bootargs root=/dev/nfs rw " \ | |
fe126d8b | 86 | "nfsroot=${serverip}:${rootpath}\0" \ |
a87589da | 87 | "ramargs=setenv bootargs root=/dev/ram rw\0" \ |
fe126d8b WD |
88 | "addip=setenv bootargs ${bootargs} " \ |
89 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ | |
90 | ":${hostname}:${netdev}:off panic=1\0" \ | |
a87589da | 91 | "flash_nfs=run nfsargs addip;" \ |
fe126d8b WD |
92 | "bootm ${kernel_addr}\0" \ |
93 | "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ | |
a87589da WD |
94 | "rootpath=/opt/eldk/ppc_82xx\0" \ |
95 | "" | |
96 | ||
97 | #define CONFIG_BOOTCOMMAND "run net_nfs" | |
98 | ||
9f96ae44 WD |
99 | #define CONFIG_MISC_INIT_R 1 |
100 | ||
a87589da WD |
101 | /* |
102 | * IPB Bus clocking configuration. | |
103 | */ | |
6d0f6bcf | 104 | #undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ |
a87589da | 105 | |
342717f7 WD |
106 | /* |
107 | * I2C configuration | |
108 | */ | |
109 | #define CONFIG_HARD_I2C 1 /* I2C with hardware support */ | |
6d0f6bcf | 110 | #define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #1 or #2 */ |
342717f7 | 111 | |
6d0f6bcf JCPV |
112 | #define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */ |
113 | #define CONFIG_SYS_I2C_SLAVE 0x7F | |
342717f7 WD |
114 | |
115 | /* | |
116 | * EEPROM configuration | |
117 | */ | |
6d0f6bcf JCPV |
118 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x58 |
119 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 | |
120 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 | |
121 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 | |
342717f7 WD |
122 | |
123 | /* | |
124 | * RTC configuration | |
125 | */ | |
126 | #define CONFIG_RTC_PCF8563 | |
6d0f6bcf | 127 | #define CONFIG_SYS_I2C_RTC_ADDR 0x51 |
342717f7 | 128 | |
a87589da WD |
129 | /* |
130 | * Flash configuration | |
131 | */ | |
6d0f6bcf | 132 | #define CONFIG_SYS_FLASH_BASE 0xFF800000 |
a87589da | 133 | |
6d0f6bcf JCPV |
134 | #define CONFIG_SYS_FLASH_SIZE 0x00800000 /* 8 MByte */ |
135 | #define CONFIG_SYS_MAX_FLASH_SECT 67 /* max num of sects on one chip */ | |
a87589da | 136 | |
14d0a02a | 137 | #define CONFIG_ENV_ADDR (CONFIG_SYS_TEXT_BASE+0x40000) /* second sector */ |
6d0f6bcf | 138 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks |
a87589da | 139 | (= chip selects) */ |
6d0f6bcf JCPV |
140 | #define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ |
141 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ | |
a87589da | 142 | |
00b1883a | 143 | #define CONFIG_FLASH_CFI_DRIVER |
6d0f6bcf JCPV |
144 | #define CONFIG_SYS_FLASH_CFI |
145 | #define CONFIG_SYS_FLASH_EMPTY_INFO | |
146 | #define CONFIG_SYS_FLASH_CFI_AMD_RESET | |
a87589da WD |
147 | |
148 | /* | |
149 | * Environment settings | |
150 | */ | |
5a1aceb0 | 151 | #define CONFIG_ENV_IS_IN_FLASH 1 |
0e8d1586 JCPV |
152 | #define CONFIG_ENV_SIZE 0x4000 |
153 | #define CONFIG_ENV_SECT_SIZE 0x20000 | |
154 | #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE) | |
155 | #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) | |
a87589da WD |
156 | |
157 | /* | |
158 | * Memory map | |
159 | */ | |
6d0f6bcf JCPV |
160 | #define CONFIG_SYS_MBAR 0xF0000000 |
161 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 | |
162 | #define CONFIG_SYS_DEFAULT_MBAR 0x80000000 | |
163 | #define CONFIG_SYS_DISPLAY_BASE 0x80600000 | |
164 | #define CONFIG_SYS_STATUS1_BASE 0x80600200 | |
165 | #define CONFIG_SYS_STATUS2_BASE 0x80600300 | |
a87589da WD |
166 | |
167 | /* Settings for XLB = 132 MHz */ | |
168 | #define SDRAM_DDR 1 | |
169 | #define SDRAM_MODE 0x018D0000 | |
170 | #define SDRAM_EMODE 0x40090000 | |
171 | #define SDRAM_CONTROL 0x714f0f00 | |
172 | #define SDRAM_CONFIG1 0x73722930 | |
173 | #define SDRAM_CONFIG2 0x47770000 | |
174 | #define SDRAM_TAPDELAY 0x10000000 | |
175 | ||
176 | /* Use ON-Chip SRAM until RAM will be available */ | |
6d0f6bcf | 177 | #define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM |
800eb096 | 178 | |
a87589da | 179 | /* preserve space for the post_word at end of on-chip SRAM */ |
800eb096 MZ |
180 | #define MPC5XXX_SRAM_POST_SIZE (MPC5XXX_SRAM_SIZE - 4) |
181 | ||
182 | #ifdef CONFIG_POST | |
553f0982 | 183 | #define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_POST_SIZE |
a87589da | 184 | #else |
553f0982 | 185 | #define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE |
a87589da WD |
186 | #endif |
187 | ||
25ddd1fb | 188 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
6d0f6bcf | 189 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
a87589da | 190 | |
14d0a02a | 191 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE |
6d0f6bcf JCPV |
192 | #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) |
193 | # define CONFIG_SYS_RAMBOOT 1 | |
a87589da WD |
194 | #endif |
195 | ||
6d0f6bcf JCPV |
196 | #define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ |
197 | #define CONFIG_SYS_MALLOC_LEN (512 << 10) /* Reserve 128 kB for malloc() */ | |
198 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ | |
a87589da WD |
199 | |
200 | /* | |
201 | * Ethernet configuration | |
202 | */ | |
203 | #define CONFIG_MPC5xxx_FEC 1 | |
86321fc1 | 204 | #define CONFIG_MPC5xxx_FEC_MII100 |
a87589da | 205 | #define CONFIG_PHY_ADDR 0x00 |
8d7e2732 | 206 | #define CONFIG_MII 1 /* MII PHY management */ |
a87589da WD |
207 | |
208 | /* | |
209 | * GPIO configuration | |
210 | */ | |
6d0f6bcf | 211 | #define CONFIG_SYS_GPS_PORT_CONFIG 0x01051004 |
a87589da | 212 | |
a87589da WD |
213 | /* |
214 | * Miscellaneous configurable options | |
215 | */ | |
6d0f6bcf | 216 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
48d5d102 | 217 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 218 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
a87589da | 219 | #else |
6d0f6bcf | 220 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
a87589da | 221 | #endif |
6d0f6bcf JCPV |
222 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
223 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
224 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
a87589da | 225 | |
6d0f6bcf | 226 | #define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ |
48d5d102 | 227 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 228 | # define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ |
48d5d102 JL |
229 | #endif |
230 | ||
a87589da | 231 | /* Enable an alternate, more extensive memory test */ |
6d0f6bcf | 232 | #define CONFIG_SYS_ALT_MEMTEST |
a87589da | 233 | |
6d0f6bcf JCPV |
234 | #define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ |
235 | #define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ | |
a87589da | 236 | |
6d0f6bcf | 237 | #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ |
a87589da | 238 | |
a87589da | 239 | /* |
7f5c0157 | 240 | * Enable loopw command. |
a87589da WD |
241 | */ |
242 | #define CONFIG_LOOPW | |
243 | ||
244 | /* | |
245 | * Various low-level settings | |
246 | */ | |
6d0f6bcf JCPV |
247 | #define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI |
248 | #define CONFIG_SYS_HID0_FINAL HID0_ICE | |
a87589da | 249 | |
6d0f6bcf JCPV |
250 | #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE |
251 | #define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE | |
252 | #define CONFIG_SYS_BOOTCS_CFG 0x0004FB00 | |
253 | #define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE | |
254 | #define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE | |
a87589da WD |
255 | |
256 | /* 8Mbit SRAM @0x80100000 */ | |
6d0f6bcf JCPV |
257 | #define CONFIG_SYS_CS1_START 0x80100000 |
258 | #define CONFIG_SYS_CS1_SIZE 0x00100000 | |
259 | #define CONFIG_SYS_CS1_CFG 0x19B00 | |
a87589da WD |
260 | |
261 | /* FRAM 32Kbyte @0x80700000 */ | |
6d0f6bcf JCPV |
262 | #define CONFIG_SYS_CS2_START 0x80700000 |
263 | #define CONFIG_SYS_CS2_SIZE 0x00008000 | |
264 | #define CONFIG_SYS_CS2_CFG 0x19800 | |
a87589da WD |
265 | |
266 | /* Display H1, Status Inputs, EPLD @0x80600000 */ | |
6d0f6bcf JCPV |
267 | #define CONFIG_SYS_CS3_START 0x80600000 |
268 | #define CONFIG_SYS_CS3_SIZE 0x00100000 | |
269 | #define CONFIG_SYS_CS3_CFG 0x00019800 | |
a87589da | 270 | |
6d0f6bcf JCPV |
271 | #define CONFIG_SYS_CS_BURST 0x00000000 |
272 | #define CONFIG_SYS_CS_DEADCYCLE 0x33333333 | |
a87589da | 273 | |
08abe158 WD |
274 | /*----------------------------------------------------------------------- |
275 | * IDE/ATA stuff Supports IDE harddisk | |
276 | *----------------------------------------------------------------------- | |
277 | */ | |
278 | ||
279 | #undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */ | |
280 | ||
281 | #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ | |
282 | #undef CONFIG_IDE_LED /* LED for ide not supported */ | |
283 | ||
6d0f6bcf JCPV |
284 | #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ |
285 | #define CONFIG_SYS_IDE_MAXDEVICE 2 /* max. 2 drives per IDE bus */ | |
08abe158 | 286 | |
9d3338d2 WD |
287 | #define CONFIG_IDE_PREINIT 1 |
288 | ||
6d0f6bcf | 289 | #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 |
08abe158 | 290 | |
6d0f6bcf | 291 | #define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA |
08abe158 WD |
292 | |
293 | /* Offset for data I/O */ | |
6d0f6bcf | 294 | #define CONFIG_SYS_ATA_DATA_OFFSET (0x0060) |
08abe158 WD |
295 | |
296 | /* Offset for normal register accesses */ | |
6d0f6bcf | 297 | #define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET) |
08abe158 WD |
298 | |
299 | /* Offset for alternate registers */ | |
6d0f6bcf | 300 | #define CONFIG_SYS_ATA_ALT_OFFSET (0x005C) |
08abe158 WD |
301 | |
302 | /* Interval between registers */ | |
6d0f6bcf | 303 | #define CONFIG_SYS_ATA_STRIDE 4 |
08abe158 WD |
304 | |
305 | #define CONFIG_ATAPI 1 | |
306 | ||
ccd9d3d6 WD |
307 | #define CONFIG_VIDEO_SMI_LYNXEM |
308 | #define CONFIG_CFB_CONSOLE | |
309 | #define CONFIG_VGA_AS_SINGLE_DEVICE | |
310 | #define CONFIG_VIDEO_LOGO | |
311 | ||
98128f38 WD |
312 | /* |
313 | * PCI Mapping: | |
314 | * 0x40000000 - 0x4fffffff - PCI Memory | |
315 | * 0x50000000 - 0x50ffffff - PCI IO Space | |
316 | */ | |
317 | #define CONFIG_PCI 1 | |
318 | #define CONFIG_PCI_PNP 1 | |
319 | #define CONFIG_PCI_SCAN_SHOW 1 | |
f33fca22 | 320 | #define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1 |
98128f38 WD |
321 | |
322 | #define CONFIG_PCI_MEM_BUS 0x40000000 | |
323 | #define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS | |
324 | #define CONFIG_PCI_MEM_SIZE 0x10000000 | |
325 | ||
326 | #define CONFIG_PCI_IO_BUS 0x50000000 | |
327 | #define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS | |
328 | #define CONFIG_PCI_IO_SIZE 0x01000000 | |
329 | ||
6d0f6bcf | 330 | #define CONFIG_SYS_ISA_IO CONFIG_PCI_IO_BUS |
ccd9d3d6 | 331 | |
9f96ae44 WD |
332 | /*---------------------------------------------------------------------*/ |
333 | /* Display addresses */ | |
334 | /*---------------------------------------------------------------------*/ | |
335 | ||
7f0d241d | 336 | #define CONFIG_PDSP188x |
6d0f6bcf JCPV |
337 | #define CONFIG_SYS_DISP_CHR_RAM (CONFIG_SYS_DISPLAY_BASE + 0x38) |
338 | #define CONFIG_SYS_DISP_CWORD (CONFIG_SYS_DISPLAY_BASE + 0x30) | |
9f96ae44 | 339 | |
a87589da | 340 | #endif /* __CONFIG_H */ |