[people/ms/u-boot.git] / include / configs / igep00x0.h

/*
 * Common configuration settings for IGEP technology based boards
 *
 * (C) Copyright 2012
 * ISEE 2007 SL, <www.iseebcn.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __IGEP00X0_H
#define __IGEP00X0_H

#include <asm/sizes.h>

/*
 * High Level Configuration Options
 */
#define CONFIG_OMAP		1	/* in a TI OMAP core */
#define CONFIG_OMAP34XX		1	/* which is a 34XX */
#define CONFIG_OMAP_GPIO
#define CONFIG_OMAP_COMMON

#define CONFIG_SDRC	/* The chip has SDRC controller */

#include <asm/arch/cpu.h>
#include <asm/arch/omap3.h>
#include <asm/mach-types.h>

/*
 * Display CPU and Board information
 */
#define CONFIG_DISPLAY_CPUINFO		1
#define CONFIG_DISPLAY_BOARDINFO	1

/* Clock Defines */
#define V_OSCK			26000000	/* Clock output from T2 */
#define V_SCLK			(V_OSCK >> 1)

#define CONFIG_MISC_INIT_R

#define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS	1
#define CONFIG_INITRD_TAG		1
#define CONFIG_REVISION_TAG		1

#define CONFIG_OF_LIBFDT
#define CONFIG_CMD_BOOTZ
#define CONFIG_SUPPORT_RAW_INITRD

/*
 * NS16550 Configuration
 */

#define V_NS16550_CLK			48000000	/* 48MHz (APLL96/2) */

#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
#define CONFIG_SYS_NS16550_CLK		V_NS16550_CLK

/* select serial console configuration */
#define CONFIG_CONS_INDEX		3
#define CONFIG_SYS_NS16550_COM3		OMAP34XX_UART3
#define CONFIG_SERIAL3			3

/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_BAUDRATE			115200
#define CONFIG_SYS_BAUDRATE_TABLE	{4800, 9600, 19200, 38400, 57600, \
					115200}
#define CONFIG_GENERIC_MMC		1
#define CONFIG_MMC			1
#define CONFIG_OMAP_HSMMC		1
#define CONFIG_DOS_PARTITION		1

/* define to enable boot progress via leds */
#if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0020) || \
    (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0030)
#define CONFIG_SHOW_BOOT_PROGRESS
#endif

/* USB */
#define CONFIG_MUSB_UDC			1
#define CONFIG_USB_OMAP3		1
#define CONFIG_TWL4030_USB		1

/* USB device configuration */
#define CONFIG_USB_DEVICE		1
#define CONFIG_USB_TTY			1
#define CONFIG_SYS_CONSOLE_IS_IN_ENV	1

/* Change these to suit your needs */
#define CONFIG_USBD_VENDORID		0x0451
#define CONFIG_USBD_PRODUCTID		0x5678
#define CONFIG_USBD_MANUFACTURER	"Texas Instruments"
#define CONFIG_USBD_PRODUCT_NAME	"IGEP"

/* commands to include */
#include <config_cmd_default.h>

#define CONFIG_CMD_CACHE
#define CONFIG_CMD_EXT4
#define CONFIG_CMD_FAT		/* FAT support			*/
#define CONFIG_CMD_FS_GENERIC
#define CONFIG_CMD_I2C		/* I2C serial bus support	*/
#define CONFIG_CMD_MMC		/* MMC support			*/
#ifdef CONFIG_BOOT_ONENAND
#define CONFIG_CMD_ONENAND	/* ONENAND support		*/
#endif
#ifdef CONFIG_BOOT_NAND
#define CONFIG_CMD_NAND
#endif
#if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0020) || \
    (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0032)
#define CONFIG_CMD_NET		/* bootp, tftpboot, rarpboot	*/
#endif
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_PING
#define CONFIG_CMD_NFS		/* NFS support			*/
#define CONFIG_CMD_MTDPARTS	/* Enable MTD parts commands	*/
#define CONFIG_MTD_DEVICE

#undef CONFIG_CMD_FLASH		/* flinfo, erase, protect	*/
#undef CONFIG_CMD_IMLS		/* List all found images	*/

#define CONFIG_SYS_NO_FLASH
#define CONFIG_HARD_I2C			1
#define CONFIG_SYS_I2C_SPEED		100000
#define CONFIG_SYS_I2C_SLAVE		1
#define CONFIG_DRIVER_OMAP34XX_I2C	1

/*
 * TWL4030
 */
#define CONFIG_TWL4030_POWER		1

#define CONFIG_BOOTDELAY		3

#define CONFIG_EXTRA_ENV_SETTINGS \
	"usbtty=cdc_acm\0" \
	"loadaddr=0x82000000\0" \
	"dtbaddr=0x81600000\0" \
	"bootdir=/boot\0" \
	"bootfile=zImage\0" \
	"usbtty=cdc_acm\0" \
	"console=ttyO2,115200n8\0" \
	"mpurate=auto\0" \
	"vram=12M\0" \
	"dvimode=1024x768MR-16@60\0" \
	"defaultdisplay=dvi\0" \
	"mmcdev=0\0" \
	"mmcroot=/dev/mmcblk0p2 rw\0" \
	"mmcrootfstype=ext4 rootwait\0" \
	"nandroot=/dev/mtdblock4 rw\0" \
	"nandrootfstype=jffs2\0" \
	"mmcargs=setenv bootargs console=${console} " \
		"mpurate=${mpurate} " \
		"vram=${vram} " \
		"omapfb.mode=dvi:${dvimode} " \
		"omapfb.debug=y " \
		"omapdss.def_disp=${defaultdisplay} " \
		"root=${mmcroot} " \
		"rootfstype=${mmcrootfstype}\0" \
	"nandargs=setenv bootargs console=${console} " \
		"mpurate=${mpurate} " \
		"vram=${vram} " \
		"omapfb.mode=dvi:${dvimode} " \
		"omapfb.debug=y " \
		"omapdss.def_disp=${defaultdisplay} " \
		"root=${nandroot} " \
		"rootfstype=${nandrootfstype}\0" \
	"loadbootenv=load mmc ${mmcdev} ${loadaddr} uEnv.txt\0" \
	"importbootenv=echo Importing environment from mmc ...; " \
		"env import -t $loadaddr $filesize\0" \
	"loadzimage=load mmc ${mmcdev}:2 ${loadaddr} ${bootdir}/${bootfile}\0" \
	"loadfdt=load mmc ${mmcdev}:2 ${dtbaddr} ${bootdir}/${dtbfile}\0" \
	"mmcboot=echo Booting from mmc ...; " \
		"run mmcargs; " \
		"bootz ${loadaddr}\0" \
	"mmcbootfdt=echo Booting with DT from mmc ...; " \
		"bootz ${loadaddr} - ${dtbaddr}\0" \
	"nandboot=echo Booting from onenand ...; " \
		"run nandargs; " \
		"onenand read ${loadaddr} 280000 400000; " \
		"bootz ${loadaddr}\0" \

#define CONFIG_BOOTCOMMAND \
	"mmc dev ${mmcdev}; if mmc rescan; then " \
		"echo SD/MMC found on device ${mmcdev};" \
		"if run loadbootenv; then " \
			"run importbootenv;" \
		"fi;" \
		"if test -n $uenvcmd; then " \
			"echo Running uenvcmd ...;" \
			"run uenvcmd;" \
		"fi;" \
		"if run loadzimage; then " \
			"if test -n $dtbfile; then " \
				"if run loadfdt; then " \
					"run mmcbootfdt;" \
				"fi;" \
			"fi;" \
			"run mmcboot;" \
		"fi;" \
	"fi;" \
	"run nandboot;" \

#define CONFIG_AUTO_COMPLETE		1

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP		/* undef to save memory */
#define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser */
#define CONFIG_SYS_PROMPT		"U-Boot # "
#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size */
/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
					sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_MAXARGS		16	/* max number of command args */
/* Boot Argument Buffer Size */
#define CONFIG_SYS_BARGSIZE		(CONFIG_SYS_CBSIZE)

#define CONFIG_SYS_MEMTEST_START	(OMAP34XX_SDRC_CS0)	/* memtest */
								/* works on */
#define CONFIG_SYS_MEMTEST_END		(OMAP34XX_SDRC_CS0 + \
					0x01F00000) /* 31MB */

#define CONFIG_SYS_LOAD_ADDR		(OMAP34XX_SDRC_CS0)	/* default */
							/* load address */

#define CONFIG_SYS_MONITOR_LEN		(256 << 10)

/*
 * OMAP3 has 12 GP timers, they can be driven by the system clock
 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
 * This rate is divided by a local divisor.
 */
#define CONFIG_SYS_TIMERBASE		(OMAP34XX_GPT2)
#define CONFIG_SYS_PTV			2       /* Divisor: 2^(PTV+1) => 8 */

/*
 * Physical Memory Map
 *
 */
#define CONFIG_NR_DRAM_BANKS	2	/* CS1 may or may not be populated */
#define PHYS_SDRAM_1		OMAP34XX_SDRC_CS0
#define PHYS_SDRAM_2		OMAP34XX_SDRC_CS1

/*
 * FLASH and environment organization
 */

#ifdef CONFIG_BOOT_ONENAND
#define PISMO1_ONEN_SIZE		GPMC_SIZE_128M /* Configure the PISMO */

#define CONFIG_SYS_ONENAND_BASE		ONENAND_MAP

#define ONENAND_ENV_OFFSET		0x260000 /* environment starts here */

#define CONFIG_ENV_IS_IN_ONENAND	1
#define CONFIG_ENV_SIZE			(512 << 10) /* Total Size Environment */
#define CONFIG_ENV_ADDR			ONENAND_ENV_OFFSET
#endif

#ifdef CONFIG_BOOT_NAND
#define PISMO1_NAND_SIZE		GPMC_SIZE_128M /* Configure the PISMO */
#define CONFIG_NAND_OMAP_GPMC
#define CONFIG_SYS_NAND_BASE		NAND_BASE
#define GPMC_NAND_ECC_LP_x16_LAYOUT	1
#define CONFIG_ENV_OFFSET		0x260000 /* environment starts here */
#define CONFIG_ENV_IS_IN_NAND	        1
#define CONFIG_ENV_SIZE			(512 << 10) /* Total Size Environment */
#define CONFIG_ENV_ADDR			NAND_ENV_OFFSET
#define CONFIG_SYS_MAX_NAND_DEVICE      1
#endif

/*
 * Size of malloc() pool
 */
#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (128 << 10))

/*
 * SMSC911x Ethernet
 */
#if defined(CONFIG_CMD_NET)
#define CONFIG_SMC911X
#define CONFIG_SMC911X_32_BIT
#define CONFIG_SMC911X_BASE	0x2C000000
#endif /* (CONFIG_CMD_NET) */

/*
 * Leave it at 0x80008000 to allow booting new u-boot.bin with X-loader
 * and older u-boot.bin with the new U-Boot SPL.
 */
#define CONFIG_SYS_TEXT_BASE		0x80008000
#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
#define CONFIG_SYS_INIT_RAM_ADDR	0x4020f800
#define CONFIG_SYS_INIT_RAM_SIZE	0x800
#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INIT_RAM_ADDR + \
					 CONFIG_SYS_INIT_RAM_SIZE - \
					 GENERATED_GBL_DATA_SIZE)

/* SPL */
#define CONFIG_SPL
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_NAND_SIMPLE
#define CONFIG_SPL_TEXT_BASE		0x40200800
#define CONFIG_SPL_MAX_SIZE		(54 * 1024)
#define CONFIG_SPL_STACK		LOW_LEVEL_SRAM_STACK

/* move malloc and bss high to prevent clashing with the main image */
#define CONFIG_SYS_SPL_MALLOC_START	0x87000000
#define CONFIG_SYS_SPL_MALLOC_SIZE	0x80000
#define CONFIG_SPL_BSS_START_ADDR	0x87080000	/* end of minimum RAM */
#define CONFIG_SPL_BSS_MAX_SIZE		0x80000		/* 512 KB */

/* MMC boot config */
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR	0x300 /* address 0x60000 */
#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS	0x200 /* 256 KB */
#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION	1
#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME	"u-boot.img"

#define CONFIG_SPL_BOARD_INIT
#define CONFIG_SPL_LIBCOMMON_SUPPORT
#define CONFIG_SPL_LIBDISK_SUPPORT
#define CONFIG_SPL_I2C_SUPPORT
#define CONFIG_SPL_LIBGENERIC_SUPPORT
#define CONFIG_SPL_MMC_SUPPORT
#define CONFIG_SPL_FAT_SUPPORT
#define CONFIG_SPL_SERIAL_SUPPORT

#define CONFIG_SPL_POWER_SUPPORT
#define CONFIG_SPL_LDSCRIPT		"$(CPUDIR)/omap-common/u-boot-spl.lds"

#ifdef CONFIG_BOOT_ONENAND
#define CONFIG_SPL_ONENAND_SUPPORT

/* OneNAND boot config */
#define CONFIG_SYS_ONENAND_U_BOOT_OFFS  0x80000
#define CONFIG_SYS_ONENAND_PAGE_SIZE	2048
#define CONFIG_SPL_ONENAND_LOAD_ADDR    0x80000
#define CONFIG_SPL_ONENAND_LOAD_SIZE    \
	(512 * 1024 - CONFIG_SPL_ONENAND_LOAD_ADDR)

#endif

#ifdef CONFIG_BOOT_NAND
#define CONFIG_SPL_NAND_SUPPORT
#define CONFIG_SPL_NAND_BASE
#define CONFIG_SPL_NAND_DRIVERS
#define CONFIG_SPL_NAND_ECC

/* NAND boot config */
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
#define CONFIG_SYS_NAND_PAGE_COUNT	64
#define CONFIG_SYS_NAND_PAGE_SIZE	2048
#define CONFIG_SYS_NAND_OOBSIZE		64
#define CONFIG_SYS_NAND_BLOCK_SIZE	(128*1024)
#define CONFIG_SYS_NAND_BAD_BLOCK_POS	0
#define CONFIG_SYS_NAND_ECCPOS		{2, 3, 4, 5, 6, 7, 8, 9,\
						10, 11, 12, 13}
#define CONFIG_SYS_NAND_ECCSIZE		512
#define CONFIG_SYS_NAND_ECCBYTES	3
#define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x80000
#endif

#endif /* __IGEP00X0_H */
Commit	Line	Data
8a3f6bb6	1	/*
dc7a9e64 EBS	2	* Common configuration settings for IGEP technology based boards
	3	*
	4	* (C) Copyright 2012
8a3f6bb6 EBS	5	* ISEE 2007 SL, <www.iseebcn.com>
8a3f6bb6 EBS	6	*
3765b3e7	7	* SPDX-License-Identifier: GPL-2.0+
8a3f6bb6 EBS	8	*/
8a3f6bb6 EBS	9
dc7a9e64 EBS	10	#ifndef __IGEP00X0_H
	11	#define __IGEP00X0_H
	12
8a3f6bb6 EBS	13	#include <asm/sizes.h>
	14
	15	/*
	16	* High Level Configuration Options
	17	*/
8a3f6bb6 EBS	18	#define CONFIG_OMAP 1 /* in a TI OMAP core */
8a3f6bb6 EBS	19	#define CONFIG_OMAP34XX 1 /* which is a 34XX */
308252ad	20	#define CONFIG_OMAP_GPIO
806d2792	21	#define CONFIG_OMAP_COMMON
8a3f6bb6 EBS	22
	23	#define CONFIG_SDRC /* The chip has SDRC controller */
	24
	25	#include <asm/arch/cpu.h>
	26	#include <asm/arch/omap3.h>
aa127df6	27	#include <asm/mach-types.h>
8a3f6bb6 EBS	28
	29	/*
	30	* Display CPU and Board information
	31	*/
	32	#define CONFIG_DISPLAY_CPUINFO 1
	33	#define CONFIG_DISPLAY_BOARDINFO 1
	34
	35	/* Clock Defines */
	36	#define V_OSCK 26000000 /* Clock output from T2 */
	37	#define V_SCLK (V_OSCK >> 1)
	38
	39	#define CONFIG_MISC_INIT_R
	40
	41	#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
	42	#define CONFIG_SETUP_MEMORY_TAGS 1
	43	#define CONFIG_INITRD_TAG 1
	44	#define CONFIG_REVISION_TAG 1
	45
e284f88b EBS	46	#define CONFIG_OF_LIBFDT
e284f88b EBS	47	#define CONFIG_CMD_BOOTZ
372d7fa1	48	#define CONFIG_SUPPORT_RAW_INITRD
2fa8ca98	49
8a3f6bb6 EBS	50	/*
	51	* NS16550 Configuration
	52	*/
	53
	54	#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
	55
	56	#define CONFIG_SYS_NS16550
	57	#define CONFIG_SYS_NS16550_SERIAL
	58	#define CONFIG_SYS_NS16550_REG_SIZE (-4)
	59	#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
	60
	61	/* select serial console configuration */
	62	#define CONFIG_CONS_INDEX 3
	63	#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
	64	#define CONFIG_SERIAL3 3
	65
	66	/* allow to overwrite serial and ethaddr */
	67	#define CONFIG_ENV_OVERWRITE
	68	#define CONFIG_BAUDRATE 115200
dc7a9e64 EBS	69	#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, \
dc7a9e64 EBS	70	115200}
f49d7b6c	71	#define CONFIG_GENERIC_MMC 1
8a3f6bb6	72	#define CONFIG_MMC 1
f49d7b6c	73	#define CONFIG_OMAP_HSMMC 1
8a3f6bb6 EBS	74	#define CONFIG_DOS_PARTITION 1
8a3f6bb6 EBS	75
9d4f5421	76	/* define to enable boot progress via leds */
d9aacf41 EBS	77	#if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0020) \|\| \
d9aacf41 EBS	78	(CONFIG_MACH_TYPE == MACH_TYPE_IGEP0030)
9d4f5421	79	#define CONFIG_SHOW_BOOT_PROGRESS
d9aacf41	80	#endif
9d4f5421	81
8a3f6bb6 EBS	82	/* USB */
	83	#define CONFIG_MUSB_UDC 1
	84	#define CONFIG_USB_OMAP3 1
	85	#define CONFIG_TWL4030_USB 1
	86
	87	/* USB device configuration */
	88	#define CONFIG_USB_DEVICE 1
	89	#define CONFIG_USB_TTY 1
	90	#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1
	91
	92	/* Change these to suit your needs */
	93	#define CONFIG_USBD_VENDORID 0x0451
	94	#define CONFIG_USBD_PRODUCTID 0x5678
	95	#define CONFIG_USBD_MANUFACTURER "Texas Instruments"
	96	#define CONFIG_USBD_PRODUCT_NAME "IGEP"
	97
	98	/* commands to include */
	99	#include <config_cmd_default.h>
	100
	101	#define CONFIG_CMD_CACHE
2be6bed0	102	#define CONFIG_CMD_EXT4
8a3f6bb6	103	#define CONFIG_CMD_FAT /* FAT support */
2be6bed0	104	#define CONFIG_CMD_FS_GENERIC
8a3f6bb6 EBS	105	#define CONFIG_CMD_I2C /* I2C serial bus support */
8a3f6bb6 EBS	106	#define CONFIG_CMD_MMC /* MMC support */
ca511cfb	107	#ifdef CONFIG_BOOT_ONENAND
8a3f6bb6	108	#define CONFIG_CMD_ONENAND /* ONENAND support */
ca511cfb JMC	109	#endif
	110	#ifdef CONFIG_BOOT_NAND
	111	#define CONFIG_CMD_NAND
	112	#endif
d9aacf41 EBS	113	#if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0020) \|\| \
d9aacf41 EBS	114	(CONFIG_MACH_TYPE == MACH_TYPE_IGEP0032)
8a3f6bb6	115	#define CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */
77eea280	116	#endif
8a3f6bb6 EBS	117	#define CONFIG_CMD_DHCP
	118	#define CONFIG_CMD_PING
	119	#define CONFIG_CMD_NFS /* NFS support */
	120	#define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */
	121	#define CONFIG_MTD_DEVICE
	122
	123	#undef CONFIG_CMD_FLASH /* flinfo, erase, protect */
	124	#undef CONFIG_CMD_IMLS /* List all found images */
	125
	126	#define CONFIG_SYS_NO_FLASH
	127	#define CONFIG_HARD_I2C 1
	128	#define CONFIG_SYS_I2C_SPEED 100000
	129	#define CONFIG_SYS_I2C_SLAVE 1
8a3f6bb6 EBS	130	#define CONFIG_DRIVER_OMAP34XX_I2C 1
	131
	132	/*
	133	* TWL4030
	134	*/
	135	#define CONFIG_TWL4030_POWER 1
	136
8a3f6bb6 EBS	137	#define CONFIG_BOOTDELAY 3
	138
	139	#define CONFIG_EXTRA_ENV_SETTINGS \
304a46ca EBS	140	"usbtty=cdc_acm\0" \
304a46ca EBS	141	"loadaddr=0x82000000\0" \
a2fa28bc JMC	142	"dtbaddr=0x81600000\0" \
	143	"bootdir=/boot\0" \
	144	"bootfile=zImage\0" \
304a46ca	145	"usbtty=cdc_acm\0" \
e5e73c17	146	"console=ttyO2,115200n8\0" \
f1e445c3	147	"mpurate=auto\0" \
304a46ca EBS	148	"vram=12M\0" \
	149	"dvimode=1024x768MR-16@60\0" \
	150	"defaultdisplay=dvi\0" \
	151	"mmcdev=0\0" \
	152	"mmcroot=/dev/mmcblk0p2 rw\0" \
b4ebeb86	153	"mmcrootfstype=ext4 rootwait\0" \
304a46ca EBS	154	"nandroot=/dev/mtdblock4 rw\0" \
	155	"nandrootfstype=jffs2\0" \
	156	"mmcargs=setenv bootargs console=${console} " \
	157	"mpurate=${mpurate} " \
	158	"vram=${vram} " \
	159	"omapfb.mode=dvi:${dvimode} " \
	160	"omapfb.debug=y " \
	161	"omapdss.def_disp=${defaultdisplay} " \
	162	"root=${mmcroot} " \
	163	"rootfstype=${mmcrootfstype}\0" \
	164	"nandargs=setenv bootargs console=${console} " \
	165	"mpurate=${mpurate} " \
	166	"vram=${vram} " \
	167	"omapfb.mode=dvi:${dvimode} " \
	168	"omapfb.debug=y " \
	169	"omapdss.def_disp=${defaultdisplay} " \
	170	"root=${nandroot} " \
	171	"rootfstype=${nandrootfstype}\0" \
2be6bed0	172	"loadbootenv=load mmc ${mmcdev} ${loadaddr} uEnv.txt\0" \
1b8ec016 EBS	173	"importbootenv=echo Importing environment from mmc ...; " \
1b8ec016 EBS	174	"env import -t $loadaddr $filesize\0" \
a2fa28bc JMC	175	"loadzimage=load mmc ${mmcdev}:2 ${loadaddr} ${bootdir}/${bootfile}\0" \
a2fa28bc JMC	176	"loadfdt=load mmc ${mmcdev}:2 ${dtbaddr} ${bootdir}/${dtbfile}\0" \
304a46ca EBS	177	"mmcboot=echo Booting from mmc ...; " \
304a46ca EBS	178	"run mmcargs; " \
2be6bed0	179	"bootz ${loadaddr}\0" \
a2fa28bc JMC	180	"mmcbootfdt=echo Booting with DT from mmc ...; " \
a2fa28bc JMC	181	"bootz ${loadaddr} - ${dtbaddr}\0" \
304a46ca EBS	182	"nandboot=echo Booting from onenand ...; " \
	183	"run nandargs; " \
	184	"onenand read ${loadaddr} 280000 400000; " \
2be6bed0	185	"bootz ${loadaddr}\0" \
304a46ca EBS	186
304a46ca EBS	187	#define CONFIG_BOOTCOMMAND \
66968110	188	"mmc dev ${mmcdev}; if mmc rescan; then " \
1b8ec016 EBS	189	"echo SD/MMC found on device ${mmcdev};" \
	190	"if run loadbootenv; then " \
	191	"run importbootenv;" \
	192	"fi;" \
	193	"if test -n $uenvcmd; then " \
	194	"echo Running uenvcmd ...;" \
	195	"run uenvcmd;" \
	196	"fi;" \
2be6bed0	197	"if run loadzimage; then " \
a2fa28bc JMC	198	"if test -n $dtbfile; then " \
	199	"if run loadfdt; then " \
	200	"run mmcbootfdt;" \
	201	"fi;" \
	202	"fi;" \
1b8ec016 EBS	203	"run mmcboot;" \
	204	"fi;" \
	205	"fi;" \
	206	"run nandboot;" \
8a3f6bb6 EBS	207
	208	#define CONFIG_AUTO_COMPLETE 1
	209
	210	/*
	211	* Miscellaneous configurable options
	212	*/
	213	#define CONFIG_SYS_LONGHELP /* undef to save memory */
	214	#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
8a3f6bb6 EBS	215	#define CONFIG_SYS_PROMPT "U-Boot # "
	216	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
	217	/* Print Buffer Size */
	218	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
	219	sizeof(CONFIG_SYS_PROMPT) + 16)
	220	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	221	/* Boot Argument Buffer Size */
	222	#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
	223
	224	#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) /* memtest */
	225	/* works on */
	226	#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \
	227	0x01F00000) /* 31MB */
	228
	229	#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default */
	230	/* load address */
	231
	232	#define CONFIG_SYS_MONITOR_LEN (256 << 10)
	233
	234	/*
	235	* OMAP3 has 12 GP timers, they can be driven by the system clock
	236	* (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
	237	* This rate is divided by a local divisor.
	238	*/
	239	#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
	240	#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
8a3f6bb6	241
8a3f6bb6 EBS	242	/*
	243	* Physical Memory Map
	244	*
	245	*/
	246	#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
	247	#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
8a3f6bb6 EBS	248	#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
8a3f6bb6 EBS	249
8a3f6bb6 EBS	250	/*
	251	* FLASH and environment organization
	252	*/
	253
ca511cfb	254	#ifdef CONFIG_BOOT_ONENAND
8a3f6bb6 EBS	255	#define PISMO1_ONEN_SIZE GPMC_SIZE_128M /* Configure the PISMO */
	256
	257	#define CONFIG_SYS_ONENAND_BASE ONENAND_MAP
	258
	259	#define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */
	260
	261	#define CONFIG_ENV_IS_IN_ONENAND 1
	262	#define CONFIG_ENV_SIZE (512 << 10) /* Total Size Environment */
	263	#define CONFIG_ENV_ADDR ONENAND_ENV_OFFSET
ca511cfb JMC	264	#endif
	265
	266	#ifdef CONFIG_BOOT_NAND
	267	#define PISMO1_NAND_SIZE GPMC_SIZE_128M /* Configure the PISMO */
	268	#define CONFIG_NAND_OMAP_GPMC
	269	#define CONFIG_SYS_NAND_BASE NAND_BASE
	270	#define GPMC_NAND_ECC_LP_x16_LAYOUT 1
	271	#define CONFIG_ENV_OFFSET 0x260000 /* environment starts here */
	272	#define CONFIG_ENV_IS_IN_NAND 1
	273	#define CONFIG_ENV_SIZE (512 << 10) /* Total Size Environment */
	274	#define CONFIG_ENV_ADDR NAND_ENV_OFFSET
	275	#define CONFIG_SYS_MAX_NAND_DEVICE 1
	276	#endif
8a3f6bb6 EBS	277
	278	/*
	279	* Size of malloc() pool
	280	*/
	281	#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10))
8a3f6bb6 EBS	282
	283	/*
	284	* SMSC911x Ethernet
	285	*/
	286	#if defined(CONFIG_CMD_NET)
8a3f6bb6 EBS	287	#define CONFIG_SMC911X
	288	#define CONFIG_SMC911X_32_BIT
	289	#define CONFIG_SMC911X_BASE 0x2C000000
	290	#endif /* (CONFIG_CMD_NET) */
	291
d271a611 JMC	292	/*
	293	* Leave it at 0x80008000 to allow booting new u-boot.bin with X-loader
	294	* and older u-boot.bin with the new U-Boot SPL.
	295	*/
	296	#define CONFIG_SYS_TEXT_BASE 0x80008000
8a3f6bb6	297	#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
31bfcf1c SS	298	#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
	299	#define CONFIG_SYS_INIT_RAM_SIZE 0x800
	300	#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
	301	CONFIG_SYS_INIT_RAM_SIZE - \
	302	GENERATED_GBL_DATA_SIZE)
8a3f6bb6	303
d271a611 JMC	304	/* SPL */
d271a611 JMC	305	#define CONFIG_SPL
47f7bcae	306	#define CONFIG_SPL_FRAMEWORK
d271a611 JMC	307	#define CONFIG_SPL_NAND_SIMPLE
	308	#define CONFIG_SPL_TEXT_BASE 0x40200800
	309	#define CONFIG_SPL_MAX_SIZE (54 * 1024)
	310	#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK
	311
	312	/* move malloc and bss high to prevent clashing with the main image */
	313	#define CONFIG_SYS_SPL_MALLOC_START 0x87000000
	314	#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000
	315	#define CONFIG_SPL_BSS_START_ADDR 0x87080000 /* end of minimum RAM */
	316	#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */
	317
	318	/* MMC boot config */
	319	#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
	320	#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */
	321	#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1
	322	#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img"
	323
0e29a248	324	#define CONFIG_SPL_BOARD_INIT
d271a611 JMC	325	#define CONFIG_SPL_LIBCOMMON_SUPPORT
	326	#define CONFIG_SPL_LIBDISK_SUPPORT
	327	#define CONFIG_SPL_I2C_SUPPORT
	328	#define CONFIG_SPL_LIBGENERIC_SUPPORT
	329	#define CONFIG_SPL_MMC_SUPPORT
	330	#define CONFIG_SPL_FAT_SUPPORT
	331	#define CONFIG_SPL_SERIAL_SUPPORT
	332
	333	#define CONFIG_SPL_POWER_SUPPORT
	334	#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
	335
	336	#ifdef CONFIG_BOOT_ONENAND
	337	#define CONFIG_SPL_ONENAND_SUPPORT
	338
	339	/* OneNAND boot config */
	340	#define CONFIG_SYS_ONENAND_U_BOOT_OFFS 0x80000
	341	#define CONFIG_SYS_ONENAND_PAGE_SIZE 2048
	342	#define CONFIG_SPL_ONENAND_LOAD_ADDR 0x80000
	343	#define CONFIG_SPL_ONENAND_LOAD_SIZE \
	344	(512 * 1024 - CONFIG_SPL_ONENAND_LOAD_ADDR)
	345
	346	#endif
	347
	348	#ifdef CONFIG_BOOT_NAND
	349	#define CONFIG_SPL_NAND_SUPPORT
6f2f01b9 SW	350	#define CONFIG_SPL_NAND_BASE
	351	#define CONFIG_SPL_NAND_DRIVERS
	352	#define CONFIG_SPL_NAND_ECC
d271a611 JMC	353
	354	/* NAND boot config */
	355	#define CONFIG_SYS_NAND_5_ADDR_CYCLE
	356	#define CONFIG_SYS_NAND_PAGE_COUNT 64
	357	#define CONFIG_SYS_NAND_PAGE_SIZE 2048
	358	#define CONFIG_SYS_NAND_OOBSIZE 64
	359	#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
	360	#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
	361	#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\
	362	10, 11, 12, 13}
	363	#define CONFIG_SYS_NAND_ECCSIZE 512
	364	#define CONFIG_SYS_NAND_ECCBYTES 3
	365	#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
	366	#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
	367	#endif
	368
dc7a9e64	369	#endif /* __IGEP00X0_H */