[people/ms/u-boot.git] / include / configs / ls1021atwr.h

/*
 * Copyright 2014 Freescale Semiconductor, Inc.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __CONFIG_H
#define __CONFIG_H

#define CONFIG_LS102XA

#define CONFIG_ARMV7_PSCI_1_0

#define CONFIG_ARMV7_SECURE_BASE	OCRAM_BASE_S_ADDR

#define CONFIG_SYS_FSL_CLK

#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO

#define CONFIG_SKIP_LOWLEVEL_INIT
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_DEEP_SLEEP
#ifdef CONFIG_DEEP_SLEEP
#define CONFIG_SILENT_CONSOLE
#endif

/*
 * Size of malloc() pool
 */
#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 16 * 1024 * 1024)

#define CONFIG_SYS_INIT_RAM_ADDR	OCRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE	OCRAM_SIZE

/*
 * USB
 */

/*
 * EHCI Support - disbaled by default as
 * there is no signal coming out of soc on
 * this board for this controller. However,
 * the silicon still has this controller,
 * and anyone can use this controller by
 * taking signals out on their board.
 */

/*#define CONFIG_HAS_FSL_DR_USB*/

#ifdef CONFIG_HAS_FSL_DR_USB
#define CONFIG_USB_EHCI
#define CONFIG_USB_EHCI_FSL
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
#endif

/* XHCI Support - enabled by default */
#define CONFIG_HAS_FSL_XHCI_USB

#ifdef CONFIG_HAS_FSL_XHCI_USB
#define CONFIG_USB_XHCI_FSL
#define CONFIG_USB_MAX_CONTROLLER_COUNT        1
#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS     2
#endif

/*
 * Generic Timer Definitions
 */
#define GENERIC_TIMER_CLK		12500000

#define CONFIG_SYS_CLK_FREQ		100000000
#define CONFIG_DDR_CLK_FREQ		100000000

#define DDR_SDRAM_CFG			0x470c0008
#define DDR_CS0_BNDS			0x008000bf
#define DDR_CS0_CONFIG			0x80014302
#define DDR_TIMING_CFG_0		0x50550004
#define DDR_TIMING_CFG_1		0xbcb38c56
#define DDR_TIMING_CFG_2		0x0040d120
#define DDR_TIMING_CFG_3		0x010e1000
#define DDR_TIMING_CFG_4		0x00000001
#define DDR_TIMING_CFG_5		0x03401400
#define DDR_SDRAM_CFG_2			0x00401010
#define DDR_SDRAM_MODE			0x00061c60
#define DDR_SDRAM_MODE_2		0x00180000
#define DDR_SDRAM_INTERVAL		0x18600618
#define DDR_DDR_WRLVL_CNTL		0x8655f605
#define DDR_DDR_WRLVL_CNTL_2		0x05060607
#define DDR_DDR_WRLVL_CNTL_3		0x05050505
#define DDR_DDR_CDR1			0x80040000
#define DDR_DDR_CDR2			0x00000001
#define DDR_SDRAM_CLK_CNTL		0x02000000
#define DDR_DDR_ZQ_CNTL			0x89080600
#define DDR_CS0_CONFIG_2		0
#define DDR_SDRAM_CFG_MEM_EN		0x80000000
#define SDRAM_CFG2_D_INIT		0x00000010
#define DDR_CDR2_VREF_TRAIN_EN		0x00000080
#define SDRAM_CFG2_FRC_SR		0x80000000
#define SDRAM_CFG_BI			0x00000001

#ifdef CONFIG_RAMBOOT_PBL
#define CONFIG_SYS_FSL_PBL_PBI	board/freescale/ls1021atwr/ls102xa_pbi.cfg
#endif

#ifdef CONFIG_SD_BOOT
#ifdef CONFIG_SD_BOOT_QSPI
#define CONFIG_SYS_FSL_PBL_RCW	\
	board/freescale/ls1021atwr/ls102xa_rcw_sd_qspi.cfg
#else
#define CONFIG_SYS_FSL_PBL_RCW	\
	board/freescale/ls1021atwr/ls102xa_rcw_sd_ifc.cfg
#endif
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_LDSCRIPT	"arch/$(ARCH)/cpu/u-boot-spl.lds"
#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
#define CONFIG_SPL_WATCHDOG_SUPPORT
#define CONFIG_SPL_SERIAL_SUPPORT
#define CONFIG_SPL_MMC_SUPPORT
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR		0xe8

#ifdef CONFIG_SECURE_BOOT
#define CONFIG_U_BOOT_HDR_SIZE				(16 << 10)
/*
 * HDR would be appended at end of image and copied to DDR along
 * with U-Boot image.
 */
#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS		(0x400 + \
		(CONFIG_U_BOOT_HDR_SIZE / 512)
#else
#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS		0x400
#endif /* ifdef CONFIG_SECURE_BOOT */

#define CONFIG_SPL_TEXT_BASE		0x10000000
#define CONFIG_SPL_MAX_SIZE		0x1a000
#define CONFIG_SPL_STACK		0x1001d000
#define CONFIG_SPL_PAD_TO		0x1c000
#define CONFIG_SYS_TEXT_BASE		0x82000000

#define CONFIG_SYS_SPL_MALLOC_START	(CONFIG_SYS_TEXT_BASE + \
		CONFIG_SYS_MONITOR_LEN)
#define CONFIG_SYS_SPL_MALLOC_SIZE	0x100000
#define CONFIG_SPL_BSS_START_ADDR	0x80100000
#define CONFIG_SPL_BSS_MAX_SIZE		0x80000

#ifdef CONFIG_U_BOOT_HDR_SIZE
/*
 * HDR would be appended at end of image and copied to DDR along
 * with U-Boot image. Here u-boot max. size is 512K. So if binary
 * size increases then increase this size in case of secure boot as
 * it uses raw u-boot image instead of fit image.
 */
#define CONFIG_SYS_MONITOR_LEN		(0x80000 + CONFIG_U_BOOT_HDR_SIZE)
#else
#define CONFIG_SYS_MONITOR_LEN		0x80000
#endif /* ifdef CONFIG_U_BOOT_HDR_SIZE */
#endif

#ifdef CONFIG_QSPI_BOOT
#define CONFIG_SYS_TEXT_BASE		0x40010000
#endif

#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
#define CONFIG_SYS_NO_FLASH
#endif

#ifndef CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_TEXT_BASE		0x60100000
#endif

#define CONFIG_NR_DRAM_BANKS		1
#define PHYS_SDRAM			0x80000000
#define PHYS_SDRAM_SIZE			(1u * 1024 * 1024 * 1024)

#define CONFIG_SYS_DDR_SDRAM_BASE      0x80000000UL
#define CONFIG_SYS_SDRAM_BASE          CONFIG_SYS_DDR_SDRAM_BASE

#define CONFIG_SYS_HAS_SERDES

#define CONFIG_FSL_CAAM			/* Enable CAAM */

#if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \
	!defined(CONFIG_QSPI_BOOT)
#define CONFIG_U_QE
#endif

/*
 * IFC Definitions
 */
#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
#define CONFIG_FSL_IFC
#define CONFIG_SYS_FLASH_BASE		0x60000000
#define CONFIG_SYS_FLASH_BASE_PHYS	CONFIG_SYS_FLASH_BASE

#define CONFIG_SYS_NOR0_CSPR_EXT	(0x0)
#define CONFIG_SYS_NOR0_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
				CSPR_PORT_SIZE_16 | \
				CSPR_MSEL_NOR | \
				CSPR_V)
#define CONFIG_SYS_NOR_AMASK		IFC_AMASK(128 * 1024 * 1024)

/* NOR Flash Timing Params */
#define CONFIG_SYS_NOR_CSOR		(CSOR_NOR_ADM_SHIFT(4) | \
					CSOR_NOR_TRHZ_80)
#define CONFIG_SYS_NOR_FTIM0		(FTIM0_NOR_TACSE(0x4) | \
					FTIM0_NOR_TEADC(0x5) | \
					FTIM0_NOR_TAVDS(0x0) | \
					FTIM0_NOR_TEAHC(0x5))
#define CONFIG_SYS_NOR_FTIM1		(FTIM1_NOR_TACO(0x35) | \
					FTIM1_NOR_TRAD_NOR(0x1A) | \
					FTIM1_NOR_TSEQRAD_NOR(0x13))
#define CONFIG_SYS_NOR_FTIM2		(FTIM2_NOR_TCS(0x4) | \
					FTIM2_NOR_TCH(0x4) | \
					FTIM2_NOR_TWP(0x1c) | \
					FTIM2_NOR_TWPH(0x0e))
#define CONFIG_SYS_NOR_FTIM3		0

#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
#define CONFIG_SYS_FLASH_QUIET_TEST
#define CONFIG_FLASH_SHOW_PROGRESS	45	/* count down from 45/5: 9..1 */

#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* number of banks */
#define CONFIG_SYS_MAX_FLASH_SECT	1024	/* sectors per device */
#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */

#define CONFIG_SYS_FLASH_EMPTY_INFO
#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE_PHYS }

#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
#define CONFIG_SYS_WRITE_SWAPPED_DATA
#endif

/* CPLD */

#define CONFIG_SYS_CPLD_BASE	0x7fb00000
#define CPLD_BASE_PHYS		CONFIG_SYS_CPLD_BASE

#define CONFIG_SYS_FPGA_CSPR_EXT        (0x0)
#define CONFIG_SYS_FPGA_CSPR		(CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \
					CSPR_PORT_SIZE_8 | \
					CSPR_MSEL_GPCM | \
					CSPR_V)
#define CONFIG_SYS_FPGA_AMASK		IFC_AMASK(64 * 1024)
#define CONFIG_SYS_FPGA_CSOR		(CSOR_NOR_ADM_SHIFT(4) | \
					CSOR_NOR_NOR_MODE_AVD_NOR | \
					CSOR_NOR_TRHZ_80)

/* CPLD Timing parameters for IFC GPCM */
#define CONFIG_SYS_FPGA_FTIM0		(FTIM0_GPCM_TACSE(0xf) | \
					FTIM0_GPCM_TEADC(0xf) | \
					FTIM0_GPCM_TEAHC(0xf))
#define CONFIG_SYS_FPGA_FTIM1		(FTIM1_GPCM_TACO(0xff) | \
					FTIM1_GPCM_TRAD(0x3f))
#define CONFIG_SYS_FPGA_FTIM2		(FTIM2_GPCM_TCS(0xf) | \
					FTIM2_GPCM_TCH(0xf) | \
					FTIM2_GPCM_TWP(0xff))
#define CONFIG_SYS_FPGA_FTIM3           0x0
#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NOR0_CSPR_EXT
#define CONFIG_SYS_CSPR0		CONFIG_SYS_NOR0_CSPR
#define CONFIG_SYS_AMASK0		CONFIG_SYS_NOR_AMASK
#define CONFIG_SYS_CSOR0		CONFIG_SYS_NOR_CSOR
#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NOR_FTIM0
#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NOR_FTIM1
#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NOR_FTIM2
#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NOR_FTIM3
#define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_FPGA_CSPR_EXT
#define CONFIG_SYS_CSPR1		CONFIG_SYS_FPGA_CSPR
#define CONFIG_SYS_AMASK1		CONFIG_SYS_FPGA_AMASK
#define CONFIG_SYS_CSOR1		CONFIG_SYS_FPGA_CSOR
#define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_FPGA_FTIM0
#define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_FPGA_FTIM1
#define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_FPGA_FTIM2
#define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_FPGA_FTIM3

/*
 * Serial Port
 */
#ifdef CONFIG_LPUART
#define CONFIG_LPUART_32B_REG
#else
#define CONFIG_CONS_INDEX		1
#define CONFIG_SYS_NS16550_SERIAL
#ifndef CONFIG_DM_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	1
#endif
#define CONFIG_SYS_NS16550_CLK		get_serial_clock()
#endif

#define CONFIG_BAUDRATE			115200

/*
 * I2C
 */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_MXC
#define CONFIG_SYS_I2C_MXC_I2C1		/* enable I2C bus 1 */
#define CONFIG_SYS_I2C_MXC_I2C2		/* enable I2C bus 2 */
#define CONFIG_SYS_I2C_MXC_I2C3		/* enable I2C bus 3 */

/* EEPROM */
#define CONFIG_ID_EEPROM
#define CONFIG_SYS_I2C_EEPROM_NXID
#define CONFIG_SYS_EEPROM_BUS_NUM		1
#define CONFIG_SYS_I2C_EEPROM_ADDR		0x53
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	3
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	5

/*
 * MMC
 */
#define CONFIG_MMC
#define CONFIG_FSL_ESDHC
#define CONFIG_GENERIC_MMC

#define CONFIG_DOS_PARTITION

/* SPI */
#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
/* QSPI */
#define QSPI0_AMBA_BASE			0x40000000
#define FSL_QSPI_FLASH_SIZE		(1 << 24)
#define FSL_QSPI_FLASH_NUM		2

/* DSPI */
#endif

/* DM SPI */
#if defined(CONFIG_FSL_DSPI) || defined(CONFIG_FSL_QSPI)
#define CONFIG_DM_SPI_FLASH
#endif

/*
 * Video
 */
#define CONFIG_FSL_DCU_FB

#ifdef CONFIG_FSL_DCU_FB
#define CONFIG_VIDEO
#define CONFIG_CMD_BMP
#define CONFIG_CFB_CONSOLE
#define CONFIG_VGA_AS_SINGLE_DEVICE
#define CONFIG_VIDEO_LOGO
#define CONFIG_VIDEO_BMP_LOGO
#define CONFIG_SYS_CONSOLE_IS_IN_ENV

#define CONFIG_FSL_DCU_SII9022A
#define CONFIG_SYS_I2C_DVI_BUS_NUM	1
#define CONFIG_SYS_I2C_DVI_ADDR		0x39
#endif

/*
 * eTSEC
 */
#define CONFIG_TSEC_ENET

#ifdef CONFIG_TSEC_ENET
#define CONFIG_MII
#define CONFIG_MII_DEFAULT_TSEC		1
#define CONFIG_TSEC1			1
#define CONFIG_TSEC1_NAME		"eTSEC1"
#define CONFIG_TSEC2			1
#define CONFIG_TSEC2_NAME		"eTSEC2"
#define CONFIG_TSEC3			1
#define CONFIG_TSEC3_NAME		"eTSEC3"

#define TSEC1_PHY_ADDR			2
#define TSEC2_PHY_ADDR			0
#define TSEC3_PHY_ADDR			1

#define TSEC1_FLAGS			(TSEC_GIGABIT | TSEC_REDUCED)
#define TSEC2_FLAGS			(TSEC_GIGABIT | TSEC_REDUCED)
#define TSEC3_FLAGS			(TSEC_GIGABIT | TSEC_REDUCED)

#define TSEC1_PHYIDX			0
#define TSEC2_PHYIDX			0
#define TSEC3_PHYIDX			0

#define CONFIG_ETHPRIME			"eTSEC1"

#define CONFIG_PHY_GIGE
#define CONFIG_PHYLIB
#define CONFIG_PHY_ATHEROS

#define CONFIG_HAS_ETH0
#define CONFIG_HAS_ETH1
#define CONFIG_HAS_ETH2
#endif

/* PCIe */
#define CONFIG_PCI		/* Enable PCI/PCIE */
#define CONFIG_PCIE1		/* PCIE controller 1 */
#define CONFIG_PCIE2		/* PCIE controller 2 */
#define CONFIG_PCIE_LAYERSCAPE	/* Use common FSL Layerscape PCIe code */
#define FSL_PCIE_COMPAT "fsl,ls1021a-pcie"

#define CONFIG_SYS_PCI_64BIT

#define CONFIG_SYS_PCIE_CFG0_PHYS_OFF	0x00000000
#define CONFIG_SYS_PCIE_CFG0_SIZE	0x00001000	/* 4k */
#define CONFIG_SYS_PCIE_CFG1_PHYS_OFF	0x00001000
#define CONFIG_SYS_PCIE_CFG1_SIZE	0x00001000	/* 4k */

#define CONFIG_SYS_PCIE_IO_BUS		0x00000000
#define CONFIG_SYS_PCIE_IO_PHYS_OFF	0x00010000
#define CONFIG_SYS_PCIE_IO_SIZE		0x00010000	/* 64k */

#define CONFIG_SYS_PCIE_MEM_BUS		0x08000000
#define CONFIG_SYS_PCIE_MEM_PHYS_OFF	0x04000000
#define CONFIG_SYS_PCIE_MEM_SIZE	0x08000000	/* 128M */

#ifdef CONFIG_PCI
#define CONFIG_PCI_PNP
#define CONFIG_PCI_SCAN_SHOW
#define CONFIG_CMD_PCI
#endif

#define CONFIG_CMDLINE_TAG
#define CONFIG_CMDLINE_EDITING

#define CONFIG_ARMV7_NONSEC
#define CONFIG_ARMV7_VIRT
#define CONFIG_PEN_ADDR_BIG_ENDIAN
#define CONFIG_LAYERSCAPE_NS_ACCESS
#define CONFIG_SMP_PEN_ADDR		0x01ee0200
#define CONFIG_TIMER_CLK_FREQ		12500000

#define CONFIG_HWCONFIG
#define HWCONFIG_BUFFER_SIZE		256

#define CONFIG_FSL_DEVICE_DISABLE


#ifdef CONFIG_LPUART
#define CONFIG_EXTRA_ENV_SETTINGS       \
	"bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0" \
	"initrd_high=0xffffffff\0"      \
	"fdt_high=0xffffffff\0"
#else
#define CONFIG_EXTRA_ENV_SETTINGS	\
	"bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \
	"initrd_high=0xffffffff\0"      \
	"fdt_high=0xffffffff\0"
#endif

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP		/* undef to save memory */
#define CONFIG_AUTO_COMPLETE
#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size */
#define CONFIG_SYS_PBSIZE		\
		(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_MAXARGS		16	/* max number of command args */
#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE

#define CONFIG_SYS_MEMTEST_START	0x80000000
#define CONFIG_SYS_MEMTEST_END		0x9fffffff

#define CONFIG_SYS_LOAD_ADDR		0x82000000

#define CONFIG_LS102XA_STREAM_ID

/*
 * Stack sizes
 * The stack sizes are set up in start.S using the settings below
 */
#define CONFIG_STACKSIZE		(30 * 1024)

#define CONFIG_SYS_INIT_SP_OFFSET \
	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_ADDR \
	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)

#ifdef CONFIG_SPL_BUILD
#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
#else
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
#endif

#define CONFIG_SYS_QE_FW_ADDR     0x600c0000

/*
 * Environment
 */
#define CONFIG_ENV_OVERWRITE

#if defined(CONFIG_SD_BOOT)
#define CONFIG_ENV_OFFSET		0x100000
#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_MMC_ENV_DEV		0
#define CONFIG_ENV_SIZE			0x20000
#elif defined(CONFIG_QSPI_BOOT)
#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_SIZE			0x2000
#define CONFIG_ENV_OFFSET		0x100000
#define CONFIG_ENV_SECT_SIZE		0x10000
#else
#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_SIZE			0x20000
#define CONFIG_ENV_SECT_SIZE		0x20000 /* 128K (one sector) */
#endif

#define CONFIG_MISC_INIT_R

/* Hash command with SHA acceleration supported in hardware */
#ifdef CONFIG_FSL_CAAM
#define CONFIG_CMD_HASH
#define CONFIG_SHA_HW_ACCEL
#endif

#include <asm/fsl_secure_boot.h>
#define CONFIG_SYS_BOOTM_LEN	(64 << 20) /* Increase max gunzip size */

#endif
Commit	Line	Data
c8a7d9da WH	1	/*
	2	* Copyright 2014 Freescale Semiconductor, Inc.
	3	*
	4	* SPDX-License-Identifier: GPL-2.0+
	5	*/
	6
	7	#ifndef __CONFIG_H
	8	#define __CONFIG_H
	9
c8a7d9da WH	10	#define CONFIG_LS102XA
c8a7d9da WH	11
aeb901f2	12	#define CONFIG_ARMV7_PSCI_1_0
340848b1	13
3288628a HZ	14	#define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR
3288628a HZ	15
18fb0e3c	16	#define CONFIG_SYS_FSL_CLK
c8a7d9da WH	17
	18	#define CONFIG_DISPLAY_CPUINFO
	19	#define CONFIG_DISPLAY_BOARDINFO
	20
	21	#define CONFIG_SKIP_LOWLEVEL_INIT
	22	#define CONFIG_BOARD_EARLY_INIT_F
99e1bd42 TY	23	#define CONFIG_DEEP_SLEEP
	24	#ifdef CONFIG_DEEP_SLEEP
	25	#define CONFIG_SILENT_CONSOLE
	26	#endif
c8a7d9da WH	27
	28	/*
	29	* Size of malloc() pool
	30	*/
	31	#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024 * 1024)
	32
	33	#define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR
	34	#define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE
	35
10a28644 RM	36	/*
	37	* USB
	38	*/
	39
	40	/*
	41	* EHCI Support - disbaled by default as
	42	* there is no signal coming out of soc on
	43	* this board for this controller. However,
	44	* the silicon still has this controller,
	45	* and anyone can use this controller by
	46	* taking signals out on their board.
	47	*/
	48
	49	/#define CONFIG_HAS_FSL_DR_USB/
	50
	51	#ifdef CONFIG_HAS_FSL_DR_USB
	52	#define CONFIG_USB_EHCI
	53	#define CONFIG_USB_EHCI_FSL
	54	#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
	55	#endif
	56
	57	/* XHCI Support - enabled by default */
	58	#define CONFIG_HAS_FSL_XHCI_USB
	59
	60	#ifdef CONFIG_HAS_FSL_XHCI_USB
	61	#define CONFIG_USB_XHCI_FSL
10a28644 RM	62	#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
	63	#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
	64	#endif
	65
c8a7d9da WH	66	/*
	67	* Generic Timer Definitions
	68	*/
	69	#define GENERIC_TIMER_CLK 12500000
	70
	71	#define CONFIG_SYS_CLK_FREQ 100000000
	72	#define CONFIG_DDR_CLK_FREQ 100000000
	73
a88cc3bd YS	74	#define DDR_SDRAM_CFG 0x470c0008
	75	#define DDR_CS0_BNDS 0x008000bf
	76	#define DDR_CS0_CONFIG 0x80014302
	77	#define DDR_TIMING_CFG_0 0x50550004
	78	#define DDR_TIMING_CFG_1 0xbcb38c56
	79	#define DDR_TIMING_CFG_2 0x0040d120
	80	#define DDR_TIMING_CFG_3 0x010e1000
	81	#define DDR_TIMING_CFG_4 0x00000001
	82	#define DDR_TIMING_CFG_5 0x03401400
	83	#define DDR_SDRAM_CFG_2 0x00401010
	84	#define DDR_SDRAM_MODE 0x00061c60
	85	#define DDR_SDRAM_MODE_2 0x00180000
	86	#define DDR_SDRAM_INTERVAL 0x18600618
	87	#define DDR_DDR_WRLVL_CNTL 0x8655f605
	88	#define DDR_DDR_WRLVL_CNTL_2 0x05060607
	89	#define DDR_DDR_WRLVL_CNTL_3 0x05050505
	90	#define DDR_DDR_CDR1 0x80040000
	91	#define DDR_DDR_CDR2 0x00000001
	92	#define DDR_SDRAM_CLK_CNTL 0x02000000
	93	#define DDR_DDR_ZQ_CNTL 0x89080600
	94	#define DDR_CS0_CONFIG_2 0
	95	#define DDR_SDRAM_CFG_MEM_EN 0x80000000
99e1bd42 TY	96	#define SDRAM_CFG2_D_INIT 0x00000010
	97	#define DDR_CDR2_VREF_TRAIN_EN 0x00000080
	98	#define SDRAM_CFG2_FRC_SR 0x80000000
	99	#define SDRAM_CFG_BI 0x00000001
a88cc3bd	100
8415bb68 AW	101	#ifdef CONFIG_RAMBOOT_PBL
	102	#define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1021atwr/ls102xa_pbi.cfg
	103	#endif
	104
	105	#ifdef CONFIG_SD_BOOT
947cee11 AW	106	#ifdef CONFIG_SD_BOOT_QSPI
	107	#define CONFIG_SYS_FSL_PBL_RCW \
	108	board/freescale/ls1021atwr/ls102xa_rcw_sd_qspi.cfg
	109	#else
	110	#define CONFIG_SYS_FSL_PBL_RCW \
	111	board/freescale/ls1021atwr/ls102xa_rcw_sd_ifc.cfg
	112	#endif
8415bb68 AW	113	#define CONFIG_SPL_FRAMEWORK
8415bb68 AW	114	#define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds"
8415bb68	115	#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
8415bb68 AW	116	#define CONFIG_SPL_WATCHDOG_SUPPORT
	117	#define CONFIG_SPL_SERIAL_SUPPORT
	118	#define CONFIG_SPL_MMC_SUPPORT
	119	#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0xe8
e7e720c2 SG	120
	121	#ifdef CONFIG_SECURE_BOOT
	122	#define CONFIG_U_BOOT_HDR_SIZE (16 << 10)
	123	/*
	124	* HDR would be appended at end of image and copied to DDR along
	125	* with U-Boot image.
	126	*/
	127	#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS (0x400 + \
	128	(CONFIG_U_BOOT_HDR_SIZE / 512)
	129	#else
8415bb68	130	#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x400
e7e720c2	131	#endif /* ifdef CONFIG_SECURE_BOOT */
8415bb68 AW	132
	133	#define CONFIG_SPL_TEXT_BASE 0x10000000
	134	#define CONFIG_SPL_MAX_SIZE 0x1a000
	135	#define CONFIG_SPL_STACK 0x1001d000
	136	#define CONFIG_SPL_PAD_TO 0x1c000
	137	#define CONFIG_SYS_TEXT_BASE 0x82000000
	138
99e1bd42 TY	139	#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE + \
99e1bd42 TY	140	CONFIG_SYS_MONITOR_LEN)
8415bb68 AW	141	#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
	142	#define CONFIG_SPL_BSS_START_ADDR 0x80100000
	143	#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
e7e720c2 SG	144
	145	#ifdef CONFIG_U_BOOT_HDR_SIZE
	146	/*
	147	* HDR would be appended at end of image and copied to DDR along
	148	* with U-Boot image. Here u-boot max. size is 512K. So if binary
	149	* size increases then increase this size in case of secure boot as
	150	* it uses raw u-boot image instead of fit image.
	151	*/
	152	#define CONFIG_SYS_MONITOR_LEN (0x80000 + CONFIG_U_BOOT_HDR_SIZE)
	153	#else
8415bb68	154	#define CONFIG_SYS_MONITOR_LEN 0x80000
e7e720c2	155	#endif /* ifdef CONFIG_U_BOOT_HDR_SIZE */
8415bb68 AW	156	#endif
8415bb68 AW	157
d612f0ab AW	158	#ifdef CONFIG_QSPI_BOOT
d612f0ab AW	159	#define CONFIG_SYS_TEXT_BASE 0x40010000
947cee11 AW	160	#endif
	161
	162	#if defined(CONFIG_QSPI_BOOT) \|\| defined(CONFIG_SD_BOOT_QSPI)
d612f0ab AW	163	#define CONFIG_SYS_NO_FLASH
	164	#endif
	165
c8a7d9da	166	#ifndef CONFIG_SYS_TEXT_BASE
1c69a51c	167	#define CONFIG_SYS_TEXT_BASE 0x60100000
c8a7d9da WH	168	#endif
	169
	170	#define CONFIG_NR_DRAM_BANKS 1
	171	#define PHYS_SDRAM 0x80000000
	172	#define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024)
	173
	174	#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
	175	#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
	176
	177	#define CONFIG_SYS_HAS_SERDES
	178
4ba4a095 RG	179	#define CONFIG_FSL_CAAM /* Enable CAAM */
4ba4a095 RG	180
4c59ab9c AW	181	#if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \
4c59ab9c AW	182	!defined(CONFIG_QSPI_BOOT)
eaa859e7 ZQ	183	#define CONFIG_U_QE
	184	#endif
	185
c8a7d9da WH	186	/*
	187	* IFC Definitions
	188	*/
947cee11	189	#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
c8a7d9da WH	190	#define CONFIG_FSL_IFC
	191	#define CONFIG_SYS_FLASH_BASE 0x60000000
	192	#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
	193
	194	#define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
	195	#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \| \
	196	CSPR_PORT_SIZE_16 \| \
	197	CSPR_MSEL_NOR \| \
	198	CSPR_V)
	199	#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024)
	200
	201	/* NOR Flash Timing Params */
	202	#define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) \| \
	203	CSOR_NOR_TRHZ_80)
	204	#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) \| \
	205	FTIM0_NOR_TEADC(0x5) \| \
	206	FTIM0_NOR_TAVDS(0x0) \| \
	207	FTIM0_NOR_TEAHC(0x5))
	208	#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) \| \
	209	FTIM1_NOR_TRAD_NOR(0x1A) \| \
	210	FTIM1_NOR_TSEQRAD_NOR(0x13))
	211	#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) \| \
	212	FTIM2_NOR_TCH(0x4) \| \
	213	FTIM2_NOR_TWP(0x1c) \| \
	214	FTIM2_NOR_TWPH(0x0e))
	215	#define CONFIG_SYS_NOR_FTIM3 0
	216
	217	#define CONFIG_FLASH_CFI_DRIVER
	218	#define CONFIG_SYS_FLASH_CFI
	219	#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
	220	#define CONFIG_SYS_FLASH_QUIET_TEST
	221	#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
	222
	223	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
	224	#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
	225	#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
	226	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
	227
	228	#define CONFIG_SYS_FLASH_EMPTY_INFO
	229	#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS }
	230
	231	#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
272c5265	232	#define CONFIG_SYS_WRITE_SWAPPED_DATA
d612f0ab	233	#endif
c8a7d9da WH	234
	235	/* CPLD */
	236
	237	#define CONFIG_SYS_CPLD_BASE 0x7fb00000
	238	#define CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE
	239
	240	#define CONFIG_SYS_FPGA_CSPR_EXT (0x0)
	241	#define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) \| \
	242	CSPR_PORT_SIZE_8 \| \
	243	CSPR_MSEL_GPCM \| \
	244	CSPR_V)
	245	#define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024)
	246	#define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) \| \
	247	CSOR_NOR_NOR_MODE_AVD_NOR \| \
	248	CSOR_NOR_TRHZ_80)
	249
	250	/* CPLD Timing parameters for IFC GPCM */
	251	#define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xf) \| \
	252	FTIM0_GPCM_TEADC(0xf) \| \
	253	FTIM0_GPCM_TEAHC(0xf))
	254	#define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0xff) \| \
	255	FTIM1_GPCM_TRAD(0x3f))
	256	#define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0xf) \| \
	257	FTIM2_GPCM_TCH(0xf) \| \
	258	FTIM2_GPCM_TWP(0xff))
	259	#define CONFIG_SYS_FPGA_FTIM3 0x0
	260	#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
	261	#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
	262	#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
	263	#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
	264	#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
	265	#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
	266	#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
	267	#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
	268	#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_FPGA_CSPR_EXT
	269	#define CONFIG_SYS_CSPR1 CONFIG_SYS_FPGA_CSPR
	270	#define CONFIG_SYS_AMASK1 CONFIG_SYS_FPGA_AMASK
	271	#define CONFIG_SYS_CSOR1 CONFIG_SYS_FPGA_CSOR
	272	#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_FPGA_FTIM0
	273	#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_FPGA_FTIM1
	274	#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_FPGA_FTIM2
	275	#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_FPGA_FTIM3
	276
	277	/*
	278	* Serial Port
	279	*/
55d53ab4	280	#ifdef CONFIG_LPUART
55d53ab4 AW	281	#define CONFIG_LPUART_32B_REG
55d53ab4 AW	282	#else
c8a7d9da	283	#define CONFIG_CONS_INDEX 1
c8a7d9da	284	#define CONFIG_SYS_NS16550_SERIAL
f833cd62	285	#ifndef CONFIG_DM_SERIAL
c8a7d9da	286	#define CONFIG_SYS_NS16550_REG_SIZE 1
f833cd62	287	#endif
c8a7d9da	288	#define CONFIG_SYS_NS16550_CLK get_serial_clock()
55d53ab4	289	#endif
c8a7d9da WH	290
	291	#define CONFIG_BAUDRATE 115200
	292
	293	/*
	294	* I2C
	295	*/
c8a7d9da WH	296	#define CONFIG_SYS_I2C
c8a7d9da WH	297	#define CONFIG_SYS_I2C_MXC
03544c66 AA	298	#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
03544c66 AA	299	#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
f8cb101e	300	#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
c8a7d9da	301
5175a288	302	/* EEPROM */
5175a288 AW	303	#define CONFIG_ID_EEPROM
	304	#define CONFIG_SYS_I2C_EEPROM_NXID
	305	#define CONFIG_SYS_EEPROM_BUS_NUM 1
	306	#define CONFIG_SYS_I2C_EEPROM_ADDR 0x53
	307	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
	308	#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
	309	#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
5175a288	310
c8a7d9da WH	311	/*
	312	* MMC
	313	*/
	314	#define CONFIG_MMC
c8a7d9da WH	315	#define CONFIG_FSL_ESDHC
	316	#define CONFIG_GENERIC_MMC
	317
8251ed23 AW	318	#define CONFIG_DOS_PARTITION
8251ed23 AW	319
9dd3d3c0	320	/* SPI */
947cee11	321	#if defined(CONFIG_QSPI_BOOT) \|\| defined(CONFIG_SD_BOOT_QSPI)
9dd3d3c0	322	/* QSPI */
d612f0ab AW	323	#define QSPI0_AMBA_BASE 0x40000000
	324	#define FSL_QSPI_FLASH_SIZE (1 << 24)
	325	#define FSL_QSPI_FLASH_NUM 2
	326
03d1d568	327	/* DSPI */
03d1d568 YY	328	#endif
03d1d568 YY	329
9dd3d3c0 HW	330	/* DM SPI */
9dd3d3c0 HW	331	#if defined(CONFIG_FSL_DSPI) \|\| defined(CONFIG_FSL_QSPI)
9dd3d3c0 HW	332	#define CONFIG_DM_SPI_FLASH
9dd3d3c0 HW	333	#endif
d612f0ab	334
b4ecc8c6 WH	335	/*
	336	* Video
	337	*/
	338	#define CONFIG_FSL_DCU_FB
	339
	340	#ifdef CONFIG_FSL_DCU_FB
	341	#define CONFIG_VIDEO
	342	#define CONFIG_CMD_BMP
	343	#define CONFIG_CFB_CONSOLE
	344	#define CONFIG_VGA_AS_SINGLE_DEVICE
	345	#define CONFIG_VIDEO_LOGO
	346	#define CONFIG_VIDEO_BMP_LOGO
f8008f14	347	#define CONFIG_SYS_CONSOLE_IS_IN_ENV
b4ecc8c6 WH	348
	349	#define CONFIG_FSL_DCU_SII9022A
	350	#define CONFIG_SYS_I2C_DVI_BUS_NUM 1
	351	#define CONFIG_SYS_I2C_DVI_ADDR 0x39
	352	#endif
	353
c8a7d9da WH	354	/*
	355	* eTSEC
	356	*/
	357	#define CONFIG_TSEC_ENET
	358
	359	#ifdef CONFIG_TSEC_ENET
	360	#define CONFIG_MII
	361	#define CONFIG_MII_DEFAULT_TSEC 1
	362	#define CONFIG_TSEC1 1
	363	#define CONFIG_TSEC1_NAME "eTSEC1"
	364	#define CONFIG_TSEC2 1
	365	#define CONFIG_TSEC2_NAME "eTSEC2"
	366	#define CONFIG_TSEC3 1
	367	#define CONFIG_TSEC3_NAME "eTSEC3"
	368
	369	#define TSEC1_PHY_ADDR 2
	370	#define TSEC2_PHY_ADDR 0
	371	#define TSEC3_PHY_ADDR 1
	372
	373	#define TSEC1_FLAGS (TSEC_GIGABIT \| TSEC_REDUCED)
	374	#define TSEC2_FLAGS (TSEC_GIGABIT \| TSEC_REDUCED)
	375	#define TSEC3_FLAGS (TSEC_GIGABIT \| TSEC_REDUCED)
	376
	377	#define TSEC1_PHYIDX 0
	378	#define TSEC2_PHYIDX 0
	379	#define TSEC3_PHYIDX 0
	380
	381	#define CONFIG_ETHPRIME "eTSEC1"
	382
	383	#define CONFIG_PHY_GIGE
	384	#define CONFIG_PHYLIB
	385	#define CONFIG_PHY_ATHEROS
	386
	387	#define CONFIG_HAS_ETH0
	388	#define CONFIG_HAS_ETH1
	389	#define CONFIG_HAS_ETH2
	390	#endif
	391
da419027 ML	392	/* PCIe */
da419027 ML	393	#define CONFIG_PCI /* Enable PCI/PCIE */
b38eaec5 RD	394	#define CONFIG_PCIE1 /* PCIE controller 1 */
b38eaec5 RD	395	#define CONFIG_PCIE2 /* PCIE controller 2 */
da419027 ML	396	#define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */
	397	#define FSL_PCIE_COMPAT "fsl,ls1021a-pcie"
	398
180b8688 ML	399	#define CONFIG_SYS_PCI_64BIT
	400
	401	#define CONFIG_SYS_PCIE_CFG0_PHYS_OFF 0x00000000
	402	#define CONFIG_SYS_PCIE_CFG0_SIZE 0x00001000 /* 4k */
	403	#define CONFIG_SYS_PCIE_CFG1_PHYS_OFF 0x00001000
	404	#define CONFIG_SYS_PCIE_CFG1_SIZE 0x00001000 /* 4k */
	405
	406	#define CONFIG_SYS_PCIE_IO_BUS 0x00000000
	407	#define CONFIG_SYS_PCIE_IO_PHYS_OFF 0x00010000
	408	#define CONFIG_SYS_PCIE_IO_SIZE 0x00010000 /* 64k */
	409
	410	#define CONFIG_SYS_PCIE_MEM_BUS 0x08000000
	411	#define CONFIG_SYS_PCIE_MEM_PHYS_OFF 0x04000000
	412	#define CONFIG_SYS_PCIE_MEM_SIZE 0x08000000 /* 128M */
	413
	414	#ifdef CONFIG_PCI
180b8688	415	#define CONFIG_PCI_PNP
180b8688 ML	416	#define CONFIG_PCI_SCAN_SHOW
180b8688 ML	417	#define CONFIG_CMD_PCI
180b8688 ML	418	#endif
180b8688 ML	419
c8a7d9da WH	420	#define CONFIG_CMDLINE_TAG
c8a7d9da WH	421	#define CONFIG_CMDLINE_EDITING
8415bb68	422
1a2826f6 XL	423	#define CONFIG_ARMV7_NONSEC
	424	#define CONFIG_ARMV7_VIRT
	425	#define CONFIG_PEN_ADDR_BIG_ENDIAN
435acd83	426	#define CONFIG_LAYERSCAPE_NS_ACCESS
1a2826f6 XL	427	#define CONFIG_SMP_PEN_ADDR 0x01ee0200
1a2826f6 XL	428	#define CONFIG_TIMER_CLK_FREQ 12500000
1a2826f6	429
c8a7d9da	430	#define CONFIG_HWCONFIG
03c22449 ZZ	431	#define HWCONFIG_BUFFER_SIZE 256
	432
	433	#define CONFIG_FSL_DEVICE_DISABLE
c8a7d9da	434
c8a7d9da	435
55d53ab4 AW	436	#ifdef CONFIG_LPUART
	437	#define CONFIG_EXTRA_ENV_SETTINGS \
	438	"bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0" \
7ff7166c AW	439	"initrd_high=0xffffffff\0" \
7ff7166c AW	440	"fdt_high=0xffffffff\0"
55d53ab4	441	#else
c8a7d9da WH	442	#define CONFIG_EXTRA_ENV_SETTINGS \
c8a7d9da WH	443	"bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \
7ff7166c AW	444	"initrd_high=0xffffffff\0" \
7ff7166c AW	445	"fdt_high=0xffffffff\0"
55d53ab4	446	#endif
c8a7d9da WH	447
	448	/*
	449	* Miscellaneous configurable options
	450	*/
	451	#define CONFIG_SYS_LONGHELP /* undef to save memory */
c8a7d9da WH	452	#define CONFIG_AUTO_COMPLETE
	453	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
	454	#define CONFIG_SYS_PBSIZE \
	455	(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
	456	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	457	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
	458
c8a7d9da WH	459	#define CONFIG_SYS_MEMTEST_START 0x80000000
	460	#define CONFIG_SYS_MEMTEST_END 0x9fffffff
	461
	462	#define CONFIG_SYS_LOAD_ADDR 0x82000000
c8a7d9da	463
660673af XL	464	#define CONFIG_LS102XA_STREAM_ID
660673af XL	465
c8a7d9da WH	466	/*
	467	* Stack sizes
	468	* The stack sizes are set up in start.S using the settings below
	469	*/
	470	#define CONFIG_STACKSIZE (30 * 1024)
	471
	472	#define CONFIG_SYS_INIT_SP_OFFSET \
	473	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
	474	#define CONFIG_SYS_INIT_SP_ADDR \
	475	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
	476
8415bb68 AW	477	#ifdef CONFIG_SPL_BUILD
	478	#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
	479	#else
c8a7d9da	480	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
8415bb68	481	#endif
c8a7d9da	482
713bf94f	483	#define CONFIG_SYS_QE_FW_ADDR 0x600c0000
eaa859e7	484
c8a7d9da WH	485	/*
	486	* Environment
	487	*/
	488	#define CONFIG_ENV_OVERWRITE
	489
8415bb68 AW	490	#if defined(CONFIG_SD_BOOT)
	491	#define CONFIG_ENV_OFFSET 0x100000
	492	#define CONFIG_ENV_IS_IN_MMC
	493	#define CONFIG_SYS_MMC_ENV_DEV 0
	494	#define CONFIG_ENV_SIZE 0x20000
d612f0ab AW	495	#elif defined(CONFIG_QSPI_BOOT)
	496	#define CONFIG_ENV_IS_IN_SPI_FLASH
	497	#define CONFIG_ENV_SIZE 0x2000
	498	#define CONFIG_ENV_OFFSET 0x100000
	499	#define CONFIG_ENV_SECT_SIZE 0x10000
8415bb68	500	#else
c8a7d9da WH	501	#define CONFIG_ENV_IS_IN_FLASH
	502	#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
	503	#define CONFIG_ENV_SIZE 0x20000
	504	#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
8415bb68	505	#endif
c8a7d9da	506
4ba4a095 RG	507	#define CONFIG_MISC_INIT_R
	508
	509	/* Hash command with SHA acceleration supported in hardware */
ef6c55a2	510	#ifdef CONFIG_FSL_CAAM
4ba4a095 RG	511	#define CONFIG_CMD_HASH
4ba4a095 RG	512	#define CONFIG_SHA_HW_ACCEL
ef6c55a2 AB	513	#endif
	514
	515	#include <asm/fsl_secure_boot.h>
cc7b8b9a	516	#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
4ba4a095	517
c8a7d9da	518	#endif