[people/ms/u-boot.git] / include / configs / ls2080a_common.h

/*
 * Copyright (C) 2014 Freescale Semiconductor
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __LS2_COMMON_H
#define __LS2_COMMON_H


#define CONFIG_REMAKE_ELF
#define CONFIG_FSL_LAYERSCAPE
#define CONFIG_FSL_LSCH3
#define CONFIG_MP
#define CONFIG_GICV3
#define CONFIG_FSL_TZPC_BP147


#include <asm/arch/ls2080a_stream_id.h>
#include <asm/arch/config.h>
#if (defined(CONFIG_SYS_FSL_SRDS_1) || defined(CONFIG_SYS_FSL_SRDS_2))
#define	CONFIG_SYS_HAS_SERDES
#endif

/* Link Definitions */
#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)

/* We need architecture specific misc initializations */
#define CONFIG_ARCH_MISC_INIT

/* Link Definitions */
#ifdef CONFIG_SPL
#define CONFIG_SYS_TEXT_BASE		0x80400000
#else
#define CONFIG_SYS_TEXT_BASE		0x30100000
#endif

#ifdef CONFIG_EMU
#define CONFIG_SYS_NO_FLASH
#endif

#define CONFIG_SUPPORT_RAW_INITRD

#define CONFIG_SKIP_LOWLEVEL_INIT
#define CONFIG_BOARD_EARLY_INIT_F	1

#ifndef CONFIG_SPL
#define CONFIG_FSL_DDR_INTERACTIVE	/* Interactive debugging */
#endif
#ifndef CONFIG_SYS_FSL_DDR4
#define CONFIG_SYS_FSL_DDR3		/* Use DDR3 memory */
#define CONFIG_SYS_DDR_RAW_TIMING
#endif

#define CONFIG_SYS_FSL_DDR_INTLV_256B	/* force 256 byte interleaving */

#define CONFIG_VERY_BIG_RAM
#define CONFIG_SYS_DDR_SDRAM_BASE	0x80000000UL
#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY	0
#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
#define CONFIG_SYS_DDR_BLOCK2_BASE	0x8080000000ULL
#define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS	2

/*
 * SMP Definitinos
 */
#define CPU_RELEASE_ADDR		secondary_boot_func

#define CONFIG_SYS_FSL_OTHER_DDR_NUM_CTRLS
#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
#define CONFIG_SYS_DP_DDR_BASE		0x6000000000ULL
/*
 * DDR controller use 0 as the base address for binding.
 * It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access.
 */
#define CONFIG_SYS_DP_DDR_BASE_PHY	0
#define CONFIG_DP_DDR_CTRL		2
#define CONFIG_DP_DDR_NUM_CTRLS		1
#endif

/* Generic Timer Definitions */
/*
 * This is not an accurate number. It is used in start.S. The frequency
 * will be udpated later when get_bus_freq(0) is available.
 */
#define COUNTER_FREQUENCY		25000000	/* 25MHz */

/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 2048 * 1024)

/* I2C */
#define CONFIG_CMD_I2C
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_MXC
#define CONFIG_SYS_I2C_MXC_I2C1		/* enable I2C bus 1 */
#define CONFIG_SYS_I2C_MXC_I2C2		/* enable I2C bus 2 */
#define CONFIG_SYS_I2C_MXC_I2C3		/* enable I2C bus 3 */
#define CONFIG_SYS_I2C_MXC_I2C4		/* enable I2C bus 4 */

/* Serial Port */
#define CONFIG_CONS_INDEX       1
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE     1
#define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)

#define CONFIG_BAUDRATE			115200
#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }

/* IFC */
#define CONFIG_FSL_IFC

/*
 * During booting, IFC is mapped at the region of 0x30000000.
 * But this region is limited to 256MB. To accommodate NOR, promjet
 * and FPGA. This region is divided as below:
 * 0x30000000 - 0x37ffffff : 128MB : NOR flash
 * 0x38000000 - 0x3BFFFFFF : 64MB  : Promjet
 * 0x3C000000 - 0x40000000 : 64MB  : FPGA etc
 *
 * To accommodate bigger NOR flash and other devices, we will map IFC
 * chip selects to as below:
 * 0x5_1000_0000..0x5_1fff_ffff	Memory Hole
 * 0x5_2000_0000..0x5_3fff_ffff	IFC CSx (FPGA, NAND and others 512MB)
 * 0x5_4000_0000..0x5_7fff_ffff	ASIC or others 1GB
 * 0x5_8000_0000..0x5_bfff_ffff	IFC CS0 1GB (NOR/Promjet)
 * 0x5_C000_0000..0x5_ffff_ffff	IFC CS1 1GB (NOR/Promjet)
 *
 * For e.g. NOR flash at CS0 will be mapped to 0x580000000 after relocation.
 * CONFIG_SYS_FLASH_BASE has the final address (core view)
 * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view)
 * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address
 * CONFIG_SYS_TEXT_BASE is linked to 0x30000000 for booting
 */

#define CONFIG_SYS_FLASH_BASE			0x580000000ULL
#define CONFIG_SYS_FLASH_BASE_PHYS		0x80000000
#define CONFIG_SYS_FLASH_BASE_PHYS_EARLY	0x00000000

#define CONFIG_SYS_FLASH1_BASE_PHYS		0xC0000000
#define CONFIG_SYS_FLASH1_BASE_PHYS_EARLY	0x8000000

#ifndef CONFIG_SYS_NO_FLASH
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
#define CONFIG_SYS_FLASH_QUIET_TEST
#endif

#ifndef __ASSEMBLY__
unsigned long long get_qixis_addr(void);
#endif
#define QIXIS_BASE				get_qixis_addr()
#define QIXIS_BASE_PHYS				0x20000000
#define QIXIS_BASE_PHYS_EARLY			0xC000000
#define QIXIS_STAT_PRES1			0xb
#define QIXIS_SDID_MASK				0x07
#define QIXIS_ESDHC_NO_ADAPTER			0x7

#define CONFIG_SYS_NAND_BASE			0x530000000ULL
#define CONFIG_SYS_NAND_BASE_PHYS		0x30000000

/* Debug Server firmware */
#define CONFIG_FSL_DEBUG_SERVER
/* 2 sec timeout */
#define CONFIG_SYS_DEBUG_SERVER_TIMEOUT			(2 * 1000 * 1000)

/* MC firmware */
#define CONFIG_FSL_MC_ENET
/* TODO Actual DPL max length needs to be confirmed with the MC FW team */
#define CONFIG_SYS_LS_MC_DPC_MAX_LENGTH	    0x20000
#define CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET    0x00F00000
#define CONFIG_SYS_LS_MC_DPL_MAX_LENGTH	    0x20000
#define CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET    0x00F20000
#ifdef CONFIG_LS2085A
#define CONFIG_SYS_LS_MC_AIOP_IMG_MAX_LENGTH	0x200000
#define CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET	0x07000000
#endif

/*
 * Carve out a DDR region which will not be used by u-boot/Linux
 *
 * It will be used by MC and Debug Server. The MC region must be
 * 512MB aligned, so the min size to hide is 512MB.
 */
#if defined(CONFIG_FSL_MC_ENET) || defined(CONFIG_FSL_DEBUG_SERVER)
#define CONFIG_SYS_DEBUG_SERVER_DRAM_BLOCK_MIN_SIZE	(254UL * 1024 * 1024)
#define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE		(512UL * 1024 * 1024)
#define CONFIG_SYS_MC_RSV_MEM_ALIGN			(512UL * 1024 * 1024)
#endif

/* PCIe */
#define CONFIG_PCIE1		/* PCIE controler 1 */
#define CONFIG_PCIE2		/* PCIE controler 2 */
#define CONFIG_PCIE3		/* PCIE controler 3 */
#define CONFIG_PCIE4		/* PCIE controler 4 */
#define CONFIG_PCIE_LAYERSCAPE	/* Use common FSL Layerscape PCIe code */
#ifdef CONFIG_LS2080A
#define FSL_PCIE_COMPAT "fsl,ls2080a-pcie"
#endif

#ifdef CONFIG_LS2085A
#define FSL_PCIE_COMPAT "fsl,ls2085a-pcie"
#endif

#define CONFIG_SYS_PCI_64BIT

#define CONFIG_SYS_PCIE_CFG0_PHYS_OFF	0x00000000
#define CONFIG_SYS_PCIE_CFG0_SIZE	0x00001000	/* 4k */
#define CONFIG_SYS_PCIE_CFG1_PHYS_OFF	0x00001000
#define CONFIG_SYS_PCIE_CFG1_SIZE	0x00001000	/* 4k */

#define CONFIG_SYS_PCIE_IO_BUS		0x00000000
#define CONFIG_SYS_PCIE_IO_PHYS_OFF	0x00010000
#define CONFIG_SYS_PCIE_IO_SIZE		0x00010000	/* 64k */

#define CONFIG_SYS_PCIE_MEM_BUS		0x40000000
#define CONFIG_SYS_PCIE_MEM_PHYS_OFF	0x40000000
#define CONFIG_SYS_PCIE_MEM_SIZE	0x40000000	/* 1G */

/* Command line configuration */
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_ENV
#define CONFIG_CMD_GREPENV
#define CONFIG_CMD_MII
#define CONFIG_CMD_PING

/* Miscellaneous configurable options */
#define CONFIG_SYS_LOAD_ADDR	(CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
#define CONFIG_ARCH_EARLY_INIT_R

/* Physical Memory Map */
/* fixme: these need to be checked against the board */
#define CONFIG_CHIP_SELECTS_PER_CTRL	4

#define CONFIG_NR_DRAM_BANKS		3

#define CONFIG_HWCONFIG
#define HWCONFIG_BUFFER_SIZE		128

#define CONFIG_DISPLAY_CPUINFO

/* Allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE

/* Initial environment variables */
#define CONFIG_EXTRA_ENV_SETTINGS		\
	"hwconfig=fsl_ddr:bank_intlv=auto\0"	\
	"loadaddr=0x80100000\0"			\
	"kernel_addr=0x100000\0"		\
	"ramdisk_addr=0x800000\0"		\
	"ramdisk_size=0x2000000\0"		\
	"fdt_high=0xa0000000\0"			\
	"initrd_high=0xffffffffffffffff\0"	\
	"kernel_start=0x581200000\0"		\
	"kernel_load=0xa0000000\0"		\
	"kernel_size=0x2800000\0"		\
	"console=ttyAMA0,38400n8\0"		\
	"mcinitcmd=fsl_mc start mc 0x580300000"	\
	" 0x580800000 \0"

#define CONFIG_BOOTARGS		"console=ttyS0,115200 root=/dev/ram0 " \
				"earlycon=uart8250,mmio,0x21c0500" \
				"ramdisk_size=0x2000000 default_hugepagesz=2m" \
				" hugepagesz=2m hugepages=256"
#define CONFIG_BOOTCOMMAND	"fsl_mc apply dpl 0x580700000 &&" \
				" cp.b $kernel_start $kernel_load" \
				" $kernel_size && bootm $kernel_load"
#define CONFIG_BOOTDELAY		10

/* Monitor Command Prompt */
#define CONFIG_SYS_CBSIZE		512	/* Console I/O Buffer Size */
#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
					sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_HUSH_PARSER
#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE /* Boot args buffer */
#define CONFIG_SYS_LONGHELP
#define CONFIG_CMDLINE_EDITING		1
#define CONFIG_AUTO_COMPLETE
#define CONFIG_SYS_MAXARGS		64	/* max command args */

#define CONFIG_PANIC_HANG	/* do not reset board on panic */

#define CONFIG_SPL_BSS_START_ADDR	0x80100000
#define CONFIG_SPL_BSS_MAX_SIZE		0x00100000
#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
#define CONFIG_SPL_ENV_SUPPORT
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_I2C_SUPPORT
#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"
#define CONFIG_SPL_LIBCOMMON_SUPPORT
#define CONFIG_SPL_LIBGENERIC_SUPPORT
#define CONFIG_SPL_MAX_SIZE		0x16000
#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
#define CONFIG_SPL_NAND_SUPPORT
#define CONFIG_SPL_SERIAL_SUPPORT
#define CONFIG_SPL_STACK		(CONFIG_SYS_FSL_OCRAM_BASE + 0x9ff0)
#define CONFIG_SPL_TARGET		"u-boot-with-spl.bin"
#define CONFIG_SPL_TEXT_BASE		0x1800a000

#define CONFIG_SYS_NAND_U_BOOT_DST	0x80400000
#define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_NAND_U_BOOT_DST
#define CONFIG_SYS_SPL_MALLOC_SIZE	0x00100000
#define CONFIG_SYS_SPL_MALLOC_START	0x80200000
#define CONFIG_SYS_MONITOR_LEN		(512 * 1024)

#define CONFIG_SYS_BOOTM_LEN   (64 << 20)      /* Increase max gunzip size */


#endif /* __LS2_COMMON_H */
Commit	Line	Data
f749db3a YS	1	/*
	2	* Copyright (C) 2014 Freescale Semiconductor
	3	*
	4	* SPDX-License-Identifier: GPL-2.0+
	5	*/
	6
	7	#ifndef __LS2_COMMON_H
	8	#define __LS2_COMMON_H
	9
f749db3a YS	10
f749db3a YS	11	#define CONFIG_REMAKE_ELF
9f3183d2	12	#define CONFIG_FSL_LAYERSCAPE
f749db3a	13	#define CONFIG_FSL_LSCH3
9f3183d2	14	#define CONFIG_MP
f749db3a	15	#define CONFIG_GICV3
9c66ce66	16	#define CONFIG_FSL_TZPC_BP147
f749db3a	17
1b1069cd	18
44937214	19	#include <asm/arch/ls2080a_stream_id.h>
9f3183d2	20	#include <asm/arch/config.h>
31d34c6c ML	21	#if (defined(CONFIG_SYS_FSL_SRDS_1) \|\| defined(CONFIG_SYS_FSL_SRDS_2))
	22	#define CONFIG_SYS_HAS_SERDES
	23	#endif
	24
9f3183d2 MH	25	/* Link Definitions */
	26	#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
	27
422cb08a BS	28	/* We need architecture specific misc initializations */
	29	#define CONFIG_ARCH_MISC_INIT
	30
f749db3a	31	/* Link Definitions */
b2d5ac59 SW	32	#ifdef CONFIG_SPL
	33	#define CONFIG_SYS_TEXT_BASE 0x80400000
	34	#else
f3f8c564	35	#define CONFIG_SYS_TEXT_BASE 0x30100000
b2d5ac59	36	#endif
f749db3a	37
e211c12e	38	#ifdef CONFIG_EMU
f749db3a	39	#define CONFIG_SYS_NO_FLASH
e211c12e	40	#endif
f749db3a YS	41
	42	#define CONFIG_SUPPORT_RAW_INITRD
	43
	44	#define CONFIG_SKIP_LOWLEVEL_INIT
	45	#define CONFIG_BOARD_EARLY_INIT_F 1
	46
b2d5ac59	47	#ifndef CONFIG_SPL
f749db3a	48	#define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */
b2d5ac59	49	#endif
f749db3a YS	50	#ifndef CONFIG_SYS_FSL_DDR4
	51	#define CONFIG_SYS_FSL_DDR3 /* Use DDR3 memory */
	52	#define CONFIG_SYS_DDR_RAW_TIMING
	53	#endif
f749db3a YS	54
	55	#define CONFIG_SYS_FSL_DDR_INTLV_256B /* force 256 byte interleaving */
	56
9f3183d2	57	#define CONFIG_VERY_BIG_RAM
f749db3a YS	58	#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
	59	#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
	60	#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
	61	#define CONFIG_SYS_DDR_BLOCK2_BASE 0x8080000000ULL
d9c68b14 YS	62	#define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS 2
d9c68b14 YS	63
8bfa301b YS	64	/*
	65	* SMP Definitinos
	66	*/
	67	#define CPU_RELEASE_ADDR secondary_boot_func
	68
d9c68b14	69	#define CONFIG_SYS_FSL_OTHER_DDR_NUM_CTRLS
44937214	70	#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
d9c68b14 YS	71	#define CONFIG_SYS_DP_DDR_BASE 0x6000000000ULL
	72	/*
	73	* DDR controller use 0 as the base address for binding.
	74	* It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access.
	75	*/
	76	#define CONFIG_SYS_DP_DDR_BASE_PHY 0
	77	#define CONFIG_DP_DDR_CTRL 2
	78	#define CONFIG_DP_DDR_NUM_CTRLS 1
44937214	79	#endif
f749db3a YS	80
f749db3a YS	81	/* Generic Timer Definitions */
207774b2 YS	82	/*
	83	* This is not an accurate number. It is used in start.S. The frequency
	84	* will be udpated later when get_bus_freq(0) is available.
	85	*/
	86	#define COUNTER_FREQUENCY 25000000 /* 25MHz */
f749db3a YS	87
f749db3a YS	88	/* Size of malloc() pool */
aa66acbf	89	#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2048 * 1024)
f749db3a YS	90
	91	/* I2C */
	92	#define CONFIG_CMD_I2C
	93	#define CONFIG_SYS_I2C
	94	#define CONFIG_SYS_I2C_MXC
03544c66 AA	95	#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
03544c66 AA	96	#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
f8cb101e YS	97	#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
f8cb101e YS	98	#define CONFIG_SYS_I2C_MXC_I2C4 /* enable I2C bus 4 */
f749db3a YS	99
f749db3a YS	100	/* Serial Port */
7288c2c2	101	#define CONFIG_CONS_INDEX 1
f749db3a YS	102	#define CONFIG_SYS_NS16550_SERIAL
	103	#define CONFIG_SYS_NS16550_REG_SIZE 1
	104	#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
	105
	106	#define CONFIG_BAUDRATE 115200
	107	#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
	108
	109	/* IFC */
	110	#define CONFIG_FSL_IFC
f3f8c564	111
f749db3a	112	/*
7288c2c2 YS	113	* During booting, IFC is mapped at the region of 0x30000000.
	114	* But this region is limited to 256MB. To accommodate NOR, promjet
	115	* and FPGA. This region is divided as below:
	116	* 0x30000000 - 0x37ffffff : 128MB : NOR flash
	117	* 0x38000000 - 0x3BFFFFFF : 64MB : Promjet
	118	* 0x3C000000 - 0x40000000 : 64MB : FPGA etc
	119	*
	120	* To accommodate bigger NOR flash and other devices, we will map IFC
	121	* chip selects to as below:
	122	* 0x5_1000_0000..0x5_1fff_ffff Memory Hole
	123	* 0x5_2000_0000..0x5_3fff_ffff IFC CSx (FPGA, NAND and others 512MB)
	124	* 0x5_4000_0000..0x5_7fff_ffff ASIC or others 1GB
	125	* 0x5_8000_0000..0x5_bfff_ffff IFC CS0 1GB (NOR/Promjet)
	126	* 0x5_C000_0000..0x5_ffff_ffff IFC CS1 1GB (NOR/Promjet)
	127	*
	128	* For e.g. NOR flash at CS0 will be mapped to 0x580000000 after relocation.
f749db3a YS	129	* CONFIG_SYS_FLASH_BASE has the final address (core view)
	130	* CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view)
	131	* CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address
	132	* CONFIG_SYS_TEXT_BASE is linked to 0x30000000 for booting
	133	*/
7288c2c2	134
f749db3a YS	135	#define CONFIG_SYS_FLASH_BASE 0x580000000ULL
	136	#define CONFIG_SYS_FLASH_BASE_PHYS 0x80000000
	137	#define CONFIG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000
	138
7288c2c2 YS	139	#define CONFIG_SYS_FLASH1_BASE_PHYS 0xC0000000
	140	#define CONFIG_SYS_FLASH1_BASE_PHYS_EARLY 0x8000000
	141
e211c12e PK	142	#ifndef CONFIG_SYS_NO_FLASH
	143	#define CONFIG_FLASH_CFI_DRIVER
	144	#define CONFIG_SYS_FLASH_CFI
	145	#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
	146	#define CONFIG_SYS_FLASH_QUIET_TEST
e211c12e PK	147	#endif
e211c12e PK	148
7288c2c2 YS	149	#ifndef __ASSEMBLY__
	150	unsigned long long get_qixis_addr(void);
	151	#endif
	152	#define QIXIS_BASE get_qixis_addr()
	153	#define QIXIS_BASE_PHYS 0x20000000
	154	#define QIXIS_BASE_PHYS_EARLY 0xC000000
8b06460e YL	155	#define QIXIS_STAT_PRES1 0xb
	156	#define QIXIS_SDID_MASK 0x07
	157	#define QIXIS_ESDHC_NO_ADAPTER 0x7
7288c2c2 YS	158
	159	#define CONFIG_SYS_NAND_BASE 0x530000000ULL
	160	#define CONFIG_SYS_NAND_BASE_PHYS 0x30000000
e211c12e	161
422cb08a	162	/* Debug Server firmware */
b0ba9d48	163	#define CONFIG_FSL_DEBUG_SERVER
422cb08a BS	164	/* 2 sec timeout */
	165	#define CONFIG_SYS_DEBUG_SERVER_TIMEOUT (2 * 1000 * 1000)
	166
f749db3a YS	167	/* MC firmware */
f749db3a YS	168	#define CONFIG_FSL_MC_ENET
f749db3a	169	/* TODO Actual DPL max length needs to be confirmed with the MC FW team */
125e2bc1 GR	170	#define CONFIG_SYS_LS_MC_DPC_MAX_LENGTH 0x20000
	171	#define CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET 0x00F00000
	172	#define CONFIG_SYS_LS_MC_DPL_MAX_LENGTH 0x20000
	173	#define CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET 0x00F20000
06b53010	174	#ifdef CONFIG_LS2085A
c1000c12 GR	175	#define CONFIG_SYS_LS_MC_AIOP_IMG_MAX_LENGTH 0x200000
c1000c12 GR	176	#define CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET 0x07000000
44937214	177	#endif
f749db3a	178
5c055089 PK	179	/*
	180	* Carve out a DDR region which will not be used by u-boot/Linux
	181	*
	182	* It will be used by MC and Debug Server. The MC region must be
	183	* 512MB aligned, so the min size to hide is 512MB.
	184	*/
422cb08a	185	#if defined(CONFIG_FSL_MC_ENET) \|\| defined(CONFIG_FSL_DEBUG_SERVER)
c0492141	186	#define CONFIG_SYS_DEBUG_SERVER_DRAM_BLOCK_MIN_SIZE (254UL * 1024 * 1024)
52c11d4f	187	#define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (512UL * 1024 * 1024)
c0492141	188	#define CONFIG_SYS_MC_RSV_MEM_ALIGN (512UL * 1024 * 1024)
f749db3a YS	189	#endif
f749db3a YS	190
f3f8c564 PK	191	/* PCIe */
	192	#define CONFIG_PCIE1 /* PCIE controler 1 */
	193	#define CONFIG_PCIE2 /* PCIE controler 2 */
	194	#define CONFIG_PCIE3 /* PCIE controler 3 */
	195	#define CONFIG_PCIE4 /* PCIE controler 4 */
252b17e0	196	#define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */
06b53010	197	#ifdef CONFIG_LS2080A
44937214	198	#define FSL_PCIE_COMPAT "fsl,ls2080a-pcie"
06b53010 PK	199	#endif
	200
	201	#ifdef CONFIG_LS2085A
	202	#define FSL_PCIE_COMPAT "fsl,ls2085a-pcie"
	203	#endif
f3f8c564 PK	204
	205	#define CONFIG_SYS_PCI_64BIT
	206
	207	#define CONFIG_SYS_PCIE_CFG0_PHYS_OFF 0x00000000
	208	#define CONFIG_SYS_PCIE_CFG0_SIZE 0x00001000 /* 4k */
	209	#define CONFIG_SYS_PCIE_CFG1_PHYS_OFF 0x00001000
	210	#define CONFIG_SYS_PCIE_CFG1_SIZE 0x00001000 /* 4k */
	211
	212	#define CONFIG_SYS_PCIE_IO_BUS 0x00000000
	213	#define CONFIG_SYS_PCIE_IO_PHYS_OFF 0x00010000
	214	#define CONFIG_SYS_PCIE_IO_SIZE 0x00010000 /* 64k */
	215
	216	#define CONFIG_SYS_PCIE_MEM_BUS 0x40000000
	217	#define CONFIG_SYS_PCIE_MEM_PHYS_OFF 0x40000000
	218	#define CONFIG_SYS_PCIE_MEM_SIZE 0x40000000 /* 1G */
	219
f749db3a YS	220	/* Command line configuration */
f749db3a YS	221	#define CONFIG_CMD_CACHE
f749db3a YS	222	#define CONFIG_CMD_DHCP
f749db3a YS	223	#define CONFIG_CMD_ENV
778145ac	224	#define CONFIG_CMD_GREPENV
f749db3a	225	#define CONFIG_CMD_MII
f749db3a	226	#define CONFIG_CMD_PING
f749db3a YS	227
	228	/* Miscellaneous configurable options */
	229	#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
8bfa301b	230	#define CONFIG_ARCH_EARLY_INIT_R
f749db3a YS	231
	232	/* Physical Memory Map */
	233	/* fixme: these need to be checked against the board */
	234	#define CONFIG_CHIP_SELECTS_PER_CTRL 4
f749db3a	235
d9c68b14	236	#define CONFIG_NR_DRAM_BANKS 3
f749db3a	237
f749db3a YS	238	#define CONFIG_HWCONFIG
	239	#define HWCONFIG_BUFFER_SIZE 128
	240
	241	#define CONFIG_DISPLAY_CPUINFO
	242
1d3a76fa AW	243	/* Allow to overwrite serial and ethaddr */
	244	#define CONFIG_ENV_OVERWRITE
	245
f749db3a YS	246	/* Initial environment variables */
	247	#define CONFIG_EXTRA_ENV_SETTINGS \
	248	"hwconfig=fsl_ddr:bank_intlv=auto\0" \
	249	"loadaddr=0x80100000\0" \
	250	"kernel_addr=0x100000\0" \
	251	"ramdisk_addr=0x800000\0" \
	252	"ramdisk_size=0x2000000\0" \
f3f8c564	253	"fdt_high=0xa0000000\0" \
f749db3a YS	254	"initrd_high=0xffffffffffffffff\0" \
f749db3a YS	255	"kernel_start=0x581200000\0" \
052ddd5c	256	"kernel_load=0xa0000000\0" \
97421bd2	257	"kernel_size=0x2800000\0" \
16ed8560 PK	258	"console=ttyAMA0,38400n8\0" \
	259	"mcinitcmd=fsl_mc start mc 0x580300000" \
	260	" 0x580800000 \0"
f749db3a	261
56cd0760	262	#define CONFIG_BOOTARGS "console=ttyS0,115200 root=/dev/ram0 " \
b22b1dc6	263	"earlycon=uart8250,mmio,0x21c0500" \
34cc7546	264	"ramdisk_size=0x2000000 default_hugepagesz=2m" \
9e71bb9c	265	" hugepagesz=2m hugepages=256"
9f3e1b8a PK	266	#define CONFIG_BOOTCOMMAND "fsl_mc apply dpl 0x580700000 &&" \
	267	" cp.b $kernel_start $kernel_load" \
	268	" $kernel_size && bootm $kernel_load"
7288c2c2	269	#define CONFIG_BOOTDELAY 10
f749db3a	270
f749db3a YS	271	/* Monitor Command Prompt */
f749db3a YS	272	#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
f749db3a YS	273	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
	274	sizeof(CONFIG_SYS_PROMPT) + 16)
	275	#define CONFIG_SYS_HUSH_PARSER
	276	#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
	277	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot args buffer */
	278	#define CONFIG_SYS_LONGHELP
	279	#define CONFIG_CMDLINE_EDITING 1
f3f8c564	280	#define CONFIG_AUTO_COMPLETE
f749db3a YS	281	#define CONFIG_SYS_MAXARGS 64 /* max command args */
f749db3a YS	282
f3f8c564 PK	283	#define CONFIG_PANIC_HANG /* do not reset board on panic */
f3f8c564 PK	284
b2d5ac59 SW	285	#define CONFIG_SPL_BSS_START_ADDR 0x80100000
	286	#define CONFIG_SPL_BSS_MAX_SIZE 0x00100000
	287	#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
	288	#define CONFIG_SPL_ENV_SUPPORT
	289	#define CONFIG_SPL_FRAMEWORK
	290	#define CONFIG_SPL_I2C_SUPPORT
	291	#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"
	292	#define CONFIG_SPL_LIBCOMMON_SUPPORT
	293	#define CONFIG_SPL_LIBGENERIC_SUPPORT
	294	#define CONFIG_SPL_MAX_SIZE 0x16000
	295	#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
	296	#define CONFIG_SPL_NAND_SUPPORT
	297	#define CONFIG_SPL_SERIAL_SUPPORT
	298	#define CONFIG_SPL_STACK (CONFIG_SYS_FSL_OCRAM_BASE + 0x9ff0)
	299	#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
	300	#define CONFIG_SPL_TEXT_BASE 0x1800a000
	301
	302	#define CONFIG_SYS_NAND_U_BOOT_DST 0x80400000
	303	#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST
	304	#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00100000
	305	#define CONFIG_SYS_SPL_MALLOC_START 0x80200000
	306	#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
	307
34cc7546 BS	308	#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
	309
	310
f749db3a	311	#endif /* __LS2_COMMON_H */