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f749db3a YS |
1 | /* |
2 | * Copyright (C) 2014 Freescale Semiconductor | |
3 | * | |
4 | * SPDX-License-Identifier: GPL-2.0+ | |
5 | */ | |
6 | ||
7 | #ifndef __LS2_COMMON_H | |
8 | #define __LS2_COMMON_H | |
9 | ||
f749db3a YS |
10 | |
11 | #define CONFIG_REMAKE_ELF | |
9f3183d2 | 12 | #define CONFIG_FSL_LAYERSCAPE |
f749db3a | 13 | #define CONFIG_FSL_LSCH3 |
9f3183d2 | 14 | #define CONFIG_MP |
f749db3a | 15 | #define CONFIG_GICV3 |
9c66ce66 | 16 | #define CONFIG_FSL_TZPC_BP147 |
f749db3a | 17 | |
1b1069cd | 18 | |
44937214 | 19 | #include <asm/arch/ls2080a_stream_id.h> |
9f3183d2 | 20 | #include <asm/arch/config.h> |
31d34c6c ML |
21 | #if (defined(CONFIG_SYS_FSL_SRDS_1) || defined(CONFIG_SYS_FSL_SRDS_2)) |
22 | #define CONFIG_SYS_HAS_SERDES | |
23 | #endif | |
24 | ||
9f3183d2 MH |
25 | /* Link Definitions */ |
26 | #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0) | |
27 | ||
422cb08a BS |
28 | /* We need architecture specific misc initializations */ |
29 | #define CONFIG_ARCH_MISC_INIT | |
30 | ||
f749db3a | 31 | /* Link Definitions */ |
b2d5ac59 SW |
32 | #ifdef CONFIG_SPL |
33 | #define CONFIG_SYS_TEXT_BASE 0x80400000 | |
34 | #else | |
f3f8c564 | 35 | #define CONFIG_SYS_TEXT_BASE 0x30100000 |
b2d5ac59 | 36 | #endif |
f749db3a | 37 | |
e211c12e | 38 | #ifdef CONFIG_EMU |
f749db3a | 39 | #define CONFIG_SYS_NO_FLASH |
e211c12e | 40 | #endif |
f749db3a YS |
41 | |
42 | #define CONFIG_SUPPORT_RAW_INITRD | |
43 | ||
44 | #define CONFIG_SKIP_LOWLEVEL_INIT | |
45 | #define CONFIG_BOARD_EARLY_INIT_F 1 | |
46 | ||
f749db3a | 47 | /* Flat Device Tree Definitions */ |
f749db3a | 48 | #define CONFIG_OF_BOARD_SETUP |
6b6db0d5 | 49 | #define CONFIG_OF_STDOUT_VIA_ALIAS |
f749db3a YS |
50 | |
51 | /* new uImage format support */ | |
52 | #define CONFIG_FIT | |
53 | #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ | |
54 | ||
b2d5ac59 | 55 | #ifndef CONFIG_SPL |
f749db3a | 56 | #define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */ |
b2d5ac59 | 57 | #endif |
f749db3a YS |
58 | #ifndef CONFIG_SYS_FSL_DDR4 |
59 | #define CONFIG_SYS_FSL_DDR3 /* Use DDR3 memory */ | |
60 | #define CONFIG_SYS_DDR_RAW_TIMING | |
61 | #endif | |
f749db3a YS |
62 | |
63 | #define CONFIG_SYS_FSL_DDR_INTLV_256B /* force 256 byte interleaving */ | |
64 | ||
9f3183d2 | 65 | #define CONFIG_VERY_BIG_RAM |
f749db3a YS |
66 | #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL |
67 | #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 | |
68 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE | |
69 | #define CONFIG_SYS_DDR_BLOCK2_BASE 0x8080000000ULL | |
d9c68b14 YS |
70 | #define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS 2 |
71 | ||
8bfa301b YS |
72 | /* |
73 | * SMP Definitinos | |
74 | */ | |
75 | #define CPU_RELEASE_ADDR secondary_boot_func | |
76 | ||
d9c68b14 | 77 | #define CONFIG_SYS_FSL_OTHER_DDR_NUM_CTRLS |
44937214 | 78 | #ifdef CONFIG_SYS_FSL_HAS_DP_DDR |
d9c68b14 YS |
79 | #define CONFIG_SYS_DP_DDR_BASE 0x6000000000ULL |
80 | /* | |
81 | * DDR controller use 0 as the base address for binding. | |
82 | * It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access. | |
83 | */ | |
84 | #define CONFIG_SYS_DP_DDR_BASE_PHY 0 | |
85 | #define CONFIG_DP_DDR_CTRL 2 | |
86 | #define CONFIG_DP_DDR_NUM_CTRLS 1 | |
44937214 | 87 | #endif |
f749db3a YS |
88 | |
89 | /* Generic Timer Definitions */ | |
207774b2 YS |
90 | /* |
91 | * This is not an accurate number. It is used in start.S. The frequency | |
92 | * will be udpated later when get_bus_freq(0) is available. | |
93 | */ | |
94 | #define COUNTER_FREQUENCY 25000000 /* 25MHz */ | |
f749db3a YS |
95 | |
96 | /* Size of malloc() pool */ | |
aa66acbf | 97 | #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2048 * 1024) |
f749db3a YS |
98 | |
99 | /* I2C */ | |
100 | #define CONFIG_CMD_I2C | |
101 | #define CONFIG_SYS_I2C | |
102 | #define CONFIG_SYS_I2C_MXC | |
03544c66 AA |
103 | #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ |
104 | #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ | |
f8cb101e YS |
105 | #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ |
106 | #define CONFIG_SYS_I2C_MXC_I2C4 /* enable I2C bus 4 */ | |
f749db3a YS |
107 | |
108 | /* Serial Port */ | |
7288c2c2 | 109 | #define CONFIG_CONS_INDEX 1 |
f749db3a YS |
110 | #define CONFIG_SYS_NS16550_SERIAL |
111 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
112 | #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) | |
113 | ||
114 | #define CONFIG_BAUDRATE 115200 | |
115 | #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } | |
116 | ||
117 | /* IFC */ | |
118 | #define CONFIG_FSL_IFC | |
f3f8c564 | 119 | |
f749db3a | 120 | /* |
7288c2c2 YS |
121 | * During booting, IFC is mapped at the region of 0x30000000. |
122 | * But this region is limited to 256MB. To accommodate NOR, promjet | |
123 | * and FPGA. This region is divided as below: | |
124 | * 0x30000000 - 0x37ffffff : 128MB : NOR flash | |
125 | * 0x38000000 - 0x3BFFFFFF : 64MB : Promjet | |
126 | * 0x3C000000 - 0x40000000 : 64MB : FPGA etc | |
127 | * | |
128 | * To accommodate bigger NOR flash and other devices, we will map IFC | |
129 | * chip selects to as below: | |
130 | * 0x5_1000_0000..0x5_1fff_ffff Memory Hole | |
131 | * 0x5_2000_0000..0x5_3fff_ffff IFC CSx (FPGA, NAND and others 512MB) | |
132 | * 0x5_4000_0000..0x5_7fff_ffff ASIC or others 1GB | |
133 | * 0x5_8000_0000..0x5_bfff_ffff IFC CS0 1GB (NOR/Promjet) | |
134 | * 0x5_C000_0000..0x5_ffff_ffff IFC CS1 1GB (NOR/Promjet) | |
135 | * | |
136 | * For e.g. NOR flash at CS0 will be mapped to 0x580000000 after relocation. | |
f749db3a YS |
137 | * CONFIG_SYS_FLASH_BASE has the final address (core view) |
138 | * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view) | |
139 | * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address | |
140 | * CONFIG_SYS_TEXT_BASE is linked to 0x30000000 for booting | |
141 | */ | |
7288c2c2 | 142 | |
f749db3a YS |
143 | #define CONFIG_SYS_FLASH_BASE 0x580000000ULL |
144 | #define CONFIG_SYS_FLASH_BASE_PHYS 0x80000000 | |
145 | #define CONFIG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000 | |
146 | ||
7288c2c2 YS |
147 | #define CONFIG_SYS_FLASH1_BASE_PHYS 0xC0000000 |
148 | #define CONFIG_SYS_FLASH1_BASE_PHYS_EARLY 0x8000000 | |
149 | ||
e211c12e PK |
150 | #ifndef CONFIG_SYS_NO_FLASH |
151 | #define CONFIG_FLASH_CFI_DRIVER | |
152 | #define CONFIG_SYS_FLASH_CFI | |
153 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE | |
154 | #define CONFIG_SYS_FLASH_QUIET_TEST | |
e211c12e PK |
155 | #endif |
156 | ||
7288c2c2 YS |
157 | #ifndef __ASSEMBLY__ |
158 | unsigned long long get_qixis_addr(void); | |
159 | #endif | |
160 | #define QIXIS_BASE get_qixis_addr() | |
161 | #define QIXIS_BASE_PHYS 0x20000000 | |
162 | #define QIXIS_BASE_PHYS_EARLY 0xC000000 | |
8b06460e YL |
163 | #define QIXIS_STAT_PRES1 0xb |
164 | #define QIXIS_SDID_MASK 0x07 | |
165 | #define QIXIS_ESDHC_NO_ADAPTER 0x7 | |
7288c2c2 YS |
166 | |
167 | #define CONFIG_SYS_NAND_BASE 0x530000000ULL | |
168 | #define CONFIG_SYS_NAND_BASE_PHYS 0x30000000 | |
e211c12e | 169 | |
422cb08a | 170 | /* Debug Server firmware */ |
b0ba9d48 | 171 | #define CONFIG_FSL_DEBUG_SERVER |
422cb08a BS |
172 | /* 2 sec timeout */ |
173 | #define CONFIG_SYS_DEBUG_SERVER_TIMEOUT (2 * 1000 * 1000) | |
174 | ||
f749db3a YS |
175 | /* MC firmware */ |
176 | #define CONFIG_FSL_MC_ENET | |
f749db3a | 177 | /* TODO Actual DPL max length needs to be confirmed with the MC FW team */ |
125e2bc1 GR |
178 | #define CONFIG_SYS_LS_MC_DPC_MAX_LENGTH 0x20000 |
179 | #define CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET 0x00F00000 | |
180 | #define CONFIG_SYS_LS_MC_DPL_MAX_LENGTH 0x20000 | |
181 | #define CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET 0x00F20000 | |
06b53010 | 182 | #ifdef CONFIG_LS2085A |
c1000c12 GR |
183 | #define CONFIG_SYS_LS_MC_AIOP_IMG_MAX_LENGTH 0x200000 |
184 | #define CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET 0x07000000 | |
44937214 | 185 | #endif |
f749db3a | 186 | |
5c055089 PK |
187 | /* |
188 | * Carve out a DDR region which will not be used by u-boot/Linux | |
189 | * | |
190 | * It will be used by MC and Debug Server. The MC region must be | |
191 | * 512MB aligned, so the min size to hide is 512MB. | |
192 | */ | |
422cb08a | 193 | #if defined(CONFIG_FSL_MC_ENET) || defined(CONFIG_FSL_DEBUG_SERVER) |
c0492141 | 194 | #define CONFIG_SYS_DEBUG_SERVER_DRAM_BLOCK_MIN_SIZE (254UL * 1024 * 1024) |
52c11d4f | 195 | #define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (512UL * 1024 * 1024) |
c0492141 | 196 | #define CONFIG_SYS_MC_RSV_MEM_ALIGN (512UL * 1024 * 1024) |
f749db3a YS |
197 | #endif |
198 | ||
f3f8c564 PK |
199 | /* PCIe */ |
200 | #define CONFIG_PCIE1 /* PCIE controler 1 */ | |
201 | #define CONFIG_PCIE2 /* PCIE controler 2 */ | |
202 | #define CONFIG_PCIE3 /* PCIE controler 3 */ | |
203 | #define CONFIG_PCIE4 /* PCIE controler 4 */ | |
252b17e0 | 204 | #define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */ |
06b53010 | 205 | #ifdef CONFIG_LS2080A |
44937214 | 206 | #define FSL_PCIE_COMPAT "fsl,ls2080a-pcie" |
06b53010 PK |
207 | #endif |
208 | ||
209 | #ifdef CONFIG_LS2085A | |
210 | #define FSL_PCIE_COMPAT "fsl,ls2085a-pcie" | |
211 | #endif | |
f3f8c564 PK |
212 | |
213 | #define CONFIG_SYS_PCI_64BIT | |
214 | ||
215 | #define CONFIG_SYS_PCIE_CFG0_PHYS_OFF 0x00000000 | |
216 | #define CONFIG_SYS_PCIE_CFG0_SIZE 0x00001000 /* 4k */ | |
217 | #define CONFIG_SYS_PCIE_CFG1_PHYS_OFF 0x00001000 | |
218 | #define CONFIG_SYS_PCIE_CFG1_SIZE 0x00001000 /* 4k */ | |
219 | ||
220 | #define CONFIG_SYS_PCIE_IO_BUS 0x00000000 | |
221 | #define CONFIG_SYS_PCIE_IO_PHYS_OFF 0x00010000 | |
222 | #define CONFIG_SYS_PCIE_IO_SIZE 0x00010000 /* 64k */ | |
223 | ||
224 | #define CONFIG_SYS_PCIE_MEM_BUS 0x40000000 | |
225 | #define CONFIG_SYS_PCIE_MEM_PHYS_OFF 0x40000000 | |
226 | #define CONFIG_SYS_PCIE_MEM_SIZE 0x40000000 /* 1G */ | |
227 | ||
f749db3a YS |
228 | /* Command line configuration */ |
229 | #define CONFIG_CMD_CACHE | |
f749db3a YS |
230 | #define CONFIG_CMD_DHCP |
231 | #define CONFIG_CMD_ENV | |
778145ac | 232 | #define CONFIG_CMD_GREPENV |
f749db3a | 233 | #define CONFIG_CMD_MII |
f749db3a | 234 | #define CONFIG_CMD_PING |
f749db3a YS |
235 | |
236 | /* Miscellaneous configurable options */ | |
237 | #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000) | |
8bfa301b | 238 | #define CONFIG_ARCH_EARLY_INIT_R |
f749db3a YS |
239 | |
240 | /* Physical Memory Map */ | |
241 | /* fixme: these need to be checked against the board */ | |
242 | #define CONFIG_CHIP_SELECTS_PER_CTRL 4 | |
f749db3a | 243 | |
d9c68b14 | 244 | #define CONFIG_NR_DRAM_BANKS 3 |
f749db3a | 245 | |
f749db3a YS |
246 | #define CONFIG_HWCONFIG |
247 | #define HWCONFIG_BUFFER_SIZE 128 | |
248 | ||
249 | #define CONFIG_DISPLAY_CPUINFO | |
250 | ||
1d3a76fa AW |
251 | /* Allow to overwrite serial and ethaddr */ |
252 | #define CONFIG_ENV_OVERWRITE | |
253 | ||
f749db3a YS |
254 | /* Initial environment variables */ |
255 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
256 | "hwconfig=fsl_ddr:bank_intlv=auto\0" \ | |
257 | "loadaddr=0x80100000\0" \ | |
258 | "kernel_addr=0x100000\0" \ | |
259 | "ramdisk_addr=0x800000\0" \ | |
260 | "ramdisk_size=0x2000000\0" \ | |
f3f8c564 | 261 | "fdt_high=0xa0000000\0" \ |
f749db3a YS |
262 | "initrd_high=0xffffffffffffffff\0" \ |
263 | "kernel_start=0x581200000\0" \ | |
052ddd5c | 264 | "kernel_load=0xa0000000\0" \ |
97421bd2 | 265 | "kernel_size=0x2800000\0" \ |
16ed8560 PK |
266 | "console=ttyAMA0,38400n8\0" \ |
267 | "mcinitcmd=fsl_mc start mc 0x580300000" \ | |
268 | " 0x580800000 \0" | |
f749db3a | 269 | |
56cd0760 | 270 | #define CONFIG_BOOTARGS "console=ttyS0,115200 root=/dev/ram0 " \ |
b22b1dc6 | 271 | "earlycon=uart8250,mmio,0x21c0500" \ |
34cc7546 | 272 | "ramdisk_size=0x2000000 default_hugepagesz=2m" \ |
9e71bb9c | 273 | " hugepagesz=2m hugepages=256" |
9f3e1b8a PK |
274 | #define CONFIG_BOOTCOMMAND "fsl_mc apply dpl 0x580700000 &&" \ |
275 | " cp.b $kernel_start $kernel_load" \ | |
276 | " $kernel_size && bootm $kernel_load" | |
7288c2c2 | 277 | #define CONFIG_BOOTDELAY 10 |
f749db3a | 278 | |
f749db3a YS |
279 | /* Monitor Command Prompt */ |
280 | #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ | |
f749db3a YS |
281 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ |
282 | sizeof(CONFIG_SYS_PROMPT) + 16) | |
283 | #define CONFIG_SYS_HUSH_PARSER | |
284 | #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " | |
285 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot args buffer */ | |
286 | #define CONFIG_SYS_LONGHELP | |
287 | #define CONFIG_CMDLINE_EDITING 1 | |
f3f8c564 | 288 | #define CONFIG_AUTO_COMPLETE |
f749db3a YS |
289 | #define CONFIG_SYS_MAXARGS 64 /* max command args */ |
290 | ||
f3f8c564 PK |
291 | #define CONFIG_PANIC_HANG /* do not reset board on panic */ |
292 | ||
b2d5ac59 SW |
293 | #define CONFIG_SPL_BSS_START_ADDR 0x80100000 |
294 | #define CONFIG_SPL_BSS_MAX_SIZE 0x00100000 | |
295 | #define CONFIG_SPL_DRIVERS_MISC_SUPPORT | |
296 | #define CONFIG_SPL_ENV_SUPPORT | |
297 | #define CONFIG_SPL_FRAMEWORK | |
298 | #define CONFIG_SPL_I2C_SUPPORT | |
299 | #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds" | |
300 | #define CONFIG_SPL_LIBCOMMON_SUPPORT | |
301 | #define CONFIG_SPL_LIBGENERIC_SUPPORT | |
302 | #define CONFIG_SPL_MAX_SIZE 0x16000 | |
303 | #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT | |
304 | #define CONFIG_SPL_NAND_SUPPORT | |
305 | #define CONFIG_SPL_SERIAL_SUPPORT | |
306 | #define CONFIG_SPL_STACK (CONFIG_SYS_FSL_OCRAM_BASE + 0x9ff0) | |
307 | #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" | |
308 | #define CONFIG_SPL_TEXT_BASE 0x1800a000 | |
309 | ||
310 | #define CONFIG_SYS_NAND_U_BOOT_DST 0x80400000 | |
311 | #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST | |
312 | #define CONFIG_SYS_SPL_MALLOC_SIZE 0x00100000 | |
313 | #define CONFIG_SYS_SPL_MALLOC_START 0x80200000 | |
314 | #define CONFIG_SYS_MONITOR_LEN (512 * 1024) | |
315 | ||
34cc7546 BS |
316 | #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ |
317 | ||
318 | ||
f749db3a | 319 | #endif /* __LS2_COMMON_H */ |