[people/ms/u-boot.git] / include / configs / ls2085a_common.h

/*
 * Copyright (C) 2014 Freescale Semiconductor
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __LS2_COMMON_H
#define __LS2_COMMON_H

#define CONFIG_SYS_GENERIC_BOARD

#define CONFIG_REMAKE_ELF
#define CONFIG_FSL_LSCH3
#define CONFIG_LS2085A
#define CONFIG_GICV3
#define CONFIG_FSL_TZPC_BP147

/* Errata fixes */
#define CONFIG_ARM_ERRATA_828024
#define CONFIG_ARM_ERRATA_826974

#include <asm/arch-fsl-lsch3/ls2085a_stream_id.h>
#include <asm/arch-fsl-lsch3/config.h>
#if (defined(CONFIG_SYS_FSL_SRDS_1) || defined(CONFIG_SYS_FSL_SRDS_2))
#define	CONFIG_SYS_HAS_SERDES
#endif

/* We need architecture specific misc initializations */
#define CONFIG_ARCH_MISC_INIT

/* Link Definitions */
#ifdef CONFIG_SPL
#define CONFIG_SYS_TEXT_BASE		0x80400000
#else
#define CONFIG_SYS_TEXT_BASE		0x30100000
#endif

#ifdef CONFIG_EMU
#define CONFIG_SYS_NO_FLASH
#endif

#define CONFIG_SUPPORT_RAW_INITRD

#define CONFIG_SKIP_LOWLEVEL_INIT
#define CONFIG_BOARD_EARLY_INIT_F	1

/* Flat Device Tree Definitions */
#define CONFIG_OF_LIBFDT
#define CONFIG_OF_BOARD_SETUP

/* new uImage format support */
#define CONFIG_FIT
#define CONFIG_FIT_VERBOSE	/* enable fit_format_{error,warning}() */

#ifndef CONFIG_SPL
#define CONFIG_FSL_DDR_INTERACTIVE	/* Interactive debugging */
#endif
#ifndef CONFIG_SYS_FSL_DDR4
#define CONFIG_SYS_FSL_DDR3		/* Use DDR3 memory */
#define CONFIG_SYS_DDR_RAW_TIMING
#endif

#define CONFIG_SYS_FSL_DDR_INTLV_256B	/* force 256 byte interleaving */

#define CONFIG_SYS_DDR_SDRAM_BASE	0x80000000UL
#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY	0
#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
#define CONFIG_SYS_DDR_BLOCK2_BASE	0x8080000000ULL
#define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS	2

/*
 * SMP Definitinos
 */
#define CPU_RELEASE_ADDR		secondary_boot_func

#define CONFIG_SYS_FSL_OTHER_DDR_NUM_CTRLS
#define CONFIG_SYS_DP_DDR_BASE		0x6000000000ULL
/*
 * DDR controller use 0 as the base address for binding.
 * It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access.
 */
#define CONFIG_SYS_DP_DDR_BASE_PHY	0
#define CONFIG_DP_DDR_CTRL		2
#define CONFIG_DP_DDR_NUM_CTRLS		1

/* Generic Timer Definitions */
/*
 * This is not an accurate number. It is used in start.S. The frequency
 * will be udpated later when get_bus_freq(0) is available.
 */
#define COUNTER_FREQUENCY		25000000	/* 25MHz */

/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 2048 * 1024)

/* I2C */
#define CONFIG_CMD_I2C
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_MXC
#define CONFIG_SYS_I2C_MXC_I2C1		/* enable I2C bus 1 */
#define CONFIG_SYS_I2C_MXC_I2C2		/* enable I2C bus 2 */
#define CONFIG_SYS_I2C_MXC_I2C3		/* enable I2C bus 3 */
#define CONFIG_SYS_I2C_MXC_I2C4		/* enable I2C bus 4 */

/* Serial Port */
#define CONFIG_CONS_INDEX       1
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE     1
#define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)

#define CONFIG_BAUDRATE			115200
#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }

/* IFC */
#define CONFIG_FSL_IFC

/*
 * During booting, IFC is mapped at the region of 0x30000000.
 * But this region is limited to 256MB. To accommodate NOR, promjet
 * and FPGA. This region is divided as below:
 * 0x30000000 - 0x37ffffff : 128MB : NOR flash
 * 0x38000000 - 0x3BFFFFFF : 64MB  : Promjet
 * 0x3C000000 - 0x40000000 : 64MB  : FPGA etc
 *
 * To accommodate bigger NOR flash and other devices, we will map IFC
 * chip selects to as below:
 * 0x5_1000_0000..0x5_1fff_ffff	Memory Hole
 * 0x5_2000_0000..0x5_3fff_ffff	IFC CSx (FPGA, NAND and others 512MB)
 * 0x5_4000_0000..0x5_7fff_ffff	ASIC or others 1GB
 * 0x5_8000_0000..0x5_bfff_ffff	IFC CS0 1GB (NOR/Promjet)
 * 0x5_C000_0000..0x5_ffff_ffff	IFC CS1 1GB (NOR/Promjet)
 *
 * For e.g. NOR flash at CS0 will be mapped to 0x580000000 after relocation.
 * CONFIG_SYS_FLASH_BASE has the final address (core view)
 * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view)
 * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address
 * CONFIG_SYS_TEXT_BASE is linked to 0x30000000 for booting
 */

#define CONFIG_SYS_FLASH_BASE			0x580000000ULL
#define CONFIG_SYS_FLASH_BASE_PHYS		0x80000000
#define CONFIG_SYS_FLASH_BASE_PHYS_EARLY	0x00000000

#define CONFIG_SYS_FLASH1_BASE_PHYS		0xC0000000
#define CONFIG_SYS_FLASH1_BASE_PHYS_EARLY	0x8000000

#ifndef CONFIG_SYS_NO_FLASH
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
#define CONFIG_SYS_FLASH_QUIET_TEST
#endif

#ifndef __ASSEMBLY__
unsigned long long get_qixis_addr(void);
#endif
#define QIXIS_BASE				get_qixis_addr()
#define QIXIS_BASE_PHYS				0x20000000
#define QIXIS_BASE_PHYS_EARLY			0xC000000
#define QIXIS_STAT_PRES1			0xb
#define QIXIS_SDID_MASK				0x07
#define QIXIS_ESDHC_NO_ADAPTER			0x7

#define CONFIG_SYS_NAND_BASE			0x530000000ULL
#define CONFIG_SYS_NAND_BASE_PHYS		0x30000000

/* Debug Server firmware */
#define CONFIG_FSL_DEBUG_SERVER
/* 2 sec timeout */
#define CONFIG_SYS_DEBUG_SERVER_TIMEOUT			(2 * 1000 * 1000)

/* MC firmware */
#define CONFIG_FSL_MC_ENET
/* TODO Actual DPL max length needs to be confirmed with the MC FW team */
#define CONFIG_SYS_LS_MC_DPC_MAX_LENGTH	    0x20000
#define CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET    0x00F00000
#define CONFIG_SYS_LS_MC_DPL_MAX_LENGTH	    0x20000
#define CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET    0x00F20000
#define CONFIG_SYS_LS_MC_AIOP_IMG_MAX_LENGTH	0x200000
#define CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET	0x07000000

/*
 * Carve out a DDR region which will not be used by u-boot/Linux
 *
 * It will be used by MC and Debug Server. The MC region must be
 * 512MB aligned, so the min size to hide is 512MB.
 */
#if defined(CONFIG_FSL_MC_ENET) || defined(CONFIG_FSL_DEBUG_SERVER)
#define CONFIG_SYS_DEBUG_SERVER_DRAM_BLOCK_MIN_SIZE	(256UL * 1024 * 1024)
#define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE		(256UL * 1024 * 1024)
#define CONFIG_SYS_MEM_TOP_HIDE_MIN			(512UL * 1024 * 1024)
#define CONFIG_SYS_MEM_TOP_HIDE		get_dram_size_to_hide()
#endif

/* PCIe */
#define CONFIG_PCIE1		/* PCIE controler 1 */
#define CONFIG_PCIE2		/* PCIE controler 2 */
#define CONFIG_PCIE3		/* PCIE controler 3 */
#define CONFIG_PCIE4		/* PCIE controler 4 */
#define CONFIG_PCIE_LAYERSCAPE	/* Use common FSL Layerscape PCIe code */
#define FSL_PCIE_COMPAT "fsl,ls2085a-pcie"

#define CONFIG_SYS_PCI_64BIT

#define CONFIG_SYS_PCIE_CFG0_PHYS_OFF	0x00000000
#define CONFIG_SYS_PCIE_CFG0_SIZE	0x00001000	/* 4k */
#define CONFIG_SYS_PCIE_CFG1_PHYS_OFF	0x00001000
#define CONFIG_SYS_PCIE_CFG1_SIZE	0x00001000	/* 4k */

#define CONFIG_SYS_PCIE_IO_BUS		0x00000000
#define CONFIG_SYS_PCIE_IO_PHYS_OFF	0x00010000
#define CONFIG_SYS_PCIE_IO_SIZE		0x00010000	/* 64k */

#define CONFIG_SYS_PCIE_MEM_BUS		0x40000000
#define CONFIG_SYS_PCIE_MEM_PHYS_OFF	0x40000000
#define CONFIG_SYS_PCIE_MEM_SIZE	0x40000000	/* 1G */

/* Command line configuration */
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_ENV
#define CONFIG_CMD_GREPENV
#define CONFIG_CMD_MII
#define CONFIG_CMD_PING

/* Miscellaneous configurable options */
#define CONFIG_SYS_LOAD_ADDR	(CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
#define CONFIG_ARCH_EARLY_INIT_R

/* Physical Memory Map */
/* fixme: these need to be checked against the board */
#define CONFIG_CHIP_SELECTS_PER_CTRL	4

#define CONFIG_NR_DRAM_BANKS		3

#define CONFIG_HWCONFIG
#define HWCONFIG_BUFFER_SIZE		128

#define CONFIG_DISPLAY_CPUINFO

/* Initial environment variables */
#define CONFIG_EXTRA_ENV_SETTINGS		\
	"hwconfig=fsl_ddr:bank_intlv=auto\0"	\
	"loadaddr=0x80100000\0"			\
	"kernel_addr=0x100000\0"		\
	"ramdisk_addr=0x800000\0"		\
	"ramdisk_size=0x2000000\0"		\
	"fdt_high=0xa0000000\0"			\
	"initrd_high=0xffffffffffffffff\0"	\
	"kernel_start=0x581200000\0"		\
	"kernel_load=0xa0000000\0"		\
	"kernel_size=0x2800000\0"		\
	"console=ttyAMA0,38400n8\0"

#define CONFIG_BOOTARGS		"console=ttyS0,115200 root=/dev/ram0 " \
				"earlycon=uart8250,mmio,0x21c0500,115200 " \
				"ramdisk_size=0x2000000 default_hugepagesz=2m" \
				" hugepagesz=2m hugepages=16"
#define CONFIG_BOOTCOMMAND		"cp.b $kernel_start $kernel_load "     \
					"$kernel_size && bootm $kernel_load"
#define CONFIG_BOOTDELAY		10

/* Monitor Command Prompt */
#define CONFIG_SYS_CBSIZE		512	/* Console I/O Buffer Size */
#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
					sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_HUSH_PARSER
#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE /* Boot args buffer */
#define CONFIG_SYS_LONGHELP
#define CONFIG_CMDLINE_EDITING		1
#define CONFIG_AUTO_COMPLETE
#define CONFIG_SYS_MAXARGS		64	/* max command args */

#ifndef __ASSEMBLY__
unsigned long get_dram_size_to_hide(void);
#endif

#define CONFIG_PANIC_HANG	/* do not reset board on panic */

#define CONFIG_SPL_BSS_START_ADDR	0x80100000
#define CONFIG_SPL_BSS_MAX_SIZE		0x00100000
#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
#define CONFIG_SPL_ENV_SUPPORT
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_I2C_SUPPORT
#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"
#define CONFIG_SPL_LIBCOMMON_SUPPORT
#define CONFIG_SPL_LIBGENERIC_SUPPORT
#define CONFIG_SPL_MAX_SIZE		0x16000
#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
#define CONFIG_SPL_NAND_SUPPORT
#define CONFIG_SPL_SERIAL_SUPPORT
#define CONFIG_SPL_STACK		(CONFIG_SYS_FSL_OCRAM_BASE + 0x9ff0)
#define CONFIG_SPL_TARGET		"u-boot-with-spl.bin"
#define CONFIG_SPL_TEXT_BASE		0x1800a000

#define CONFIG_SYS_NAND_U_BOOT_DST	0x80400000
#define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_NAND_U_BOOT_DST
#define CONFIG_SYS_SPL_MALLOC_SIZE	0x00100000
#define CONFIG_SYS_SPL_MALLOC_START	0x80200000
#define CONFIG_SYS_MONITOR_LEN		(512 * 1024)

#define CONFIG_SYS_BOOTM_LEN   (64 << 20)      /* Increase max gunzip size */


#endif /* __LS2_COMMON_H */
Commit	Line	Data
f749db3a YS	1	/*
	2	* Copyright (C) 2014 Freescale Semiconductor
	3	*
	4	* SPDX-License-Identifier: GPL-2.0+
	5	*/
	6
	7	#ifndef __LS2_COMMON_H
	8	#define __LS2_COMMON_H
	9
	10	#define CONFIG_SYS_GENERIC_BOARD
	11
	12	#define CONFIG_REMAKE_ELF
	13	#define CONFIG_FSL_LSCH3
	14	#define CONFIG_LS2085A
	15	#define CONFIG_GICV3
9c66ce66	16	#define CONFIG_FSL_TZPC_BP147
f749db3a	17
1b1069cd BS	18	/* Errata fixes */
	19	#define CONFIG_ARM_ERRATA_828024
	20	#define CONFIG_ARM_ERRATA_826974
	21
39da644e	22	#include <asm/arch-fsl-lsch3/ls2085a_stream_id.h>
31d34c6c ML	23	#include <asm/arch-fsl-lsch3/config.h>
	24	#if (defined(CONFIG_SYS_FSL_SRDS_1) \|\| defined(CONFIG_SYS_FSL_SRDS_2))
	25	#define CONFIG_SYS_HAS_SERDES
	26	#endif
	27
422cb08a BS	28	/* We need architecture specific misc initializations */
	29	#define CONFIG_ARCH_MISC_INIT
	30
f749db3a	31	/* Link Definitions */
b2d5ac59 SW	32	#ifdef CONFIG_SPL
	33	#define CONFIG_SYS_TEXT_BASE 0x80400000
	34	#else
f3f8c564	35	#define CONFIG_SYS_TEXT_BASE 0x30100000
b2d5ac59	36	#endif
f749db3a	37
e211c12e	38	#ifdef CONFIG_EMU
f749db3a	39	#define CONFIG_SYS_NO_FLASH
e211c12e	40	#endif
f749db3a YS	41
	42	#define CONFIG_SUPPORT_RAW_INITRD
	43
	44	#define CONFIG_SKIP_LOWLEVEL_INIT
	45	#define CONFIG_BOARD_EARLY_INIT_F 1
	46
f749db3a YS	47	/* Flat Device Tree Definitions */
	48	#define CONFIG_OF_LIBFDT
	49	#define CONFIG_OF_BOARD_SETUP
	50
	51	/* new uImage format support */
	52	#define CONFIG_FIT
	53	#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
	54
b2d5ac59	55	#ifndef CONFIG_SPL
f749db3a	56	#define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */
b2d5ac59	57	#endif
f749db3a YS	58	#ifndef CONFIG_SYS_FSL_DDR4
	59	#define CONFIG_SYS_FSL_DDR3 /* Use DDR3 memory */
	60	#define CONFIG_SYS_DDR_RAW_TIMING
	61	#endif
f749db3a YS	62
	63	#define CONFIG_SYS_FSL_DDR_INTLV_256B /* force 256 byte interleaving */
	64
f749db3a YS	65	#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
	66	#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
	67	#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
	68	#define CONFIG_SYS_DDR_BLOCK2_BASE 0x8080000000ULL
d9c68b14 YS	69	#define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS 2
d9c68b14 YS	70
8bfa301b YS	71	/*
	72	* SMP Definitinos
	73	*/
	74	#define CPU_RELEASE_ADDR secondary_boot_func
	75
d9c68b14 YS	76	#define CONFIG_SYS_FSL_OTHER_DDR_NUM_CTRLS
	77	#define CONFIG_SYS_DP_DDR_BASE 0x6000000000ULL
	78	/*
	79	* DDR controller use 0 as the base address for binding.
	80	* It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access.
	81	*/
	82	#define CONFIG_SYS_DP_DDR_BASE_PHY 0
	83	#define CONFIG_DP_DDR_CTRL 2
	84	#define CONFIG_DP_DDR_NUM_CTRLS 1
f749db3a YS	85
f749db3a YS	86	/* Generic Timer Definitions */
207774b2 YS	87	/*
	88	* This is not an accurate number. It is used in start.S. The frequency
	89	* will be udpated later when get_bus_freq(0) is available.
	90	*/
	91	#define COUNTER_FREQUENCY 25000000 /* 25MHz */
f749db3a YS	92
f749db3a YS	93	/* Size of malloc() pool */
aa66acbf	94	#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2048 * 1024)
f749db3a YS	95
	96	/* I2C */
	97	#define CONFIG_CMD_I2C
	98	#define CONFIG_SYS_I2C
	99	#define CONFIG_SYS_I2C_MXC
03544c66 AA	100	#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
03544c66 AA	101	#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
f8cb101e YS	102	#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
f8cb101e YS	103	#define CONFIG_SYS_I2C_MXC_I2C4 /* enable I2C bus 4 */
f749db3a YS	104
f749db3a YS	105	/* Serial Port */
7288c2c2	106	#define CONFIG_CONS_INDEX 1
f749db3a YS	107	#define CONFIG_SYS_NS16550
	108	#define CONFIG_SYS_NS16550_SERIAL
	109	#define CONFIG_SYS_NS16550_REG_SIZE 1
	110	#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
	111
	112	#define CONFIG_BAUDRATE 115200
	113	#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
	114
	115	/* IFC */
	116	#define CONFIG_FSL_IFC
f3f8c564	117
f749db3a	118	/*
7288c2c2 YS	119	* During booting, IFC is mapped at the region of 0x30000000.
	120	* But this region is limited to 256MB. To accommodate NOR, promjet
	121	* and FPGA. This region is divided as below:
	122	* 0x30000000 - 0x37ffffff : 128MB : NOR flash
	123	* 0x38000000 - 0x3BFFFFFF : 64MB : Promjet
	124	* 0x3C000000 - 0x40000000 : 64MB : FPGA etc
	125	*
	126	* To accommodate bigger NOR flash and other devices, we will map IFC
	127	* chip selects to as below:
	128	* 0x5_1000_0000..0x5_1fff_ffff Memory Hole
	129	* 0x5_2000_0000..0x5_3fff_ffff IFC CSx (FPGA, NAND and others 512MB)
	130	* 0x5_4000_0000..0x5_7fff_ffff ASIC or others 1GB
	131	* 0x5_8000_0000..0x5_bfff_ffff IFC CS0 1GB (NOR/Promjet)
	132	* 0x5_C000_0000..0x5_ffff_ffff IFC CS1 1GB (NOR/Promjet)
	133	*
	134	* For e.g. NOR flash at CS0 will be mapped to 0x580000000 after relocation.
f749db3a YS	135	* CONFIG_SYS_FLASH_BASE has the final address (core view)
	136	* CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view)
	137	* CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address
	138	* CONFIG_SYS_TEXT_BASE is linked to 0x30000000 for booting
	139	*/
7288c2c2	140
f749db3a YS	141	#define CONFIG_SYS_FLASH_BASE 0x580000000ULL
	142	#define CONFIG_SYS_FLASH_BASE_PHYS 0x80000000
	143	#define CONFIG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000
	144
7288c2c2 YS	145	#define CONFIG_SYS_FLASH1_BASE_PHYS 0xC0000000
	146	#define CONFIG_SYS_FLASH1_BASE_PHYS_EARLY 0x8000000
	147
e211c12e PK	148	#ifndef CONFIG_SYS_NO_FLASH
	149	#define CONFIG_FLASH_CFI_DRIVER
	150	#define CONFIG_SYS_FLASH_CFI
	151	#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
	152	#define CONFIG_SYS_FLASH_QUIET_TEST
e211c12e PK	153	#endif
e211c12e PK	154
7288c2c2 YS	155	#ifndef __ASSEMBLY__
	156	unsigned long long get_qixis_addr(void);
	157	#endif
	158	#define QIXIS_BASE get_qixis_addr()
	159	#define QIXIS_BASE_PHYS 0x20000000
	160	#define QIXIS_BASE_PHYS_EARLY 0xC000000
8b06460e YL	161	#define QIXIS_STAT_PRES1 0xb
	162	#define QIXIS_SDID_MASK 0x07
	163	#define QIXIS_ESDHC_NO_ADAPTER 0x7
7288c2c2 YS	164
	165	#define CONFIG_SYS_NAND_BASE 0x530000000ULL
	166	#define CONFIG_SYS_NAND_BASE_PHYS 0x30000000
e211c12e	167
422cb08a	168	/* Debug Server firmware */
b0ba9d48	169	#define CONFIG_FSL_DEBUG_SERVER
422cb08a BS	170	/* 2 sec timeout */
	171	#define CONFIG_SYS_DEBUG_SERVER_TIMEOUT (2 * 1000 * 1000)
	172
f749db3a YS	173	/* MC firmware */
f749db3a YS	174	#define CONFIG_FSL_MC_ENET
f749db3a	175	/* TODO Actual DPL max length needs to be confirmed with the MC FW team */
125e2bc1 GR	176	#define CONFIG_SYS_LS_MC_DPC_MAX_LENGTH 0x20000
	177	#define CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET 0x00F00000
	178	#define CONFIG_SYS_LS_MC_DPL_MAX_LENGTH 0x20000
	179	#define CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET 0x00F20000
c1000c12 GR	180	#define CONFIG_SYS_LS_MC_AIOP_IMG_MAX_LENGTH 0x200000
c1000c12 GR	181	#define CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET 0x07000000
f749db3a	182
5c055089 PK	183	/*
	184	* Carve out a DDR region which will not be used by u-boot/Linux
	185	*
	186	* It will be used by MC and Debug Server. The MC region must be
	187	* 512MB aligned, so the min size to hide is 512MB.
	188	*/
422cb08a	189	#if defined(CONFIG_FSL_MC_ENET) \|\| defined(CONFIG_FSL_DEBUG_SERVER)
5c055089 PK	190	#define CONFIG_SYS_DEBUG_SERVER_DRAM_BLOCK_MIN_SIZE (256UL * 1024 * 1024)
	191	#define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (256UL * 1024 * 1024)
	192	#define CONFIG_SYS_MEM_TOP_HIDE_MIN (512UL * 1024 * 1024)
422cb08a	193	#define CONFIG_SYS_MEM_TOP_HIDE get_dram_size_to_hide()
f749db3a YS	194	#endif
f749db3a YS	195
f3f8c564 PK	196	/* PCIe */
	197	#define CONFIG_PCIE1 /* PCIE controler 1 */
	198	#define CONFIG_PCIE2 /* PCIE controler 2 */
	199	#define CONFIG_PCIE3 /* PCIE controler 3 */
	200	#define CONFIG_PCIE4 /* PCIE controler 4 */
252b17e0 PK	201	#define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */
252b17e0 PK	202	#define FSL_PCIE_COMPAT "fsl,ls2085a-pcie"
f3f8c564 PK	203
	204	#define CONFIG_SYS_PCI_64BIT
	205
	206	#define CONFIG_SYS_PCIE_CFG0_PHYS_OFF 0x00000000
	207	#define CONFIG_SYS_PCIE_CFG0_SIZE 0x00001000 /* 4k */
	208	#define CONFIG_SYS_PCIE_CFG1_PHYS_OFF 0x00001000
	209	#define CONFIG_SYS_PCIE_CFG1_SIZE 0x00001000 /* 4k */
	210
	211	#define CONFIG_SYS_PCIE_IO_BUS 0x00000000
	212	#define CONFIG_SYS_PCIE_IO_PHYS_OFF 0x00010000
	213	#define CONFIG_SYS_PCIE_IO_SIZE 0x00010000 /* 64k */
	214
	215	#define CONFIG_SYS_PCIE_MEM_BUS 0x40000000
	216	#define CONFIG_SYS_PCIE_MEM_PHYS_OFF 0x40000000
	217	#define CONFIG_SYS_PCIE_MEM_SIZE 0x40000000 /* 1G */
	218
f749db3a YS	219	/* Command line configuration */
f749db3a YS	220	#define CONFIG_CMD_CACHE
f749db3a YS	221	#define CONFIG_CMD_DHCP
f749db3a YS	222	#define CONFIG_CMD_ENV
778145ac	223	#define CONFIG_CMD_GREPENV
f749db3a	224	#define CONFIG_CMD_MII
f749db3a	225	#define CONFIG_CMD_PING
f749db3a YS	226
	227	/* Miscellaneous configurable options */
	228	#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
8bfa301b	229	#define CONFIG_ARCH_EARLY_INIT_R
f749db3a YS	230
	231	/* Physical Memory Map */
	232	/* fixme: these need to be checked against the board */
	233	#define CONFIG_CHIP_SELECTS_PER_CTRL 4
f749db3a	234
d9c68b14	235	#define CONFIG_NR_DRAM_BANKS 3
f749db3a	236
f749db3a YS	237	#define CONFIG_HWCONFIG
	238	#define HWCONFIG_BUFFER_SIZE 128
	239
	240	#define CONFIG_DISPLAY_CPUINFO
	241
	242	/* Initial environment variables */
	243	#define CONFIG_EXTRA_ENV_SETTINGS \
	244	"hwconfig=fsl_ddr:bank_intlv=auto\0" \
	245	"loadaddr=0x80100000\0" \
	246	"kernel_addr=0x100000\0" \
	247	"ramdisk_addr=0x800000\0" \
	248	"ramdisk_size=0x2000000\0" \
f3f8c564	249	"fdt_high=0xa0000000\0" \
f749db3a YS	250	"initrd_high=0xffffffffffffffff\0" \
f749db3a YS	251	"kernel_start=0x581200000\0" \
052ddd5c	252	"kernel_load=0xa0000000\0" \
97421bd2	253	"kernel_size=0x2800000\0" \
f749db3a YS	254	"console=ttyAMA0,38400n8\0"
f749db3a YS	255
56cd0760 PK	256	#define CONFIG_BOOTARGS "console=ttyS0,115200 root=/dev/ram0 " \
56cd0760 PK	257	"earlycon=uart8250,mmio,0x21c0500,115200 " \
34cc7546 BS	258	"ramdisk_size=0x2000000 default_hugepagesz=2m" \
34cc7546 BS	259	" hugepagesz=2m hugepages=16"
f749db3a YS	260	#define CONFIG_BOOTCOMMAND "cp.b $kernel_start $kernel_load " \
f749db3a YS	261	"$kernel_size && bootm $kernel_load"
7288c2c2	262	#define CONFIG_BOOTDELAY 10
f749db3a	263
f749db3a YS	264	/* Monitor Command Prompt */
f749db3a YS	265	#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
f749db3a YS	266	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
	267	sizeof(CONFIG_SYS_PROMPT) + 16)
	268	#define CONFIG_SYS_HUSH_PARSER
	269	#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
	270	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot args buffer */
	271	#define CONFIG_SYS_LONGHELP
	272	#define CONFIG_CMDLINE_EDITING 1
f3f8c564	273	#define CONFIG_AUTO_COMPLETE
f749db3a YS	274	#define CONFIG_SYS_MAXARGS 64 /* max command args */
	275
	276	#ifndef __ASSEMBLY__
422cb08a	277	unsigned long get_dram_size_to_hide(void);
f749db3a YS	278	#endif
f749db3a YS	279
f3f8c564 PK	280	#define CONFIG_PANIC_HANG /* do not reset board on panic */
f3f8c564 PK	281
b2d5ac59 SW	282	#define CONFIG_SPL_BSS_START_ADDR 0x80100000
	283	#define CONFIG_SPL_BSS_MAX_SIZE 0x00100000
	284	#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
	285	#define CONFIG_SPL_ENV_SUPPORT
	286	#define CONFIG_SPL_FRAMEWORK
	287	#define CONFIG_SPL_I2C_SUPPORT
	288	#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"
	289	#define CONFIG_SPL_LIBCOMMON_SUPPORT
	290	#define CONFIG_SPL_LIBGENERIC_SUPPORT
	291	#define CONFIG_SPL_MAX_SIZE 0x16000
	292	#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
	293	#define CONFIG_SPL_NAND_SUPPORT
	294	#define CONFIG_SPL_SERIAL_SUPPORT
	295	#define CONFIG_SPL_STACK (CONFIG_SYS_FSL_OCRAM_BASE + 0x9ff0)
	296	#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
	297	#define CONFIG_SPL_TEXT_BASE 0x1800a000
	298
	299	#define CONFIG_SYS_NAND_U_BOOT_DST 0x80400000
	300	#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST
	301	#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00100000
	302	#define CONFIG_SYS_SPL_MALLOC_START 0x80200000
	303	#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
	304
34cc7546 BS	305	#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
	306
	307
f749db3a	308	#endif /* __LS2_COMMON_H */