]> git.ipfire.org Git - people/ms/u-boot.git/commitdiff
I2C: mxc_i2c: make I2C1 and I2C2 optional
authorAlbert ARIBAUD \\(3ADEV\\) <albert.aribaud@3adev.fr>
Mon, 21 Sep 2015 20:43:38 +0000 (22:43 +0200)
committerStefano Babic <sbabic@denx.de>
Fri, 2 Oct 2015 08:42:31 +0000 (10:42 +0200)
The driver assumed that I2C1 and I2C2 were always enabled,
and if they were not, then an asynchronous abort was (silently)
raised, to be caught much later on in the Linux kernel.

Fix this by making I2C1 and I2C2 optional just like I2C3 and I2C4
are.

To make the change binary-invariant, declare I2C1 and I2C2 in
every include/configs/ file which defines CONFIG_SYS_I2C_MXC.

Also, while updating README about CONFIG_SYS_I2C_MXC_I2C1 and
CONFIG_SYS_I2C_MXC_I2C2, add missing descriptions for I2C4 speed
(CONFIG_SYS_MXC_I2C4_SPEED) and slave (CONFIG_SYS_MXC_I2C4_SLAVE)
config options.

Signed-off-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>
38 files changed:
README
drivers/i2c/mxc_i2c.c
include/configs/apf27.h
include/configs/aristainetos-common.h
include/configs/cgtqmx6eval.h
include/configs/cm_fx6.h
include/configs/embestmx6boards.h
include/configs/flea3.h
include/configs/gw_ventana.h
include/configs/imx31_phycore.h
include/configs/ls1021aqds.h
include/configs/ls1021atwr.h
include/configs/ls2085a_common.h
include/configs/m53evk.h
include/configs/mx25pdk.h
include/configs/mx35pdk.h
include/configs/mx53ard.h
include/configs/mx53evk.h
include/configs/mx53loco.h
include/configs/mx53smd.h
include/configs/mx6qsabreauto.h
include/configs/mx6sabresd.h
include/configs/mx6slevk.h
include/configs/mx6sxsabresd.h
include/configs/mx6ul_14x14_evk.h
include/configs/mx7dsabresd.h
include/configs/nitrogen6x.h
include/configs/novena.h
include/configs/ot1200.h
include/configs/platinum.h
include/configs/tbs2910.h
include/configs/titanium.h
include/configs/tqma6.h
include/configs/usbarmory.h
include/configs/vf610twr.h
include/configs/wandboard.h
include/configs/warp.h
include/configs/woodburn_common.h

diff --git a/README b/README
index a13705ae7a846bc5d7f51a21e21f81c4fc87810e..c22b60b49bc015a86ffeca224850cb11811bad7f 100644 (file)
--- a/README
+++ b/README
@@ -2359,16 +2359,20 @@ CBFS (Coreboot Filesystem) support
 
                - drivers/i2c/i2c_mxc.c
                  - activate this driver with CONFIG_SYS_I2C_MXC
+                 - enable bus 1 with CONFIG_SYS_I2C_MXC_I2C1
+                 - enable bus 2 with CONFIG_SYS_I2C_MXC_I2C2
+                 - enable bus 3 with CONFIG_SYS_I2C_MXC_I2C3
+                 - enable bus 4 with CONFIG_SYS_I2C_MXC_I2C4
                  - define speed for bus 1 with CONFIG_SYS_MXC_I2C1_SPEED
                  - define slave for bus 1 with CONFIG_SYS_MXC_I2C1_SLAVE
                  - define speed for bus 2 with CONFIG_SYS_MXC_I2C2_SPEED
                  - define slave for bus 2 with CONFIG_SYS_MXC_I2C2_SLAVE
                  - define speed for bus 3 with CONFIG_SYS_MXC_I2C3_SPEED
                  - define slave for bus 3 with CONFIG_SYS_MXC_I2C3_SLAVE
+                 - define speed for bus 4 with CONFIG_SYS_MXC_I2C4_SPEED
+                 - define slave for bus 4 with CONFIG_SYS_MXC_I2C4_SLAVE
                If those defines are not set, default value is 100000
                for speed, and 0 for slave.
-                 - enable bus 3 with CONFIG_SYS_I2C_MXC_I2C3
-                 - enable bus 4 with CONFIG_SYS_I2C_MXC_I2C4
 
                - drivers/i2c/rcar_i2c.c:
                  - activate this driver with CONFIG_SYS_I2C_RCAR
index f1056e21a2c82dbc053eef99d9e53cec496dcd3a..0f977d706d4f409f92e2b13bd8c6625d854a19f5 100644 (file)
@@ -612,16 +612,22 @@ static u32 mxc_i2c_set_bus_speed(struct i2c_adapter *adap, uint speed)
 /*
  * Register mxc i2c adapters
  */
+#ifdef CONFIG_SYS_I2C_MXC_I2C1
 U_BOOT_I2C_ADAP_COMPLETE(mxc0, mxc_i2c_init, mxc_i2c_probe,
                         mxc_i2c_read, mxc_i2c_write,
                         mxc_i2c_set_bus_speed,
                         CONFIG_SYS_MXC_I2C1_SPEED,
                         CONFIG_SYS_MXC_I2C1_SLAVE, 0)
+#endif
+
+#ifdef CONFIG_SYS_I2C_MXC_I2C2
 U_BOOT_I2C_ADAP_COMPLETE(mxc1, mxc_i2c_init, mxc_i2c_probe,
                         mxc_i2c_read, mxc_i2c_write,
                         mxc_i2c_set_bus_speed,
                         CONFIG_SYS_MXC_I2C2_SPEED,
                         CONFIG_SYS_MXC_I2C2_SLAVE, 1)
+#endif
+
 #ifdef CONFIG_SYS_I2C_MXC_I2C3
 U_BOOT_I2C_ADAP_COMPLETE(mxc2, mxc_i2c_init, mxc_i2c_probe,
                         mxc_i2c_read, mxc_i2c_write,
index 43fbdd3d11d69df7f5f4725493294c70f527bac5..49fbcac7760513972d07ae9046f977df1b82658f 100644 (file)
 #ifdef CONFIG_CMD_I2C
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1                /* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2                /* enable I2C bus 2 */
 #define CONFIG_SYS_MXC_I2C1_SPEED      100000  /* 100 kHz */
 #define CONFIG_SYS_MXC_I2C1_SLAVE      0x7F
 #define CONFIG_SYS_MXC_I2C2_SPEED      100000  /* 100 kHz */
index 20afdd6bc07bc1dba47ce99a9f156a50b8f9ecc9..f03297e137762199fcdddb85683748266b5197f4 100644 (file)
 #define CONFIG_CMD_I2C
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1                /* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2                /* enable I2C bus 2 */
 #define CONFIG_SYS_I2C_MXC_I2C3                /* enable I2C bus 3 */
 #define CONFIG_SYS_I2C_SPEED           100000
 #define CONFIG_SYS_I2C_SLAVE           0x7f
index 7158ab0f2b8307f93bdfd423cfa460699e58f5e8..e0aa4b08949aca714ab51b8b9eb01cda52472dbe 100644 (file)
@@ -39,6 +39,8 @@
 #define CONFIG_CMD_I2C
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1                /* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2                /* enable I2C bus 2 */
 #define CONFIG_SYS_I2C_MXC_I2C2                /* enable I2C bus 2 */
 #define CONFIG_SYS_I2C_SPEED             100000
 
index 12734a10bfdefea6c7004272b3e46c701efa95ff..05132047b78595cf3377d42223d52a1e9a4d6ecd 100644 (file)
 /* I2C */
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1                /* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2                /* enable I2C bus 2 */
 #define CONFIG_SYS_I2C_MXC_I2C3                /* enable I2C bus 3 */
 #define CONFIG_SYS_I2C_SPEED           100000
 #define CONFIG_SYS_MXC_I2C3_SPEED      400000
index 58cee96ac313b3a2f58d248392fd2d8b07bb9a7d..f55ba9f7066ba5649891823c8f4689dcea3b782c 100644 (file)
@@ -33,6 +33,8 @@
 #define CONFIG_CMD_I2C
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1                /* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2                /* enable I2C bus 2 */
 #define CONFIG_SYS_I2C_MXC_I2C3                /* enable I2C bus 3 */
 #define CONFIG_SYS_I2C_SPEED           100000
 
index 5b4b0119573f3b80a767ab554242bc388aba612b..f646feefa9e2f6fd278d996699b0ba6737b905f9 100644 (file)
@@ -52,6 +52,8 @@
  */
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1                /* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2                /* enable I2C bus 2 */
 #define CONFIG_SYS_I2C_MXC_I2C3                /* enable I2C bus 3 */
 #define CONFIG_SYS_SPD_BUS_NUM         2 /* I2C3 */
 #define CONFIG_SYS_MXC_I2C3_SLAVE      0xfe
index 231bea7855c416b8ebc871d370f4adc75bbff619..484d76305fdc485eb60c8f0aa39463c19cd9f968 100644 (file)
 #define CONFIG_CMD_I2C
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1                /* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2                /* enable I2C bus 2 */
 #define CONFIG_SYS_I2C_MXC_I2C3                /* enable I2C bus 3 */
 #define CONFIG_SYS_I2C_SPEED           100000
 #define CONFIG_I2C_GSC                 0
index 86f327c82788b67004698ef4935ae8ad5bb0cfae..3bea71b969e3de77e80cd9f9deb131acf9c76984 100644 (file)
@@ -38,6 +38,8 @@
 
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1                /* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2                /* enable I2C bus 2 */
 #define CONFIG_SYS_I2C_MXC_I2C3                /* enable I2C bus 3 */
 #define CONFIG_SYS_I2C_CLK_OFFSET      I2C2_CLK_OFFSET
 
index b44f3264e318e2154ee25f12db63118136d07721..f73900fe30cbc63237d03a2fc5b8305e19b2b224 100644 (file)
@@ -389,6 +389,8 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_CMD_I2C
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1                /* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2                /* enable I2C bus 2 */
 #define CONFIG_SYS_I2C_MXC_I2C3                /* enable I2C bus 3 */
 
 /*
index 7dcb719b0133af50814dabfa8bf4316cf868b4fe..f6bd5fcece1fff05b69f50a77f2b589f42060886 100644 (file)
 #define CONFIG_CMD_I2C
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1                /* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2                /* enable I2C bus 2 */
 #define CONFIG_SYS_I2C_MXC_I2C3                /* enable I2C bus 3 */
 
 /* EEPROM */
index 2dbb5f70a98979dfdcaf3adfd90d8c8a871b6dea..55b909ceacab97f1dc2d608608004cb281ad3297 100644 (file)
@@ -97,6 +97,8 @@
 #define CONFIG_CMD_I2C
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1                /* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2                /* enable I2C bus 2 */
 #define CONFIG_SYS_I2C_MXC_I2C3                /* enable I2C bus 3 */
 #define CONFIG_SYS_I2C_MXC_I2C4                /* enable I2C bus 4 */
 
index 35058e222ac3677b9d4957a931af63876f182dc7..8853d8fcc06ec293893ed27225d938023c2686e6 100644 (file)
 #ifdef CONFIG_CMD_I2C
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1                /* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2                /* enable I2C bus 2 */
 #define CONFIG_SYS_I2C_MXC_I2C3                /* enable I2C bus 3 */
 #define CONFIG_SYS_RTC_BUS_NUM         1 /* I2C2 */
 #endif
index bd7216e47b63a7b297e1fd377bb48270f209df9e..04140865f48fbef2dd59c730f7eb6de1472f3a9f 100644 (file)
 #define CONFIG_CMD_I2C
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1                /* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2                /* enable I2C bus 2 */
 
 /* RTC */
 #define CONFIG_RTC_IMXDI
index c9983f3f58cd605ff247f4dffbe68d266011844b..6bfdaa6432fffb2b97fa81ebc1962a67830d87eb 100644 (file)
@@ -42,6 +42,8 @@
  */
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1                /* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2                /* enable I2C bus 2 */
 #define CONFIG_SYS_I2C_MXC_I2C3                /* enable I2C bus 3 */
 #define CONFIG_MXC_SPI
 #define CONFIG_MXC_GPIO
index 0479195d6d7143a6975dd2cd7e6588baaa37019b..b889c254ccb307f6aa2c81d6d3393bf33413c99b 100644 (file)
@@ -48,6 +48,8 @@
 #define CONFIG_CMD_I2C
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1                /* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2                /* enable I2C bus 2 */
 #define CONFIG_SYS_I2C_MXC_I2C3                /* enable I2C bus 3 */
 
 /* MMC Configs */
index 82c8af802f0438987e55b35657b33814927dfa38..4f304ed89f97c3431d6cd013cb50cbc1c0f62e7b 100644 (file)
@@ -41,6 +41,8 @@
 #define CONFIG_CMD_I2C
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1                /* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2                /* enable I2C bus 2 */
 #define CONFIG_SYS_I2C_MXC_I2C3                /* enable I2C bus 3 */
 
 /* PMIC Configs */
index ad2629da723c78821fbf3e148b3be52a3b0a821c..3a65861e5e9a347068bfb8b13762acb6c9dae638 100644 (file)
@@ -76,6 +76,8 @@
 /* I2C Configs */
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1                /* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2                /* enable I2C bus 2 */
 #define CONFIG_SYS_I2C_MXC_I2C3                /* enable I2C bus 3 */
 
 /* PMIC Controller */
index bcdb05436059031ddb60242b624dc1997bc42460..e46f2eeecbbbade3020f3feb8290f241d7f2073f 100644 (file)
@@ -38,6 +38,8 @@
 #define CONFIG_CMD_I2C
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1                /* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2                /* enable I2C bus 2 */
 #define CONFIG_SYS_I2C_MXC_I2C3                /* enable I2C bus 3 */
 
 /* MMC Configs */
index 11cf538b0adfcc63c3fd248e4718875dcc3cb263..1c998058a94f1baa593490e7d067f3a432f1df62 100644 (file)
@@ -51,6 +51,8 @@
 #define CONFIG_CMD_I2C
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1                /* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2                /* enable I2C bus 2 */
 #define CONFIG_SYS_I2C_MXC_I2C3                /* enable I2C bus 3 */
 #define CONFIG_SYS_I2C_SPEED           100000
 
index 5f635ca6c5a9fc4cd897632d84f9e69b119ef9f5..e9e3b27f36355c43ae1cd0d3667abbe24c30921b 100644 (file)
@@ -44,6 +44,8 @@
 #define CONFIG_CMD_I2C
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1                /* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2                /* enable I2C bus 2 */
 #define CONFIG_SYS_I2C_MXC_I2C3                /* enable I2C bus 3 */
 #define CONFIG_SYS_I2C_SPEED             100000
 
index 51b297a1a3553bb51aaf09de8b2b36d763e77ef0..ae395035423b413bef2141337e7cd5fc11848f57 100644 (file)
@@ -35,6 +35,8 @@
 #define CONFIG_CMD_I2C
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1                /* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2                /* enable I2C bus 2 */
 #define CONFIG_SYS_I2C_MXC_I2C3                /* enable I2C bus 3 */
 #define CONFIG_SYS_I2C_SPEED             100000
 
index 381eaa24d5395a4d7c152d4fd7fb5ff4d30acfea..edf7d3f93a05772a49f7e944fdb949f7e0d4cb58 100644 (file)
 #define CONFIG_CMD_I2C
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1                /* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2                /* enable I2C bus 2 */
 #define CONFIG_SYS_I2C_MXC_I2C3                /* enable I2C bus 3 */
 #define CONFIG_SYS_I2C_SPEED             100000
 
index 465ddee8817ee4b2a0e35fd6e042e13c32f0d6a9..d5faae6a7b937f14a7cc595d5d4666fb5cb34a8f 100644 (file)
@@ -54,6 +54,8 @@
 #ifdef CONFIG_CMD_I2C
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1                /* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2                /* enable I2C bus 2 */
 #define CONFIG_SYS_I2C_SPEED           100000
 
 /* PMIC only for 9X9 EVK */
index ada5de8acaade131743cf70fa7460db4345dde84..f16f9c1271eb214ea76cb0ff10989ae59c106244 100644 (file)
@@ -47,7 +47,7 @@
 #define CONFIG_CMD_I2C
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_MXC
-#define CONFIG_SYS_I2C_MXC_I2C1
+#define CONFIG_SYS_I2C_MXC_I2C1                /* enable I2C bus 1 */
 #define CONFIG_SYS_I2C_SPEED           100000
 
 #define CONFIG_SUPPORT_EMMC_BOOT       /* eMMC specific */
index dd4cb0f8931103637c77b5ef597e52f3f24bb275..b1137713e1ea8cdb5b39fc7bb8ae47fe570253b4 100644 (file)
@@ -43,6 +43,8 @@
 #define CONFIG_CMD_I2C
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1                /* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2                /* enable I2C bus 2 */
 #define CONFIG_SYS_I2C_MXC_I2C3                /* enable I2C bus 3 */
 #define CONFIG_SYS_I2C_SPEED           100000
 #define CONFIG_I2C_EDID
index 0970fd75483e7ab9628bd76ff163bc0532587436..cd426be18c6ad5c6e9e3144bd768b2cda19f4d96 100644 (file)
 /* I2C */
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1                /* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2                /* enable I2C bus 2 */
 #define CONFIG_SYS_I2C_MXC_I2C3                /* enable I2C bus 3 */
 #define CONFIG_I2C_MULTI_BUS
 #define CONFIG_I2C_MXC
index 0d06fce1eb28b53c5b4947bd4cd2a8a9e63763b1..426ec7246f725bcf1602c8e976768a136a4daaf3 100644 (file)
@@ -44,6 +44,8 @@
 #define CONFIG_CMD_I2C
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1                /* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2                /* enable I2C bus 2 */
 #define CONFIG_SYS_I2C_MXC_I2C3                /* enable I2C bus 3 */
 #define CONFIG_SYS_I2C_SPEED            100000
 
index d65143240b6459244b1d81ace0956aa1c90537c1..bb7e84518380d188b90f4990aeb958499d969678 100644 (file)
@@ -45,6 +45,8 @@
 /* I2C config */
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1                /* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2                /* enable I2C bus 2 */
 #define CONFIG_SYS_I2C_MXC_I2C3                /* enable I2C bus 3 */
 #define CONFIG_SYS_I2C_SPEED                   100000
 
index 4534695598b0707d42b6062140f5a871c268ebcd..17b0213362e4af3c5e3b2b5c3fba09432cebb492 100644 (file)
 #ifdef CONFIG_CMD_I2C
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1                /* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2                /* enable I2C bus 2 */
 #define CONFIG_SYS_I2C_MXC_I2C3                /* enable I2C bus 3 */
 #define CONFIG_SYS_I2C_SPEED           100000
 #define CONFIG_I2C_EDID
index 1b4ca295bc8f440188f9bafdf7241776da4b3c9c..acfa84ab2cdf486a410f81b2543dc787b4aeafa6 100644 (file)
@@ -33,6 +33,8 @@
 #define CONFIG_CMD_I2C
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1                /* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2                /* enable I2C bus 2 */
 #define CONFIG_SYS_I2C_MXC_I2C3                /* enable I2C bus 3 */
 #define CONFIG_SYS_I2C_SPEED           100000
 
index f7fade12f1b9f1f8dae673595b28f5f45b090b05..295e16303ca23ec61c4a9a3f2ff8b73204c8ab4e 100644 (file)
@@ -62,6 +62,8 @@
 #define CONFIG_CMD_I2C
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1                /* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2                /* enable I2C bus 2 */
 #define CONFIG_SYS_I2C_MXC_I2C3                /* enable I2C bus 3 */
 #define CONFIG_I2C_MULTI_BUS
 #define CONFIG_SYS_I2C_SPEED           100000
index 4a7702cd092515cf64ca95557bc2f0dd41ad8fb3..714e3e2ca2160cbb7292603349411086d0119164 100644 (file)
@@ -67,6 +67,8 @@
 #define CONFIG_CMD_I2C
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1                /* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2                /* enable I2C bus 2 */
 
 /* Fuse */
 #define CONFIG_CMD_FUSE
index c5131af3403df9579536f1f6250ff042eea19cf6..324ba8f0ccdc9cf15f3647bac9c44ca3536b5bf9 100644 (file)
 #define CONFIG_CMD_I2C
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1                /* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2                /* enable I2C bus 2 */
 #define CONFIG_SYS_SPD_BUS_NUM         0
 
 #define CONFIG_BOOTDELAY               3
index f4e9cf20c53c3520758b8d7dd4fde6e80351c55d..6e8aec267def1b6cfc05c2af3810019a0aa7289b 100644 (file)
@@ -37,6 +37,8 @@
 #define CONFIG_CMD_I2C
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1                /* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2                /* enable I2C bus 2 */
 #define CONFIG_SYS_I2C_MXC_I2C3                /* enable I2C bus 3 */
 #define CONFIG_SYS_I2C_SPEED           100000
 
index fa102bbae72888bfe69893c1c2434470dc0c2f40..3e9a5a3ef3767cd387bb3f5343aa6dcd3e2219d8 100644 (file)
@@ -98,6 +98,8 @@
 #define CONFIG_CMD_I2C
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1                /* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2                /* enable I2C bus 2 */
 #define CONFIG_SYS_I2C_SPEED             100000
 
 /* PMIC */
index 5d9f5297ce81e691efcf8805f364e6875da8392f..fc4656567da132bc6ef6b8088a8425dca74506c3 100644 (file)
@@ -47,6 +47,8 @@
  */
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1                /* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2                /* enable I2C bus 2 */
 #define CONFIG_SYS_I2C_MXC_I2C3                /* enable I2C bus 3 */
 #define CONFIG_SYS_SPD_BUS_NUM         0
 #define CONFIG_MXC_SPI