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1/*
2 * (C) Copyright 2005
3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
4 * John Otken, jotken@softadvances.com
5 *
1a459660 6 * SPDX-License-Identifier: GPL-2.0+
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7 */
8
9/************************************************************************
10 * luan.h - configuration for LUAN board
11 ***********************************************************************/
12#ifndef __CONFIG_H
13#define __CONFIG_H
14
15/*-----------------------------------------------------------------------
16 * High Level Configuration Options
17 *----------------------------------------------------------------------*/
18#define CONFIG_LUAN 1 /* Board is Luan */
19#define CONFIG_440SP 1 /* Specific PPC440SP support */
20#define CONFIG_4xx 1 /* PPC4xx family */
21#define CONFIG_440 1
22#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
23
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24#define CONFIG_SYS_TEXT_BASE 0xFFFB0000
25
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26/*
27 * Include common defines/options for all AMCC eval boards
28 */
29#define CONFIG_HOSTNAME luan
30#include "amcc-common.h"
31
00cdb4ce 32#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
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33#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
34
35/*-----------------------------------------------------------------------
36 * Base addresses -- Note these are effective addresses where the
37 * actual resources get mapped (not physical addresses)
38 *----------------------------------------------------------------------*/
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39#define CONFIG_SYS_LARGE_FLASH 0xffc00000 /* 4MB flash address CS0 */
40#define CONFIG_SYS_SMALL_FLASH 0xff900000 /* 1MB flash address CS2 */
41#define CONFIG_SYS_SRAM_BASE 0xff800000 /* 1MB SRAM address CS2 */
bf560807 42#define CONFIG_SYS_SRAM_SIZE (1 << 20)
6d0f6bcf 43#define CONFIG_SYS_EPLD_BASE 0xff000000 /* EPLD and FRAM CS1 */
6e7fb6ea 44
6d0f6bcf 45#define CONFIG_SYS_ISRAM_BASE 0xf8000000 /* internal 8k SRAM (L2 cache) */
6e7fb6ea 46
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47#define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped pci memory */
48#define CONFIG_SYS_PCI_BASE 0xd0000000 /* internal PCI regs */
49#define CONFIG_SYS_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CONFIG_SYS_PCI_MEMBASE */
6e7fb6ea 50
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51#if CONFIG_SYS_LARGE_FLASH == 0xffc00000
52#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_LARGE_FLASH
6e7fb6ea 53#else
6d0f6bcf 54#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_SMALL_FLASH
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55#endif
56
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57#if CONFIG_SYS_SRAM_BASE
58#define CONFIG_SYS_KBYTES_SDRAM 1024*2
6e7fb6ea 59#else
6d0f6bcf 60#define CONFIG_SYS_KBYTES_SDRAM 1024
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61#endif
62
63/*-----------------------------------------------------------------------
64 * Initial RAM & stack pointer (placed in SDRAM)
65 *----------------------------------------------------------------------*/
6d0f6bcf 66#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_ISRAM_BASE
553f0982 67#define CONFIG_SYS_INIT_RAM_SIZE (8 << 10)
25ddd1fb 68#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
6d0f6bcf 69#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
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70
71/*-----------------------------------------------------------------------
72 * Serial Port
73 *----------------------------------------------------------------------*/
550650dd 74#define CONFIG_CONS_INDEX 1 /* Use UART0 */
6d0f6bcf 75#define CONFIG_SYS_EXT_SERIAL_CLOCK 11059200 /* external 11.059MHz clk */
6e7fb6ea 76
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77/*-----------------------------------------------------------------------
78 * Environment
79 *----------------------------------------------------------------------*/
80/*
81 * Define here the location of the environment variables (FLASH or EEPROM).
82 * Note: DENX encourages to use redundant environment in FLASH.
83 */
5a1aceb0 84#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
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85
86/*-----------------------------------------------------------------------
87 * FLASH related
88 *----------------------------------------------------------------------*/
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89#define CONFIG_SYS_MAX_FLASH_BANKS 3 /* max number of memory banks */
90#define CONFIG_SYS_MAX_FLASH_SECT 64 /* max number of sectors on one chip */
6e7fb6ea 91
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92#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
93#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
6e7fb6ea 94
6d0f6bcf 95#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
6e7fb6ea 96
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97#define CONFIG_SYS_FLASH_ADDR0 0x555
98#define CONFIG_SYS_FLASH_ADDR1 0x2aa
99#define CONFIG_SYS_FLASH_WORD_SIZE unsigned char
6e7fb6ea 100
5a1aceb0 101#ifdef CONFIG_ENV_IS_IN_FLASH
0e8d1586 102#define CONFIG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
6d0f6bcf 103#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
0e8d1586 104#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
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105
106/* Address and size of Redundant Environment Sector */
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107#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
108#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
5a1aceb0 109#endif /* CONFIG_ENV_IS_IN_FLASH */
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110
111/*-----------------------------------------------------------------------
112 * DDR SDRAM
113 *----------------------------------------------------------------------*/
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114#define CONFIG_SPD_EEPROM 1 /* Use SPD EEPROM for setup */
115#define SPD_EEPROM_ADDRESS {0x53, 0x52} /* SPD i2c spd addresses*/
e4bbed28 116#define CONFIG_DDR_ECC 1 /* with ECC support */
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117
118/*-----------------------------------------------------------------------
119 * I2C
120 *----------------------------------------------------------------------*/
880540de 121#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
6e7fb6ea 122
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123#define CONFIG_SYS_I2C_MULTI_EEPROMS
124#define CONFIG_SYS_I2C_EEPROM_ADDR (0xa8>>1)
125#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
126#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
127#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
4f92ed5f 128
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129/*
130 * Default environment variables
131 */
132#define CONFIG_EXTRA_ENV_SETTINGS \
133 CONFIG_AMCC_DEF_ENV \
134 CONFIG_AMCC_DEF_ENV_PPC \
135 CONFIG_AMCC_DEF_ENV_NOR_UPD \
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136 "kernel_addr=fc000000\0" \
137 "ramdisk_addr=fc100000\0" \
6e7fb6ea 138 ""
6e7fb6ea 139
a00eccfe 140#define CONFIG_HAS_ETH0
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141#define CONFIG_PHY_ADDR 1
142#define CONFIG_CIS8201_PHY 1 /* Enable 'special' RGMII mode for Cicada phy */
143#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
144
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145#ifdef DEBUG
146#define CONFIG_PANIC_HANG
147#else
148#define CONFIG_HW_WATCHDOG /* watchdog */
149#endif
150
7f5c0157 151/*
490f2040 152 * Commands additional to the ones defined in amcc-common.h
7f5c0157 153 */
9bbb1c08 154#define CONFIG_CMD_PCI
9bbb1c08 155#define CONFIG_CMD_SDRAM
6e7fb6ea 156
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157/*-----------------------------------------------------------------------
158 * PCI stuff
159 *-----------------------------------------------------------------------
160 */
9bbb1c08 161#if defined(CONFIG_CMD_PCI)
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162
163/* General PCI */
164#define CONFIG_PCI /* include pci support */
842033e6 165#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
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166#define CONFIG_PCI_PNP /* do (not) pci plug-and-play */
167#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
168
169/* Board-specific PCI */
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170#define CONFIG_SYS_PCI_TARGET_INIT
171#undef CONFIG_SYS_PCI_MASTER_INIT
6e7fb6ea 172
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173#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
174#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x4403 /* whatever */
6e7fb6ea 175
9bbb1c08 176#endif
6e7fb6ea 177
6e7fb6ea 178#endif /* __CONFIG_H */