]>
Commit | Line | Data |
---|---|---|
86ea5f93 | 1 | /* |
a99715b8 | 2 | * (C) Copyright 2006-2008 |
86ea5f93 WD |
3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
4 | * | |
3765b3e7 | 5 | * SPDX-License-Identifier: GPL-2.0+ |
86ea5f93 WD |
6 | */ |
7 | ||
8 | #ifndef __CONFIG_H | |
9 | #define __CONFIG_H | |
10 | ||
11 | /* | |
12 | * High Level Configuration Options | |
13 | * (easy to change) | |
14 | */ | |
15 | ||
16 | #define CONFIG_MPC5200 | |
17 | #define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ | |
18 | #define CONFIG_MCC200 1 /* ... on MCC200 board */ | |
19 | ||
2ae18241 WD |
20 | /* |
21 | * Valid values for CONFIG_SYS_TEXT_BASE are: | |
22 | * 0xFC000000 boot low (standard configuration) | |
23 | * 0xFFF00000 boot high | |
24 | * 0x00100000 boot from RAM (for testing only) | |
25 | */ | |
26 | #ifndef CONFIG_SYS_TEXT_BASE | |
27 | #define CONFIG_SYS_TEXT_BASE 0xFC000000 | |
28 | #endif | |
29 | ||
6d0f6bcf | 30 | #define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33MHz */ |
86ea5f93 WD |
31 | |
32 | #define CONFIG_MISC_INIT_R | |
33 | ||
31d82672 BB |
34 | #define CONFIG_HIGH_BATS 1 /* High BATs supported */ |
35 | ||
86ea5f93 WD |
36 | /* |
37 | * Serial console configuration | |
87791f3b WD |
38 | * |
39 | * To select console on the one of 8 external UARTs, | |
40 | * define CONFIG_QUART_CONSOLE as 1, 2, 3, or 4 for the first Quad UART, | |
41 | * or as 5, 6, 7, or 8 for the second Quad UART. | |
463764c8 | 42 | * COM11, COM12, COM13, COM14 are located on the second Quad UART. |
87791f3b WD |
43 | * |
44 | * CONFIG_PSC_CONSOLE must be undefined in this case. | |
45 | */ | |
ed1cf845 WD |
46 | #if !defined(CONFIG_PRS200) |
47 | /* MCC200 configuration: */ | |
463764c8 WD |
48 | #ifdef CONFIG_CONSOLE_COM12 |
49 | #define CONFIG_QUART_CONSOLE 6 /* console is on UARTF of QUART2 */ | |
50 | #else | |
51 | #define CONFIG_QUART_CONSOLE 8 /* console is on UARTH of QUART2 */ | |
52 | #endif | |
ed1cf845 WD |
53 | #else |
54 | /* PRS200 configuration: */ | |
55 | #undef CONFIG_QUART_CONSOLE | |
56 | #endif /* CONFIG_PRS200 */ | |
87791f3b WD |
57 | /* |
58 | * To select console on PSC1, define CONFIG_PSC_CONSOLE as 1 | |
59 | * and undefine CONFIG_QUART_CONSOLE. | |
86ea5f93 | 60 | */ |
ed1cf845 WD |
61 | #if !defined(CONFIG_PRS200) |
62 | /* MCC200 configuration: */ | |
0fd30252 WD |
63 | #define CONFIG_PSC_CONSOLE 1 /* PSC1 may be COM */ |
64 | #define CONFIG_PSC_CONSOLE2 2 /* PSC2 is PSoC */ | |
ed1cf845 WD |
65 | #else |
66 | /* PRS200 configuration: */ | |
67 | #define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ | |
68 | #endif | |
86ea5f93 | 69 | #define CONFIG_BAUDRATE 115200 |
6d0f6bcf | 70 | #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } |
86ea5f93 | 71 | |
86ea5f93 | 72 | #define CONFIG_MII 1 |
86ea5f93 | 73 | |
86ea5f93 WD |
74 | #define CONFIG_DOS_PARTITION |
75 | ||
76 | /* USB */ | |
86ea5f93 | 77 | #define CONFIG_USB_OHCI |
86ea5f93 | 78 | #define CONFIG_USB_STORAGE |
cdb97a66 AS |
79 | /* automatic software updates (see board/mcc200/auto_update.c) */ |
80 | #define CONFIG_AUTO_UPDATE 1 | |
86ea5f93 | 81 | |
5dc11a51 | 82 | |
7f5c0157 JL |
83 | /* |
84 | * BOOTP options | |
85 | */ | |
86 | #define CONFIG_BOOTP_BOOTFILESIZE | |
87 | #define CONFIG_BOOTP_BOOTPATH | |
88 | #define CONFIG_BOOTP_GATEWAY | |
89 | #define CONFIG_BOOTP_HOSTNAME | |
90 | ||
91 | ||
86ea5f93 | 92 | /* |
5dc11a51 | 93 | * Command line configuration. |
86ea5f93 | 94 | */ |
5dc11a51 JL |
95 | #include <config_cmd_default.h> |
96 | ||
97 | #define CONFIG_CMD_BEDBUG | |
98 | #define CONFIG_CMD_FAT | |
99 | #define CONFIG_CMD_I2C | |
100 | #define CONFIG_CMD_USB | |
86ea5f93 | 101 | |
a4d2636f | 102 | #undef CONFIG_CMD_NET |
085ecde1 | 103 | #undef CONFIG_CMD_NFS |
86ea5f93 WD |
104 | |
105 | /* | |
106 | * Autobooting | |
107 | */ | |
a4d2636f | 108 | #define CONFIG_BOOTDELAY 1 /* autoboot after 1 second */ |
86ea5f93 WD |
109 | |
110 | #define CONFIG_PREBOOT "echo;" \ | |
32bf3d14 | 111 | "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ |
86ea5f93 WD |
112 | "echo" |
113 | ||
114 | #undef CONFIG_BOOTARGS | |
115 | ||
ed1cf845 | 116 | #ifdef CONFIG_PRS200 |
6d0f6bcf JCPV |
117 | # define CONFIG_SYS__BOARDNAME "prs200" |
118 | # define CONFIG_SYS__LINUX_CONSOLE "ttyS0" | |
ed1cf845 | 119 | #else |
6d0f6bcf JCPV |
120 | # define CONFIG_SYS__BOARDNAME "mcc200" |
121 | # define CONFIG_SYS__LINUX_CONSOLE "ttyEU5" | |
ed1cf845 WD |
122 | #endif |
123 | ||
a4d2636f WD |
124 | /* Network */ |
125 | #define CONFIG_ETHADDR 00:17:17:ff:00:00 | |
126 | #define CONFIG_IPADDR 10.76.9.29 | |
127 | #define CONFIG_SERVERIP 10.76.9.1 | |
128 | ||
129 | #include <version.h> /* For U-Boot version */ | |
130 | ||
ed1cf845 | 131 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
a4d2636f | 132 | "ubootver=" U_BOOT_VERSION "\0" \ |
86ea5f93 | 133 | "netdev=eth0\0" \ |
5368c55d | 134 | "hostname=" CONFIG_SYS__BOARDNAME "\0" \ |
86ea5f93 WD |
135 | "nfsargs=setenv bootargs root=/dev/nfs rw " \ |
136 | "nfsroot=${serverip}:${rootpath}\0" \ | |
a4d2636f WD |
137 | "ramargs=setenv bootargs root=/dev/mtdblock2 " \ |
138 | "rootfstype=cramfs\0" \ | |
86ea5f93 WD |
139 | "addip=setenv bootargs ${bootargs} " \ |
140 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ | |
141 | ":${hostname}:${netdev}:off panic=1\0" \ | |
113f64e0 | 142 | "addcons=setenv bootargs ${bootargs} " \ |
a99715b8 DZ |
143 | "console=${console},${baudrate} " \ |
144 | "ubootver=${ubootver} board=${board}\0" \ | |
ed1cf845 | 145 | "flash_nfs=run nfsargs addip addcons;" \ |
86ea5f93 | 146 | "bootm ${kernel_addr}\0" \ |
ed1cf845 | 147 | "flash_self=run ramargs addip addcons;" \ |
86ea5f93 | 148 | "bootm ${kernel_addr} ${ramdisk_addr}\0" \ |
ed1cf845 WD |
149 | "net_nfs=tftp 200000 ${bootfile};" \ |
150 | "run nfsargs addip addcons;bootm\0" \ | |
6d0f6bcf | 151 | "console=" CONFIG_SYS__LINUX_CONSOLE "\0" \ |
82f2e33a | 152 | "rootpath=/opt/eldk/ppc_6xx\0" \ |
6d0f6bcf JCPV |
153 | "bootfile=/tftpboot/" CONFIG_SYS__BOARDNAME "/uImage\0" \ |
154 | "load=tftp 200000 /tftpboot/" CONFIG_SYS__BOARDNAME "/u-boot.bin\0" \ | |
5368c55d | 155 | "text_base=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ |
a4d2636f | 156 | "kernel_addr=0xFC0C0000\0" \ |
ed1cf845 WD |
157 | "update=protect off ${text_base} +${filesize};" \ |
158 | "era ${text_base} +${filesize};" \ | |
159 | "cp.b 200000 ${text_base} ${filesize}\0" \ | |
58ad4978 | 160 | "unlock=yes\0" \ |
86ea5f93 WD |
161 | "" |
162 | ||
163 | #define CONFIG_BOOTCOMMAND "run flash_self" | |
164 | ||
6d0f6bcf | 165 | #define CONFIG_SYS_HUSH_PARSER 1 /* use "hush" command parser */ |
82f2e33a | 166 | |
86ea5f93 WD |
167 | /* |
168 | * IPB Bus clocking configuration. | |
169 | */ | |
6d0f6bcf | 170 | #define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ |
86ea5f93 | 171 | |
86ea5f93 WD |
172 | /* |
173 | * I2C configuration | |
174 | */ | |
175 | #define CONFIG_HARD_I2C 1 /* I2C with hardware support */ | |
6d0f6bcf | 176 | #define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #1 or #2 */ |
86ea5f93 | 177 | |
6d0f6bcf JCPV |
178 | #define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */ |
179 | #define CONFIG_SYS_I2C_SLAVE 0x7F | |
86ea5f93 | 180 | |
86ea5f93 WD |
181 | /* |
182 | * Flash configuration (8,16 or 32 MB) | |
183 | * TEXT base always at 0xFFF00000 | |
184 | * ENV_ADDR always at 0xFFF40000 | |
58ad4978 | 185 | * FLASH_BASE at 0xFC000000 for 64 MB (only 32MB are supported, not enough addr lines!!!) |
360b4103 WD |
186 | * 0xFE000000 for 32 MB |
187 | * 0xFF000000 for 16 MB | |
188 | * 0xFF800000 for 8 MB | |
86ea5f93 | 189 | */ |
6d0f6bcf JCPV |
190 | #define CONFIG_SYS_FLASH_BASE 0xfc000000 |
191 | #define CONFIG_SYS_FLASH_SIZE 0x04000000 | |
86ea5f93 | 192 | |
6d0f6bcf | 193 | #define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */ |
00b1883a | 194 | #define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */ |
86ea5f93 | 195 | |
6d0f6bcf | 196 | #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } |
86ea5f93 | 197 | |
6d0f6bcf JCPV |
198 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
199 | #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */ | |
86ea5f93 | 200 | |
6d0f6bcf JCPV |
201 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ |
202 | #define CONFIG_SYS_FLASH_PROTECTION 1 /* hardware flash protection */ | |
86ea5f93 | 203 | |
6d0f6bcf JCPV |
204 | #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ |
205 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ | |
86ea5f93 | 206 | |
6d0f6bcf JCPV |
207 | #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ |
208 | #define CONFIG_SYS_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */ | |
58ad4978 | 209 | |
5a1aceb0 | 210 | #define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ |
58ad4978 | 211 | |
0e8d1586 | 212 | #define CONFIG_ENV_SECT_SIZE 0x40000 /* size of one complete sector */ |
6d0f6bcf | 213 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) |
0e8d1586 | 214 | #define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ |
58ad4978 SR |
215 | |
216 | /* Address and size of Redundant Environment Sector */ | |
0e8d1586 JCPV |
217 | #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) |
218 | #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) | |
58ad4978 SR |
219 | |
220 | #define CONFIG_ENV_OVERWRITE 1 /* allow modification of vendor params */ | |
86ea5f93 | 221 | |
14d0a02a | 222 | #if CONFIG_SYS_TEXT_BASE == CONFIG_SYS_FLASH_BASE |
6d0f6bcf | 223 | #define CONFIG_SYS_LOWBOOT 1 |
f149d864 WD |
224 | #endif |
225 | ||
86ea5f93 WD |
226 | /* |
227 | * Memory map | |
228 | */ | |
6d0f6bcf JCPV |
229 | #define CONFIG_SYS_MBAR 0xf0000000 |
230 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 | |
231 | #define CONFIG_SYS_DEFAULT_MBAR 0x80000000 | |
86ea5f93 WD |
232 | |
233 | /* Use SRAM until RAM will be available */ | |
6d0f6bcf | 234 | #define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM |
553f0982 | 235 | #define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE /* Size of used area in DPRAM */ |
86ea5f93 WD |
236 | |
237 | ||
25ddd1fb | 238 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
6d0f6bcf | 239 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
86ea5f93 | 240 | |
14d0a02a | 241 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE |
6d0f6bcf JCPV |
242 | #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) |
243 | # define CONFIG_SYS_RAMBOOT 1 | |
86ea5f93 WD |
244 | #endif |
245 | ||
6d0f6bcf JCPV |
246 | #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ |
247 | #define CONFIG_SYS_MALLOC_LEN (512 << 10) /* Reserve 512 kB for malloc() */ | |
248 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ | |
86ea5f93 WD |
249 | |
250 | /* | |
251 | * Ethernet configuration | |
252 | */ | |
86321fc1 BW |
253 | /* #define CONFIG_MPC5xxx_FEC 1 */ |
254 | /* #define CONFIG_MPC5xxx_FEC_MII100 */ | |
86ea5f93 | 255 | /* |
86321fc1 | 256 | * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb |
86ea5f93 | 257 | */ |
86321fc1 | 258 | /* #define CONFIG_MPC5xxx_FEC_MII10 */ |
58ad4978 | 259 | #define CONFIG_PHY_ADDR 1 |
86ea5f93 | 260 | |
e8143e72 WD |
261 | /* |
262 | * LCD Splash Screen | |
263 | */ | |
360b4103 | 264 | #if !defined(CONFIG_PRS200) |
e8143e72 | 265 | #define CONFIG_LCD 1 |
638dd145 | 266 | #define CONFIG_PROGRESSBAR 1 |
360b4103 WD |
267 | #endif |
268 | ||
e8143e72 WD |
269 | #if defined(CONFIG_LCD) |
270 | #define CONFIG_SPLASH_SCREEN 1 | |
6d0f6bcf | 271 | #define CONFIG_SYS_CONSOLE_IS_IN_ENV 1 |
360b4103 | 272 | #define LCD_BPP LCD_MONOCHROME |
e8143e72 WD |
273 | #endif |
274 | ||
86ea5f93 WD |
275 | /* |
276 | * GPIO configuration | |
277 | */ | |
bfc81252 WD |
278 | /* 0x10000004 = 32MB SDRAM */ |
279 | /* 0x90000004 = 64MB SDRAM */ | |
e8143e72 WD |
280 | #if defined(CONFIG_LCD) |
281 | /* set PSC2 in UART mode */ | |
6d0f6bcf | 282 | #define CONFIG_SYS_GPS_PORT_CONFIG 0x00000044 |
e8143e72 | 283 | #else |
6d0f6bcf | 284 | #define CONFIG_SYS_GPS_PORT_CONFIG 0x00000004 |
e8143e72 | 285 | #endif |
86ea5f93 WD |
286 | |
287 | /* | |
288 | * Miscellaneous configurable options | |
289 | */ | |
6d0f6bcf | 290 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
5dc11a51 | 291 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 292 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
86ea5f93 | 293 | #else |
6d0f6bcf | 294 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
86ea5f93 | 295 | #endif |
6d0f6bcf JCPV |
296 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
297 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
298 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
86ea5f93 | 299 | |
6d0f6bcf JCPV |
300 | #define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ |
301 | #define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ | |
86ea5f93 | 302 | |
6d0f6bcf | 303 | #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ |
86ea5f93 | 304 | |
6d0f6bcf | 305 | #define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ |
5dc11a51 | 306 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 307 | # define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ |
5dc11a51 JL |
308 | #endif |
309 | ||
86ea5f93 WD |
310 | /* |
311 | * Various low-level settings | |
312 | */ | |
6d0f6bcf JCPV |
313 | #define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI |
314 | #define CONFIG_SYS_HID0_FINAL HID0_ICE | |
86ea5f93 | 315 | |
6d0f6bcf JCPV |
316 | #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE |
317 | #define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE | |
318 | #define CONFIG_SYS_BOOTCS_CFG 0x0004fb00 | |
319 | #define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE | |
320 | #define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE | |
86ea5f93 | 321 | |
05d8dce9 | 322 | /* Quad UART @0x80000000 (MBAR is relocated to 0xF0000000) */ |
6d0f6bcf JCPV |
323 | #define CONFIG_SYS_CS2_START 0x80000000 |
324 | #define CONFIG_SYS_CS2_SIZE 0x00001000 | |
325 | #define CONFIG_SYS_CS2_CFG 0x1d300 | |
05d8dce9 | 326 | |
a874c8c6 | 327 | /* Second Quad UART @0x80010000 */ |
6d0f6bcf JCPV |
328 | #define CONFIG_SYS_CS1_START 0x80010000 |
329 | #define CONFIG_SYS_CS1_SIZE 0x00001000 | |
330 | #define CONFIG_SYS_CS1_CFG 0x1d300 | |
a874c8c6 | 331 | |
a4d2636f WD |
332 | /* Leica - build revision resistors */ |
333 | /* | |
6d0f6bcf JCPV |
334 | #define CONFIG_SYS_CS3_START 0x80020000 |
335 | #define CONFIG_SYS_CS3_SIZE 0x00000004 | |
336 | #define CONFIG_SYS_CS3_CFG 0x1d300 | |
a4d2636f WD |
337 | */ |
338 | ||
87791f3b WD |
339 | /* |
340 | * Select one of quarts as a default | |
341 | * console. If undefined - PSC console | |
342 | * wil be default | |
343 | */ | |
6d0f6bcf JCPV |
344 | #define CONFIG_SYS_CS_BURST 0x00000000 |
345 | #define CONFIG_SYS_CS_DEADCYCLE 0x33333333 | |
86ea5f93 | 346 | |
6d0f6bcf | 347 | #define CONFIG_SYS_RESET_ADDRESS 0xff000000 |
86ea5f93 | 348 | |
87791f3b WD |
349 | /* |
350 | * QUART Expanders support | |
351 | */ | |
352 | #if defined(CONFIG_QUART_CONSOLE) | |
353 | /* | |
354 | * We'll use NS16550 chip routines, | |
355 | */ | |
6d0f6bcf JCPV |
356 | #define CONFIG_SYS_NS16550 1 |
357 | #define CONFIG_SYS_NS16550_SERIAL 1 | |
87791f3b WD |
358 | #define CONFIG_CONS_INDEX 1 |
359 | /* | |
360 | * To achieve necessary offset on SC16C554 | |
361 | * A0-A2 (register select) pins with NS16550 | |
362 | * functions (in struct NS16550), REG_SIZE | |
363 | * should be 4, because A0-A2 pins are connected | |
364 | * to DA2-DA4 address bus lines. | |
365 | */ | |
6d0f6bcf | 366 | #define CONFIG_SYS_NS16550_REG_SIZE 4 |
87791f3b WD |
367 | /* |
368 | * LocalPlus Bus already inited in cpu_init_f(), | |
369 | * so can work with QUART's chip selects. | |
370 | * One of four SC16C554 UARTs is selected with | |
371 | * A3-A4 (DA5-DA6) lines. | |
372 | */ | |
ed1cf845 | 373 | #if (CONFIG_QUART_CONSOLE > 0) && (CONFIG_QUART_CONSOLE < 5) && !defined(CONFIG_PRS200) |
6d0f6bcf | 374 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CS2_START | (CONFIG_QUART_CONSOLE - 1)<<5) |
87791f3b | 375 | #elif (CONFIG_QUART_CONSOLE > 4) && (CONFIG_QUART_CONSOLE < 9) |
6d0f6bcf | 376 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CS1_START | (CONFIG_QUART_CONSOLE - 5)<<5) |
efd988eb | 377 | #else |
87791f3b WD |
378 | #error "Wrong QUART expander number." |
379 | #endif | |
380 | ||
381 | /* | |
382 | * SC16C554 chip's external crystal oscillator frequency | |
383 | * is 7.3728 MHz | |
384 | */ | |
6d0f6bcf | 385 | #define CONFIG_SYS_NS16550_CLK 7372800 |
87791f3b | 386 | #endif /* CONFIG_QUART_CONSOLE */ |
86ea5f93 WD |
387 | /*----------------------------------------------------------------------- |
388 | * USB stuff | |
389 | *----------------------------------------------------------------------- | |
390 | */ | |
391 | #define CONFIG_USB_CLOCK 0x0001BBBB | |
392 | #define CONFIG_USB_CONFIG 0x00005000 | |
393 | ||
a4d2636f WD |
394 | #define CONFIG_AUTOBOOT_KEYED /* use key strings to stop autoboot */ |
395 | #define CONFIG_AUTOBOOT_STOP_STR "432" | |
396 | #define CONFIG_SILENT_CONSOLE 1 | |
397 | ||
86ea5f93 | 398 | #endif /* __CONFIG_H */ |