[people/ms/u-boot.git] / include / configs / microblaze-generic.h

/*
 * (C) Copyright 2007-2010 Michal Simek
 *
 * Michal SIMEK <monstr@monstr.eu>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __CONFIG_H
#define __CONFIG_H

#include "../board/xilinx/microblaze-generic/xparameters.h"

/* MicroBlaze CPU */
#define	MICROBLAZE_V5		1

/* linear and spi flash memory */
#ifdef XILINX_FLASH_START
#define	FLASH
#undef	SPIFLASH
#undef	RAMENV	/* hold environment in flash */
#else
#ifdef XILINX_SPI_FLASH_BASEADDR
#undef	FLASH
#define	SPIFLASH
#undef	RAMENV	/* hold environment in flash */
#else
#undef	FLASH
#undef	SPIFLASH
#define	RAMENV	/* hold environment in RAM */
#endif
#endif

/* uart */
# define CONFIG_BAUDRATE	115200
/* The following table includes the supported baudrates */
# define CONFIG_SYS_BAUDRATE_TABLE \
	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}

/* setting reset address */
/*#define	CONFIG_SYS_RESET_ADDRESS	CONFIG_SYS_TEXT_BASE*/

/* ethernet */
#undef CONFIG_SYS_ENET
#if defined(CONFIG_XILINX_EMACLITE)
# define CONFIG_SYS_ENET
#endif
#if defined(XILINX_AXIEMAC_BASEADDR)
# define CONFIG_XILINX_AXIEMAC	1
# define CONFIG_SYS_ENET
#endif

#undef ET_DEBUG

/* gpio */
#ifdef XILINX_GPIO_BASEADDR
# define CONFIG_XILINX_GPIO
# define CONFIG_SYS_GPIO_0_ADDR		XILINX_GPIO_BASEADDR
#endif

/* interrupt controller */
#ifdef XILINX_INTC_BASEADDR
# define CONFIG_SYS_INTC_0_ADDR		XILINX_INTC_BASEADDR
# define CONFIG_SYS_INTC_0_NUM		XILINX_INTC_NUM_INTR_INPUTS
#endif

/* timer */
#if defined(XILINX_TIMER_BASEADDR) && defined(XILINX_TIMER_IRQ)
#  define CONFIG_SYS_TIMER_0_ADDR	XILINX_TIMER_BASEADDR
#  define CONFIG_SYS_TIMER_0_IRQ	XILINX_TIMER_IRQ
#endif

/* watchdog */
#if defined(XILINX_WATCHDOG_BASEADDR) && defined(XILINX_WATCHDOG_IRQ)
# define CONFIG_WATCHDOG_BASEADDR	XILINX_WATCHDOG_BASEADDR
# define CONFIG_WATCHDOG_IRQ		XILINX_WATCHDOG_IRQ
# ifndef CONFIG_SPL_BUILD
#  define CONFIG_HW_WATCHDOG
#  define CONFIG_XILINX_TB_WATCHDOG
# endif
#endif

#if !defined(CONFIG_OF_CONTROL) || \
	(defined(CONFIG_SPL_BUILD) && !defined(CONFIG_SPL_OF_CONTROL))
/* ddr sdram - main memory */
# define CONFIG_SYS_SDRAM_BASE	XILINX_RAM_START
# define CONFIG_SYS_SDRAM_SIZE	XILINX_RAM_SIZE
#endif

#define CONFIG_SYS_MALLOC_LEN	0xC0000

/* Stack location before relocation */
#define CONFIG_SYS_INIT_SP_OFFSET	(CONFIG_SYS_TEXT_BASE - \
					 CONFIG_SYS_MALLOC_F_LEN)

/*
 * CFI flash memory layout - Example
 * CONFIG_SYS_FLASH_BASE = 0x2200_0000;
 * CONFIG_SYS_FLASH_SIZE = 0x0080_0000;	  8MB
 *
 * SECT_SIZE = 0x20000;			128kB is one sector
 * CONFIG_ENV_SIZE = SECT_SIZE;		128kB environment store
 *
 * 0x2200_0000	CONFIG_SYS_FLASH_BASE
 *					FREE		256kB
 * 0x2204_0000	CONFIG_ENV_ADDR
 *					ENV_AREA	128kB
 * 0x2206_0000
 *					FREE
 * 0x2280_0000	CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE
 *
 */

#ifdef FLASH
# define CONFIG_SYS_FLASH_BASE		XILINX_FLASH_START
# define CONFIG_SYS_FLASH_SIZE		XILINX_FLASH_SIZE
# define CONFIG_SYS_FLASH_CFI		1
# define CONFIG_FLASH_CFI_DRIVER	1
/* ?empty sector */
# define CONFIG_SYS_FLASH_EMPTY_INFO	1
/* max number of memory banks */
# define CONFIG_SYS_MAX_FLASH_BANKS	1
/* max number of sectors on one chip */
# define CONFIG_SYS_MAX_FLASH_SECT	512
/* hardware flash protection */
# define CONFIG_SYS_FLASH_PROTECTION
/* use buffered writes (20x faster) */
# define	CONFIG_SYS_FLASH_USE_BUFFER_WRITE	1
# ifdef	RAMENV
#  define CONFIG_ENV_IS_NOWHERE	1
#  define CONFIG_ENV_SIZE	0x1000
#  define CONFIG_ENV_ADDR	(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SIZE)

# else	/* FLASH && !RAMENV */
#  define CONFIG_ENV_IS_IN_FLASH	1
/* 128K(one sector) for env */
#  define CONFIG_ENV_SECT_SIZE	0x20000
#  define CONFIG_ENV_ADDR \
			(CONFIG_SYS_FLASH_BASE + (2 * CONFIG_ENV_SECT_SIZE))
#  define CONFIG_ENV_SIZE	0x20000
# endif /* FLASH && !RAMBOOT */
#else /* !FLASH */

#ifdef SPIFLASH
# define CONFIG_SYS_NO_FLASH		1
# define CONFIG_SYS_SPI_BASE		XILINX_SPI_FLASH_BASEADDR
# define CONFIG_SPI			1
# define CONFIG_SF_DEFAULT_MODE		SPI_MODE_3
# define CONFIG_SF_DEFAULT_SPEED	XILINX_SPI_FLASH_MAX_FREQ
# define CONFIG_SF_DEFAULT_CS		XILINX_SPI_FLASH_CS

# ifdef	RAMENV
#  define CONFIG_ENV_IS_NOWHERE	1
#  define CONFIG_ENV_SIZE	0x1000
#  define CONFIG_ENV_ADDR	(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SIZE)

# else	/* SPIFLASH && !RAMENV */
#  define CONFIG_ENV_IS_IN_SPI_FLASH	1
#  define CONFIG_ENV_SPI_MODE		SPI_MODE_3
#  define CONFIG_ENV_SPI_MAX_HZ		CONFIG_SF_DEFAULT_SPEED
#  define CONFIG_ENV_SPI_CS		CONFIG_SF_DEFAULT_CS
/* 128K(two sectors) for env */
#  define CONFIG_ENV_SECT_SIZE	0x10000
#  define CONFIG_ENV_SIZE	(2 * CONFIG_ENV_SECT_SIZE)
/* Warning: adjust the offset in respect of other flash content and size */
#  define CONFIG_ENV_OFFSET	(128 * CONFIG_ENV_SECT_SIZE) /* at 8MB */
# endif /* SPIFLASH && !RAMBOOT */
#else /* !SPIFLASH */

/* ENV in RAM */
# define CONFIG_SYS_NO_FLASH	1
# define CONFIG_ENV_IS_NOWHERE	1
# define CONFIG_ENV_SIZE	0x1000
# define CONFIG_ENV_ADDR	(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SIZE)
#endif /* !SPIFLASH */
#endif /* !FLASH */

/* system ace */
#ifdef XILINX_SYSACE_BASEADDR
# define CONFIG_SYSTEMACE
/* #define DEBUG_SYSTEMACE */
# define SYSTEMACE_CONFIG_FPGA
# define CONFIG_SYS_SYSTEMACE_BASE	XILINX_SYSACE_BASEADDR
# define CONFIG_SYS_SYSTEMACE_WIDTH	XILINX_SYSACE_MEM_WIDTH
# define CONFIG_DOS_PARTITION
#endif

#if defined(XILINX_USE_ICACHE)
# define CONFIG_ICACHE
#else
# undef CONFIG_ICACHE
#endif

#if defined(XILINX_USE_DCACHE)
# define CONFIG_DCACHE
#else
# undef CONFIG_DCACHE
#endif

#ifndef XILINX_DCACHE_BYTE_SIZE
#define XILINX_DCACHE_BYTE_SIZE	32768
#endif

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME

/*
 * Command line configuration.
 */
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_IRQ
#define CONFIG_CMD_MFSL

#if defined(CONFIG_DCACHE) || defined(CONFIG_ICACHE)
# define CONFIG_CMD_CACHE
#else
# undef CONFIG_CMD_CACHE
#endif

#ifdef CONFIG_SYS_ENET
# define CONFIG_CMD_PING
# define CONFIG_CMD_DHCP
# define CONFIG_CMD_TFTPPUT
#endif

#if defined(CONFIG_SYSTEMACE)
# define CONFIG_CMD_EXT2
# define CONFIG_CMD_FAT
#endif

#if defined(FLASH)
# define CONFIG_CMD_JFFS2
# define CONFIG_CMD_UBI
# undef CONFIG_CMD_UBIFS

# if !defined(RAMENV)
#  define CONFIG_CMD_SAVES
# endif

#else
#if defined(SPIFLASH)
# define CONFIG_CMD_SF

# if !defined(RAMENV)
#  define CONFIG_CMD_SAVES
# endif
#else
# undef CONFIG_CMD_JFFS2
# undef CONFIG_CMD_UBI
# undef CONFIG_CMD_UBIFS
#endif
#endif

#if defined(CONFIG_CMD_JFFS2)
# define CONFIG_MTD_PARTITIONS
#endif

#if defined(CONFIG_CMD_UBIFS)
# define CONFIG_CMD_UBI
# define CONFIG_LZO
#endif

#if defined(CONFIG_CMD_UBI)
# define CONFIG_MTD_PARTITIONS
# define CONFIG_RBTREE
#endif

#if defined(CONFIG_MTD_PARTITIONS)
/* MTD partitions */
#define CONFIG_CMD_MTDPARTS	/* mtdparts command line support */
#define CONFIG_MTD_DEVICE	/* needed for mtdparts commands */
#define CONFIG_FLASH_CFI_MTD
#define MTDIDS_DEFAULT		"nor0=flash-0"

/* default mtd partition table */
#define MTDPARTS_DEFAULT	"mtdparts=flash-0:256k(u-boot),"\
				"256k(env),3m(kernel),1m(romfs),"\
				"1m(cramfs),-(jffs2)"
#endif

/* size of console buffer */
#define	CONFIG_SYS_CBSIZE	512
 /* print buffer size */
#define	CONFIG_SYS_PBSIZE \
		(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
/* max number of command args */
#define	CONFIG_SYS_MAXARGS	15
#define	CONFIG_SYS_LONGHELP
/* default load address */
#define	CONFIG_SYS_LOAD_ADDR	XILINX_RAM_START

#define	CONFIG_BOOTDELAY	-1	/* -1 disables auto-boot */
#define	CONFIG_BOOTARGS		"root=romfs"
#define	CONFIG_HOSTNAME		XILINX_BOARD_NAME
#define	CONFIG_BOOTCOMMAND	"base 0;tftp 11000000 image.img;bootm"
#define	CONFIG_IPADDR		192.168.0.3
#define	CONFIG_SERVERIP		192.168.0.5
#define	CONFIG_GATEWAYIP	192.168.0.1

/* architecture dependent code */
#define	CONFIG_SYS_USR_EXCEP	/* user exception */

#define	CONFIG_PREBOOT	"echo U-BOOT for ${hostname};setenv preboot;echo"

#define	CONFIG_EXTRA_ENV_SETTINGS	"unlock=yes\0" \
					"nor0=flash-0\0"\
					"mtdparts=mtdparts=flash-0:"\
					"256k(u-boot),256k(env),3m(kernel),"\
					"1m(romfs),1m(cramfs),-(jffs2)\0"\
					"nc=setenv stdout nc;"\
					"setenv stdin nc\0" \
					"serial=setenv stdout serial;"\
					"setenv stdin serial\0"

#define CONFIG_CMDLINE_EDITING

#define CONFIG_NETCONSOLE
#define CONFIG_SYS_CONSOLE_IS_IN_ENV

/* Use the HUSH parser */
#define CONFIG_SYS_HUSH_PARSER

/* Enable flat device tree support */
#define CONFIG_LMB		1
#define CONFIG_FIT		1
#define CONFIG_OF_LIBFDT	1

#if defined(CONFIG_XILINX_AXIEMAC)
# define CONFIG_MII		1
# define CONFIG_CMD_MII		1
# define CONFIG_PHY_GIGE	1
# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN	1
# define CONFIG_PHY_ATHEROS	1
# define CONFIG_PHY_BROADCOM	1
# define CONFIG_PHY_DAVICOM	1
# define CONFIG_PHY_LXT		1
# define CONFIG_PHY_MARVELL	1
# define CONFIG_PHY_MICREL	1
# define CONFIG_PHY_MICREL_KSZ9021
# define CONFIG_PHY_NATSEMI	1
# define CONFIG_PHY_REALTEK	1
# define CONFIG_PHY_VITESSE	1
#else
# undef CONFIG_MII
# undef CONFIG_CMD_MII
#endif

/* SPL part */
#define CONFIG_CMD_SPL
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_LIBCOMMON_SUPPORT
#define CONFIG_SPL_LIBGENERIC_SUPPORT
#define CONFIG_SPL_SERIAL_SUPPORT
#define CONFIG_SPL_BOARD_INIT

#define CONFIG_SPL_LDSCRIPT	"arch/microblaze/cpu/u-boot-spl.lds"

#define CONFIG_SPL_RAM_DEVICE
#ifdef CONFIG_SYS_FLASH_BASE
# define CONFIG_SPL_NOR_SUPPORT
# define CONFIG_SYS_UBOOT_BASE		CONFIG_SYS_FLASH_BASE
#endif

/* for booting directly linux */
#define CONFIG_SPL_OS_BOOT

#define CONFIG_SYS_OS_BASE		(CONFIG_SYS_FLASH_BASE + \
					 0x60000)
#define CONFIG_SYS_FDT_BASE		(CONFIG_SYS_FLASH_BASE + \
					 0x40000)
#define CONFIG_SYS_SPL_ARGS_ADDR	(CONFIG_SYS_TEXT_BASE + \
					 0x1000000)

/* SP location before relocation, must use scratch RAM */
/* BRAM start */
#define CONFIG_SYS_INIT_RAM_ADDR	0x0
/* BRAM size - will be generated */
#define CONFIG_SYS_INIT_RAM_SIZE	0x100000

# define CONFIG_SPL_STACK_ADDR		(CONFIG_SYS_INIT_RAM_ADDR + \
					 CONFIG_SYS_INIT_RAM_SIZE - \
					 CONFIG_SYS_MALLOC_F_LEN)

/* Just for sure that there is a space for stack */
#define CONFIG_SPL_STACK_SIZE		0x100

#define CONFIG_SYS_UBOOT_START		CONFIG_SYS_TEXT_BASE

#define CONFIG_SPL_MAX_FOOTPRINT	(CONFIG_SYS_INIT_RAM_SIZE - \
					 CONFIG_SYS_INIT_RAM_ADDR - \
					 CONFIG_SYS_MALLOC_F_LEN - \
					 CONFIG_SPL_STACK_SIZE)

#endif	/* __CONFIG_H */
Commit	Line	Data
76316a31	1	/*
4aecfb16	2	* (C) Copyright 2007-2010 Michal Simek
76316a31	3	*
cb1bc63b	4	* Michal SIMEK <monstr@monstr.eu>
76316a31	5	*
1a459660	6	* SPDX-License-Identifier: GPL-2.0+
76316a31 MS	7	*/
	8
	9	#ifndef __CONFIG_H
	10	#define __CONFIG_H
	11
52a822ed	12	#include "../board/xilinx/microblaze-generic/xparameters.h"
76316a31	13
4aecfb16	14	/* MicroBlaze CPU */
1a50f164	15	#define MICROBLAZE_V5 1
76316a31	16
bcec8f49	17	/* linear and spi flash memory */
1fe7e8fa SL	18	#ifdef XILINX_FLASH_START
1fe7e8fa SL	19	#define FLASH
bcec8f49	20	#undef SPIFLASH
1fe7e8fa SL	21	#undef RAMENV /* hold environment in flash */
1fe7e8fa SL	22	#else
bcec8f49	23	#ifdef XILINX_SPI_FLASH_BASEADDR
1fe7e8fa	24	#undef FLASH
bcec8f49 SL	25	#define SPIFLASH
	26	#undef RAMENV /* hold environment in flash */
	27	#else
	28	#undef FLASH
	29	#undef SPIFLASH
1fe7e8fa SL	30	#define RAMENV /* hold environment in RAM */
1fe7e8fa SL	31	#endif
bcec8f49	32	#endif
1fe7e8fa	33
76316a31	34	/* uart */
67659e2e MS	35	# define CONFIG_BAUDRATE 115200
	36	/* The following table includes the supported baudrates */
	37	# define CONFIG_SYS_BAUDRATE_TABLE \
	38	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
	39
76316a31	40	/* setting reset address */
14d0a02a	41	/#define CONFIG_SYS_RESET_ADDRESS CONFIG_SYS_TEXT_BASE/
76316a31	42
17980495	43	/* ethernet */
1252df06	44	#undef CONFIG_SYS_ENET
3229c869	45	#if defined(CONFIG_XILINX_EMACLITE)
4aecfb16	46	# define CONFIG_SYS_ENET
8422a35e	47	#endif
e634138e MS	48	#if defined(XILINX_AXIEMAC_BASEADDR)
	49	# define CONFIG_XILINX_AXIEMAC 1
	50	# define CONFIG_SYS_ENET
	51	#endif
330e5545	52
e5845e21	53	#undef ET_DEBUG
17980495	54
76316a31	55	/* gpio */
4c6a6f02	56	#ifdef XILINX_GPIO_BASEADDR
4e779ad2	57	# define CONFIG_XILINX_GPIO
4aecfb16	58	# define CONFIG_SYS_GPIO_0_ADDR XILINX_GPIO_BASEADDR
4c6a6f02	59	#endif
76316a31 MS	60
76316a31 MS	61	/* interrupt controller */
4d49b280	62	#ifdef XILINX_INTC_BASEADDR
4aecfb16 MS	63	# define CONFIG_SYS_INTC_0_ADDR XILINX_INTC_BASEADDR
4aecfb16 MS	64	# define CONFIG_SYS_INTC_0_NUM XILINX_INTC_NUM_INTR_INPUTS
4d49b280	65	#endif
76316a31 MS	66
76316a31 MS	67	/* timer */
bcbb046b	68	#if defined(XILINX_TIMER_BASEADDR) && defined(XILINX_TIMER_IRQ)
4aecfb16 MS	69	# define CONFIG_SYS_TIMER_0_ADDR XILINX_TIMER_BASEADDR
4aecfb16 MS	70	# define CONFIG_SYS_TIMER_0_IRQ XILINX_TIMER_IRQ
4d49b280	71	#endif
bcbb046b	72
0f21f98d MS	73	/* watchdog */
	74	#if defined(XILINX_WATCHDOG_BASEADDR) && defined(XILINX_WATCHDOG_IRQ)
	75	# define CONFIG_WATCHDOG_BASEADDR XILINX_WATCHDOG_BASEADDR
	76	# define CONFIG_WATCHDOG_IRQ XILINX_WATCHDOG_IRQ
b5e9b9a9 MS	77	# ifndef CONFIG_SPL_BUILD
	78	# define CONFIG_HW_WATCHDOG
	79	# define CONFIG_XILINX_TB_WATCHDOG
	80	# endif
0f21f98d MS	81	#endif
0f21f98d MS	82
0f925822 MY	83	#if !defined(CONFIG_OF_CONTROL) \|\| \
0f925822 MY	84	(defined(CONFIG_SPL_BUILD) && !defined(CONFIG_SPL_OF_CONTROL))
76316a31	85	/* ddr sdram - main memory */
e945f6dc MS	86	# define CONFIG_SYS_SDRAM_BASE XILINX_RAM_START
	87	# define CONFIG_SYS_SDRAM_SIZE XILINX_RAM_SIZE
	88	#endif
	89
	90	#define CONFIG_SYS_MALLOC_LEN 0xC0000
	91
	92	/* Stack location before relocation */
4fcd0b33 MS	93	#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_TEXT_BASE - \
4fcd0b33 MS	94	CONFIG_SYS_MALLOC_F_LEN)
76316a31	95
8f371b18 SL	96	/*
	97	* CFI flash memory layout - Example
	98	* CONFIG_SYS_FLASH_BASE = 0x2200_0000;
	99	* CONFIG_SYS_FLASH_SIZE = 0x0080_0000; 8MB
	100	*
	101	* SECT_SIZE = 0x20000; 128kB is one sector
	102	* CONFIG_ENV_SIZE = SECT_SIZE; 128kB environment store
	103	*
	104	* 0x2200_0000 CONFIG_SYS_FLASH_BASE
	105	* FREE 256kB
	106	* 0x2204_0000 CONFIG_ENV_ADDR
	107	* ENV_AREA 128kB
	108	* 0x2206_0000
	109	* FREE
	110	* 0x2280_0000 CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE
	111	*
	112	*/
	113
76316a31	114	#ifdef FLASH
4aecfb16 MS	115	# define CONFIG_SYS_FLASH_BASE XILINX_FLASH_START
	116	# define CONFIG_SYS_FLASH_SIZE XILINX_FLASH_SIZE
	117	# define CONFIG_SYS_FLASH_CFI 1
	118	# define CONFIG_FLASH_CFI_DRIVER 1
	119	/* ?empty sector */
	120	# define CONFIG_SYS_FLASH_EMPTY_INFO 1
	121	/* max number of memory banks */
	122	# define CONFIG_SYS_MAX_FLASH_BANKS 1
	123	/* max number of sectors on one chip */
	124	# define CONFIG_SYS_MAX_FLASH_SECT 512
	125	/* hardware flash protection */
	126	# define CONFIG_SYS_FLASH_PROTECTION
22ff7f4d MS	127	/* use buffered writes (20x faster) */
22ff7f4d MS	128	# define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
4aecfb16 MS	129	# ifdef RAMENV
	130	# define CONFIG_ENV_IS_NOWHERE 1
	131	# define CONFIG_ENV_SIZE 0x1000
	132	# define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SIZE)
	133
bcec8f49	134	# else /* FLASH && !RAMENV */
4aecfb16 MS	135	# define CONFIG_ENV_IS_IN_FLASH 1
	136	/* 128K(one sector) for env */
	137	# define CONFIG_ENV_SECT_SIZE 0x20000
	138	# define CONFIG_ENV_ADDR \
	139	(CONFIG_SYS_FLASH_BASE + (2 * CONFIG_ENV_SECT_SIZE))
	140	# define CONFIG_ENV_SIZE 0x20000
bcec8f49	141	# endif /* FLASH && !RAMBOOT */
76316a31	142	#else /* !FLASH */
bcec8f49 SL	143
	144	#ifdef SPIFLASH
	145	# define CONFIG_SYS_NO_FLASH 1
	146	# define CONFIG_SYS_SPI_BASE XILINX_SPI_FLASH_BASEADDR
bcec8f49	147	# define CONFIG_SPI 1
bcec8f49 SL	148	# define CONFIG_SF_DEFAULT_MODE SPI_MODE_3
	149	# define CONFIG_SF_DEFAULT_SPEED XILINX_SPI_FLASH_MAX_FREQ
	150	# define CONFIG_SF_DEFAULT_CS XILINX_SPI_FLASH_CS
	151
	152	# ifdef RAMENV
	153	# define CONFIG_ENV_IS_NOWHERE 1
	154	# define CONFIG_ENV_SIZE 0x1000
	155	# define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SIZE)
	156
	157	# else /* SPIFLASH && !RAMENV */
	158	# define CONFIG_ENV_IS_IN_SPI_FLASH 1
	159	# define CONFIG_ENV_SPI_MODE SPI_MODE_3
	160	# define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
	161	# define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS
	162	/* 128K(two sectors) for env */
	163	# define CONFIG_ENV_SECT_SIZE 0x10000
	164	# define CONFIG_ENV_SIZE (2 * CONFIG_ENV_SECT_SIZE)
	165	/* Warning: adjust the offset in respect of other flash content and size */
	166	# define CONFIG_ENV_OFFSET (128 * CONFIG_ENV_SECT_SIZE) /* at 8MB */
	167	# endif /* SPIFLASH && !RAMBOOT */
	168	#else /* !SPIFLASH */
	169
4aecfb16 MS	170	/* ENV in RAM */
	171	# define CONFIG_SYS_NO_FLASH 1
	172	# define CONFIG_ENV_IS_NOWHERE 1
	173	# define CONFIG_ENV_SIZE 0x1000
	174	# define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SIZE)
bcec8f49	175	#endif /* !SPIFLASH */
76316a31 MS	176	#endif /* !FLASH */
76316a31 MS	177
853643d8 MS	178	/* system ace */
853643d8 MS	179	#ifdef XILINX_SYSACE_BASEADDR
4aecfb16 MS	180	# define CONFIG_SYSTEMACE
	181	/* #define DEBUG_SYSTEMACE */
	182	# define SYSTEMACE_CONFIG_FPGA
	183	# define CONFIG_SYS_SYSTEMACE_BASE XILINX_SYSACE_BASEADDR
	184	# define CONFIG_SYS_SYSTEMACE_WIDTH XILINX_SYSACE_MEM_WIDTH
	185	# define CONFIG_DOS_PARTITION
853643d8 MS	186	#endif
853643d8 MS	187
e9b737de	188	#if defined(XILINX_USE_ICACHE)
4aecfb16	189	# define CONFIG_ICACHE
e9b737de	190	#else
4aecfb16	191	# undef CONFIG_ICACHE
e9b737de MS	192	#endif
	193
	194	#if defined(XILINX_USE_DCACHE)
4aecfb16	195	# define CONFIG_DCACHE
e9b737de	196	#else
4aecfb16	197	# undef CONFIG_DCACHE
e9b737de MS	198	#endif
e9b737de MS	199
5811830f MS	200	#ifndef XILINX_DCACHE_BYTE_SIZE
	201	#define XILINX_DCACHE_BYTE_SIZE 32768
	202	#endif
	203
079a136c JL	204	/*
	205	* BOOTP options
	206	*/
	207	#define CONFIG_BOOTP_BOOTFILESIZE
	208	#define CONFIG_BOOTP_BOOTPATH
	209	#define CONFIG_BOOTP_GATEWAY
	210	#define CONFIG_BOOTP_HOSTNAME
76316a31	211
5dc11a51 JL	212	/*
	213	* Command line configuration.
	214	*/
5dc11a51	215	#define CONFIG_CMD_ASKENV
5dc11a51	216	#define CONFIG_CMD_IRQ
5dc11a51	217	#define CONFIG_CMD_MFSL
4d49b280	218
e9b737de	219	#if defined(CONFIG_DCACHE) \|\| defined(CONFIG_ICACHE)
4aecfb16	220	# define CONFIG_CMD_CACHE
e9b737de	221	#else
4aecfb16	222	# undef CONFIG_CMD_CACHE
e9b737de MS	223	#endif
e9b737de MS	224
ef0f2f57	225	#ifdef CONFIG_SYS_ENET
4aecfb16 MS	226	# define CONFIG_CMD_PING
4aecfb16 MS	227	# define CONFIG_CMD_DHCP
4eb29cf0	228	# define CONFIG_CMD_TFTPPUT
4d49b280	229	#endif
853643d8 MS	230
853643d8 MS	231	#if defined(CONFIG_SYSTEMACE)
4aecfb16 MS	232	# define CONFIG_CMD_EXT2
4aecfb16 MS	233	# define CONFIG_CMD_FAT
853643d8	234	#endif
5dc11a51 JL	235
5dc11a51 JL	236	#if defined(FLASH)
4aecfb16	237	# define CONFIG_CMD_JFFS2
7cfb13a7 SL	238	# define CONFIG_CMD_UBI
7cfb13a7 SL	239	# undef CONFIG_CMD_UBIFS
4aecfb16	240
bcec8f49	241	# if !defined(RAMENV)
bcec8f49 SL	242	# define CONFIG_CMD_SAVES
	243	# endif
	244
	245	#else
	246	#if defined(SPIFLASH)
	247	# define CONFIG_CMD_SF
	248
4aecfb16	249	# if !defined(RAMENV)
4aecfb16 MS	250	# define CONFIG_CMD_SAVES
4aecfb16 MS	251	# endif
853643d8	252	#else
4aecfb16	253	# undef CONFIG_CMD_JFFS2
2cce2d32 SL	254	# undef CONFIG_CMD_UBI
2cce2d32 SL	255	# undef CONFIG_CMD_UBIFS
5dc11a51	256	#endif
bcec8f49	257	#endif
76316a31	258
5dc11a51	259	#if defined(CONFIG_CMD_JFFS2)
7cfb13a7 SL	260	# define CONFIG_MTD_PARTITIONS
	261	#endif
	262
	263	#if defined(CONFIG_CMD_UBIFS)
	264	# define CONFIG_CMD_UBI
	265	# define CONFIG_LZO
	266	#endif
	267
	268	#if defined(CONFIG_CMD_UBI)
	269	# define CONFIG_MTD_PARTITIONS
	270	# define CONFIG_RBTREE
	271	#endif
	272
	273	#if defined(CONFIG_MTD_PARTITIONS)
	274	/* MTD partitions */
68d7d651	275	#define CONFIG_CMD_MTDPARTS /* mtdparts command line support */
942556a9 SR	276	#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
942556a9 SR	277	#define CONFIG_FLASH_CFI_MTD
c82a541d	278	#define MTDIDS_DEFAULT "nor0=flash-0"
144876a3 MS	279
144876a3 MS	280	/* default mtd partition table */
c82a541d	281	#define MTDPARTS_DEFAULT "mtdparts=flash-0:256k(u-boot),"\
144876a3 MS	282	"256k(env),3m(kernel),1m(romfs),"\
	283	"1m(cramfs),-(jffs2)"
	284	#endif
	285
4aecfb16 MS	286	/* size of console buffer */
	287	#define CONFIG_SYS_CBSIZE 512
	288	/* print buffer size */
	289	#define CONFIG_SYS_PBSIZE \
	290	(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
	291	/* max number of command args */
	292	#define CONFIG_SYS_MAXARGS 15
6d0f6bcf	293	#define CONFIG_SYS_LONGHELP
4aecfb16 MS	294	/* default load address */
4aecfb16 MS	295	#define CONFIG_SYS_LOAD_ADDR XILINX_RAM_START
76316a31	296
330e5545	297	#define CONFIG_BOOTDELAY -1 /* -1 disables auto-boot */
76316a31	298	#define CONFIG_BOOTARGS "root=romfs"
330e5545	299	#define CONFIG_HOSTNAME XILINX_BOARD_NAME
853643d8	300	#define CONFIG_BOOTCOMMAND "base 0;tftp 11000000 image.img;bootm"
76316a31	301	#define CONFIG_IPADDR 192.168.0.3
853643d8 MS	302	#define CONFIG_SERVERIP 192.168.0.5
853643d8 MS	303	#define CONFIG_GATEWAYIP 192.168.0.1
76316a31 MS	304
76316a31 MS	305	/* architecture dependent code */
6d0f6bcf	306	#define CONFIG_SYS_USR_EXCEP /* user exception */
76316a31	307
0900bee9	308	#define CONFIG_PREBOOT "echo U-BOOT for ${hostname};setenv preboot;echo"
144876a3	309
4aecfb16	310	#define CONFIG_EXTRA_ENV_SETTINGS "unlock=yes\0" \
c82a541d SL	311	"nor0=flash-0\0"\
c82a541d SL	312	"mtdparts=mtdparts=flash-0:"\
144876a3	313	"256k(u-boot),256k(env),3m(kernel),"\
78376452 MS	314	"1m(romfs),1m(cramfs),-(jffs2)\0"\
	315	"nc=setenv stdout nc;"\
	316	"setenv stdin nc\0" \
	317	"serial=setenv stdout serial;"\
	318	"setenv stdin serial\0"
144876a3	319
188dc16b	320	#define CONFIG_CMDLINE_EDITING
188dc16b	321
78376452 MS	322	#define CONFIG_NETCONSOLE
	323	#define CONFIG_SYS_CONSOLE_IS_IN_ENV
	324
0900bee9 MS	325	/* Use the HUSH parser */
0900bee9 MS	326	#define CONFIG_SYS_HUSH_PARSER
0900bee9	327
37e892d9 MS	328	/* Enable flat device tree support */
	329	#define CONFIG_LMB 1
	330	#define CONFIG_FIT 1
	331	#define CONFIG_OF_LIBFDT 1
	332
4632b1ea	333	#if defined(CONFIG_XILINX_AXIEMAC)
f5e5e1ff SL	334	# define CONFIG_MII 1
	335	# define CONFIG_CMD_MII 1
	336	# define CONFIG_PHY_GIGE 1
	337	# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 1
f5e5e1ff SL	338	# define CONFIG_PHY_ATHEROS 1
	339	# define CONFIG_PHY_BROADCOM 1
	340	# define CONFIG_PHY_DAVICOM 1
	341	# define CONFIG_PHY_LXT 1
	342	# define CONFIG_PHY_MARVELL 1
	343	# define CONFIG_PHY_MICREL 1
2014a3de	344	# define CONFIG_PHY_MICREL_KSZ9021
f5e5e1ff SL	345	# define CONFIG_PHY_NATSEMI 1
	346	# define CONFIG_PHY_REALTEK 1
	347	# define CONFIG_PHY_VITESSE 1
	348	#else
	349	# undef CONFIG_MII
	350	# undef CONFIG_CMD_MII
f5e5e1ff SL	351	#endif
f5e5e1ff SL	352
9d242745	353	/* SPL part */
9d242745 MS	354	#define CONFIG_CMD_SPL
	355	#define CONFIG_SPL_FRAMEWORK
	356	#define CONFIG_SPL_LIBCOMMON_SUPPORT
	357	#define CONFIG_SPL_LIBGENERIC_SUPPORT
	358	#define CONFIG_SPL_SERIAL_SUPPORT
	359	#define CONFIG_SPL_BOARD_INIT
	360
	361	#define CONFIG_SPL_LDSCRIPT "arch/microblaze/cpu/u-boot-spl.lds"
	362
	363	#define CONFIG_SPL_RAM_DEVICE
4dd09742 MS	364	#ifdef CONFIG_SYS_FLASH_BASE
	365	# define CONFIG_SPL_NOR_SUPPORT
	366	# define CONFIG_SYS_UBOOT_BASE CONFIG_SYS_FLASH_BASE
	367	#endif
9d242745 MS	368
	369	/* for booting directly linux */
	370	#define CONFIG_SPL_OS_BOOT
	371
	372	#define CONFIG_SYS_OS_BASE (CONFIG_SYS_FLASH_BASE + \
	373	0x60000)
	374	#define CONFIG_SYS_FDT_BASE (CONFIG_SYS_FLASH_BASE + \
	375	0x40000)
	376	#define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_TEXT_BASE + \
	377	0x1000000)
	378
	379	/* SP location before relocation, must use scratch RAM */
	380	/* BRAM start */
	381	#define CONFIG_SYS_INIT_RAM_ADDR 0x0
	382	/* BRAM size - will be generated */
ca7d2266	383	#define CONFIG_SYS_INIT_RAM_SIZE 0x100000
9d242745	384
ca7d2266 MS	385	# define CONFIG_SPL_STACK_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
	386	CONFIG_SYS_INIT_RAM_SIZE - \
	387	CONFIG_SYS_MALLOC_F_LEN)
9d242745 MS	388
	389	/* Just for sure that there is a space for stack */
	390	#define CONFIG_SPL_STACK_SIZE 0x100
	391
9d242745 MS	392	#define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE
	393
	394	#define CONFIG_SPL_MAX_FOOTPRINT (CONFIG_SYS_INIT_RAM_SIZE - \
	395	CONFIG_SYS_INIT_RAM_ADDR - \
ca7d2266	396	CONFIG_SYS_MALLOC_F_LEN - \
9d242745 MS	397	CONFIG_SPL_STACK_SIZE)
9d242745 MS	398
76316a31	399	#endif /* __CONFIG_H */