projects / people / ms / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 8993e54b | 1 | /* |
| 3b74e7ec | 2 | * (C) Copyright 2007-2009 DENX Software Engineering |
| 8993e54b RJ |
3 | * |
| 4 | * See file CREDITS for list of people who contributed to this | |
| 5 | * project. | |
| 6 | * | |
| 7 | * This program is free software; you can redistribute it and/or | |
| 8 | * modify it under the terms of the GNU General Public License as | |
| 9 | * published by the Free Software Foundation; either version 2 of | |
| 10 | * the License, or (at your option) any later version. | |
| 11 | * | |
| 12 | * This program is distributed in the hope that it will be useful, | |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 15 | * GNU General Public License for more details. | |
| 16 | * | |
| 17 | * You should have received a copy of the GNU General Public License | |
| 18 | * along with this program; if not, write to the Free Software | |
| 19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
| 20 | * MA 02111-1307 USA | |
| 21 | */ | |
| 22 | ||
| 23 | /* | |
| 72601d04 | 24 | * MPC5121ADS board configuration file |
| 8993e54b RJ |
25 | */ |
| 26 | ||
| 27 | #ifndef __CONFIG_H | |
| 28 | #define __CONFIG_H | |
| 29 | ||
| 72601d04 | 30 | #define CONFIG_MPC5121ADS 1 |
| 8993e54b | 31 | /* |
| 72601d04 | 32 | * Memory map for the MPC5121ADS board: |
| 8993e54b RJ |
33 | * |
| 34 | * 0x0000_0000 - 0x0FFF_FFFF DDR RAM (256 MB) | |
| 35 | * 0x3000_0000 - 0x3001_FFFF SRAM (128 KB) | |
| 36 | * 0x8000_0000 - 0x803F_FFFF IMMR (4 MB) | |
| 37 | * 0x8200_0000 - 0x8200_001F CPLD (32 B) | |
| 5f91db7f JR |
38 | * 0x8400_0000 - 0x82FF_FFFF PCI I/O space (16 MB) |
| 39 | * 0xA000_0000 - 0xAFFF_FFFF PCI memory space (256 MB) | |
| 40 | * 0xB000_0000 - 0xBFFF_FFFF PCI memory mapped I/O space (256 MB) | |
| 8993e54b RJ |
41 | * 0xFC00_0000 - 0xFFFF_FFFF NOR Boot FLASH (64 MB) |
| 42 | */ | |
| 43 | ||
| 44 | /* | |
| 45 | * High Level Configuration Options | |
| 46 | */ | |
| 47 | #define CONFIG_E300 1 /* E300 Family */ | |
| 48 | #define CONFIG_MPC512X 1 /* MPC512X family */ | |
| 0e1bad47 | 49 | #define CONFIG_FSL_DIU_FB 1 /* FSL DIU */ |
| 92c20fbd | 50 | #undef CONFIG_FSL_DIU_LOGO_BMP /* Don't include FSL DIU binary bmp */ |
| 0e1bad47 YS |
51 | |
| 52 | /* video */ | |
| 53 | #undef CONFIG_VIDEO | |
| 54 | ||
| 55 | #if defined(CONFIG_VIDEO) | |
| 56 | #define CONFIG_CFB_CONSOLE | |
| 57 | #define CONFIG_VGA_AS_SINGLE_DEVICE | |
| 58 | #endif | |
| 8993e54b | 59 | |
| 5f91db7f | 60 | /* CONFIG_PCI is defined at config time */ |
| 8993e54b | 61 | |
| 72601d04 | 62 | #ifdef CONFIG_MPC5121ADS_REV2 |
| 6d0f6bcf | 63 | #define CONFIG_SYS_MPC512X_CLKIN 66000000 /* in Hz */ |
| f31c49db | 64 | #else |
| 6d0f6bcf | 65 | #define CONFIG_SYS_MPC512X_CLKIN 33333333 /* in Hz */ |
| f31c49db MM |
66 | #define CONFIG_PCI |
| 67 | #endif | |
| 8993e54b RJ |
68 | |
| 69 | #define CONFIG_BOARD_EARLY_INIT_F /* call board_early_init_f() */ | |
| 0e1bad47 | 70 | #define CONFIG_MISC_INIT_R |
| 8993e54b | 71 | |
| 6d0f6bcf JCPV |
72 | #define CONFIG_SYS_IMMR 0x80000000 |
| 73 | #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_IMMR+0x2100) | |
| 8993e54b | 74 | |
| 6d0f6bcf JCPV |
75 | #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */ |
| 76 | #define CONFIG_SYS_MEMTEST_END 0x00400000 | |
| 8993e54b RJ |
77 | |
| 78 | /* | |
| 79 | * DDR Setup - manually set all parameters as there's no SPD etc. | |
| 80 | */ | |
| 72601d04 | 81 | #ifdef CONFIG_MPC5121ADS_REV2 |
| 6d0f6bcf | 82 | #define CONFIG_SYS_DDR_SIZE 256 /* MB */ |
| f31c49db | 83 | #else |
| 6d0f6bcf | 84 | #define CONFIG_SYS_DDR_SIZE 512 /* MB */ |
| f31c49db | 85 | #endif |
| 6d0f6bcf JCPV |
86 | #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/ |
| 87 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE | |
| 8993e54b RJ |
88 | |
| 89 | /* DDR Controller Configuration | |
| b1b54e35 WD |
90 | * |
| 91 | * SYS_CFG: | |
| 92 | * [31:31] MDDRC Soft Reset: Diabled | |
| 93 | * [30:30] DRAM CKE pin: Enabled | |
| 94 | * [29:29] DRAM CLK: Enabled | |
| 95 | * [28:28] Command Mode: Enabled (For initialization only) | |
| 96 | * [27:25] DRAM Row Select: dram_row[15:0] = magenta_address[25:10] | |
| 97 | * [24:21] DRAM Bank Select: dram_bank[1:0] = magenta_address[11:10] | |
| 98 | * [20:19] Read Test: DON'T USE | |
| 99 | * [18:18] Self Refresh: Enabled | |
| 100 | * [17:17] 16bit Mode: Disabled | |
| 101 | * [16:13] Ready Delay: 2 | |
| 102 | * [12:12] Half DQS Delay: Disabled | |
| 103 | * [11:11] Quarter DQS Delay: Disabled | |
| 104 | * [10:08] Write Delay: 2 | |
| 105 | * [07:07] Early ODT: Disabled | |
| 106 | * [06:06] On DIE Termination: Disabled | |
| 107 | * [05:05] FIFO Overflow Clear: DON'T USE here | |
| 108 | * [04:04] FIFO Underflow Clear: DON'T USE here | |
| 109 | * [03:03] FIFO Overflow Pending: DON'T USE here | |
| 110 | * [02:02] FIFO Underlfow Pending: DON'T USE here | |
| 111 | * [01:01] FIFO Overlfow Enabled: Enabled | |
| 112 | * [00:00] FIFO Underflow Enabled: Enabled | |
| 113 | * TIME_CFG0 | |
| 114 | * [31:16] DRAM Refresh Time: 0 CSB clocks | |
| 115 | * [15:8] DRAM Command Time: 0 CSB clocks | |
| 116 | * [07:00] DRAM Precharge Time: 0 CSB clocks | |
| 117 | * TIME_CFG1 | |
| 118 | * [31:26] DRAM tRFC: | |
| 119 | * [25:21] DRAM tWR1: | |
| 120 | * [20:17] DRAM tWRT1: | |
| 121 | * [16:11] DRAM tDRR: | |
| 122 | * [10:05] DRAM tRC: | |
| 123 | * [04:00] DRAM tRAS: | |
| 124 | * TIME_CFG2 | |
| 125 | * [31:28] DRAM tRCD: | |
| 126 | * [27:23] DRAM tFAW: | |
| 127 | * [22:19] DRAM tRTW1: | |
| 128 | * [18:15] DRAM tCCD: | |
| 129 | * [14:10] DRAM tRTP: | |
| 130 | * [09:05] DRAM tRP: | |
| 131 | * [04:00] DRAM tRPA | |
| 132 | */ | |
| 72601d04 | 133 | #ifdef CONFIG_MPC5121ADS_REV2 |
| 054197ba | 134 | #define CONFIG_SYS_MDDRC_SYS_CFG 0xE8604A00 |
| 6d0f6bcf JCPV |
135 | #define CONFIG_SYS_MDDRC_TIME_CFG1 0x54EC1168 |
| 136 | #define CONFIG_SYS_MDDRC_TIME_CFG2 0x35210864 | |
| f31c49db | 137 | #else |
| 054197ba MS |
138 | #define CONFIG_SYS_MDDRC_SYS_CFG 0xEA804A00 |
| 139 | #define CONFIG_SYS_MDDRC_TIME_CFG1 0x68EC1168 | |
| 140 | #define CONFIG_SYS_MDDRC_TIME_CFG2 0x34310864 | |
| f31c49db | 141 | #endif |
| 054197ba | 142 | #define CONFIG_SYS_MDDRC_TIME_CFG0 0x06183D2E |
| 6d0f6bcf | 143 | |
| a5aa3998 MS |
144 | #define CONFIG_SYS_MDDRC_SYS_CFG_ELPIDA 0xEA802B00 |
| 145 | #define CONFIG_SYS_MDDRC_TIME_CFG1_ELPIDA 0x690e1189 | |
| 146 | #define CONFIG_SYS_MDDRC_TIME_CFG2_ELPIDA 0x35310864 | |
| 147 | ||
| 054197ba MS |
148 | #define CONFIG_SYS_DDRCMD_NOP 0x01380000 |
| 149 | #define CONFIG_SYS_DDRCMD_PCHG_ALL 0x01100400 | |
| 150 | #define CONFIG_SYS_DDRCMD_EM2 0x01020000 | |
| 151 | #define CONFIG_SYS_DDRCMD_EM3 0x01030000 | |
| 152 | #define CONFIG_SYS_DDRCMD_EN_DLL 0x01010000 | |
| 153 | #define CONFIG_SYS_DDRCMD_RFSH 0x01080000 | |
| a5aa3998 MS |
154 | |
| 155 | #define DDRCMD_EMR_OCD(pr, ohm) ( \ | |
| 156 | (1 << 24) | /* MDDRC Command Request */ \ | |
| 157 | (1 << 16) | /* MODE Reg BA[2:0] */ \ | |
| 158 | (0 << 12) | /* Outputs 0=Enabled */ \ | |
| 159 | (0 << 11) | /* RDQS */ \ | |
| 160 | (1 << 10) | /* DQS# */ \ | |
| 161 | (pr << 7) | /* OCD prog 7=deflt,0=exit */ \ | |
| 162 | /* ODT Rtt[1:0] 0=0,1=75,2=150,3=50 */ \ | |
| 163 | ((ohm & 0x2) << 5)| /* Rtt1 */ \ | |
| 164 | (0 << 3) | /* additive posted CAS# */ \ | |
| 165 | ((ohm & 0x1) << 2)| /* Rtt0 */ \ | |
| 166 | (0 << 0) | /* Output Drive Strength */ \ | |
| 167 | (0 << 0)) /* DLL Enable 0=Normal */ | |
| 168 | ||
| 169 | #define CONFIG_SYS_DDRCMD_OCD_DEFAULT DDRCMD_EMR_OCD(7, 0) | |
| 170 | #define CONFIG_SYS_ELPIDA_OCD_EXIT DDRCMD_EMR_OCD(0, 0) | |
| 171 | ||
| 172 | #define DDRCMD_MODE_REG(cas, wr) ( \ | |
| 173 | (1 << 24) | /* MDDRC Command Request */ \ | |
| 174 | (0 << 16) | /* MODE Reg BA[2:0] */ \ | |
| 175 | ((wr-1) << 9)| /* Write Recovery */ \ | |
| 176 | (cas << 4) | /* CAS */ \ | |
| 177 | (0 << 3) | /* Burst Type:0=Sequential,1=Interleaved */ \ | |
| 178 | (2 << 0)) /* 4 or 8 Burst Length:0x2=4 0x3=8 */ | |
| 179 | ||
| 180 | #define CONFIG_SYS_MICRON_INIT_DEV_OP DDRCMD_MODE_REG(3, 3) | |
| 181 | #define CONFIG_SYS_ELPIDA_INIT_DEV_OP DDRCMD_MODE_REG(4, 4) | |
| 182 | #define CONFIG_SYS_ELPIDA_RES_DLL (DDRCMD_MODE_REG(4, 4) | (1 << 8)) | |
| 8993e54b RJ |
183 | |
| 184 | /* DDR Priority Manager Configuration */ | |
| 6d0f6bcf JCPV |
185 | #define CONFIG_SYS_MDDRCGRP_PM_CFG1 0x00077777 |
| 186 | #define CONFIG_SYS_MDDRCGRP_PM_CFG2 0x00000000 | |
| 187 | #define CONFIG_SYS_MDDRCGRP_HIPRIO_CFG 0x00000001 | |
| 188 | #define CONFIG_SYS_MDDRCGRP_LUT0_MU 0xFFEEDDCC | |
| 189 | #define CONFIG_SYS_MDDRCGRP_LUT0_ML 0xBBAAAAAA | |
| 190 | #define CONFIG_SYS_MDDRCGRP_LUT1_MU 0x66666666 | |
| 191 | #define CONFIG_SYS_MDDRCGRP_LUT1_ML 0x55555555 | |
| 192 | #define CONFIG_SYS_MDDRCGRP_LUT2_MU 0x44444444 | |
| 193 | #define CONFIG_SYS_MDDRCGRP_LUT2_ML 0x44444444 | |
| 194 | #define CONFIG_SYS_MDDRCGRP_LUT3_MU 0x55555555 | |
| 195 | #define CONFIG_SYS_MDDRCGRP_LUT3_ML 0x55555558 | |
| 196 | #define CONFIG_SYS_MDDRCGRP_LUT4_MU 0x11111111 | |
| 197 | #define CONFIG_SYS_MDDRCGRP_LUT4_ML 0x11111122 | |
| 198 | #define CONFIG_SYS_MDDRCGRP_LUT0_AU 0xaaaaaaaa | |
| 199 | #define CONFIG_SYS_MDDRCGRP_LUT0_AL 0xaaaaaaaa | |
| 200 | #define CONFIG_SYS_MDDRCGRP_LUT1_AU 0x66666666 | |
| 201 | #define CONFIG_SYS_MDDRCGRP_LUT1_AL 0x66666666 | |
| 202 | #define CONFIG_SYS_MDDRCGRP_LUT2_AU 0x11111111 | |
| 203 | #define CONFIG_SYS_MDDRCGRP_LUT2_AL 0x11111111 | |
| 204 | #define CONFIG_SYS_MDDRCGRP_LUT3_AU 0x11111111 | |
| 205 | #define CONFIG_SYS_MDDRCGRP_LUT3_AL 0x11111111 | |
| 206 | #define CONFIG_SYS_MDDRCGRP_LUT4_AU 0x11111111 | |
| 207 | #define CONFIG_SYS_MDDRCGRP_LUT4_AL 0x11111111 | |
| 8993e54b RJ |
208 | |
| 209 | /* | |
| 210 | * NOR FLASH on the Local Bus | |
| 211 | */ | |
| f31c49db | 212 | #undef CONFIG_BKUP_FLASH |
| 6d0f6bcf | 213 | #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ |
| 00b1883a | 214 | #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ |
| f31c49db | 215 | #ifdef CONFIG_BKUP_FLASH |
| 6d0f6bcf JCPV |
216 | #define CONFIG_SYS_FLASH_BASE 0xFF800000 /* start of FLASH */ |
| 217 | #define CONFIG_SYS_FLASH_SIZE 0x00800000 /* max flash size in bytes */ | |
| f31c49db | 218 | #else |
| 6d0f6bcf JCPV |
219 | #define CONFIG_SYS_FLASH_BASE 0xFC000000 /* start of FLASH */ |
| 220 | #define CONFIG_SYS_FLASH_SIZE 0x04000000 /* max flash size in bytes */ | |
| f31c49db | 221 | #endif |
| 6d0f6bcf JCPV |
222 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE |
| 223 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ | |
| 224 | #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE} | |
| 225 | #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */ | |
| 8993e54b | 226 | |
| 6d0f6bcf | 227 | #undef CONFIG_SYS_FLASH_CHECKSUM |
| 8993e54b | 228 | |
| 229549a5 SR |
229 | /* |
| 230 | * NAND FLASH | |
| 13946925 | 231 | * drivers/mtd/nand/mpc5121_nfc.c (rev 2 silicon only) |
| 229549a5 | 232 | */ |
| 7d4450a9 WD |
233 | #define CONFIG_CMD_NAND /* enable NAND support */ |
| 234 | #define CONFIG_JFFS2_NAND /* with JFFS2 on it */ | |
| 229549a5 SR |
235 | #define CONFIG_NAND_MPC5121_NFC |
| 236 | #define CONFIG_SYS_NAND_BASE 0x40000000 | |
| 237 | ||
| 238 | #define CONFIG_SYS_MAX_NAND_DEVICE 2 | |
| 239 | #define NAND_MAX_CHIPS CONFIG_SYS_MAX_NAND_DEVICE | |
| 240 | #define CONFIG_SYS_NAND_SELECT_DEVICE /* driver supports mutipl. chips */ | |
| 241 | ||
| 242 | /* | |
| 243 | * Configuration parameters for MPC5121 NAND driver | |
| 244 | */ | |
| 245 | #define CONFIG_FSL_NFC_WIDTH 1 | |
| 246 | #define CONFIG_FSL_NFC_WRITE_SIZE 2048 | |
| 247 | #define CONFIG_FSL_NFC_SPARE_SIZE 64 | |
| 248 | #define CONFIG_FSL_NFC_CHIPS CONFIG_SYS_MAX_NAND_DEVICE | |
| 249 | ||
| 8993e54b RJ |
250 | /* |
| 251 | * CPLD registers area is really only 32 bytes in size, but the smallest possible LP | |
| 252 | * window is 64KB | |
| 253 | */ | |
| 6d0f6bcf JCPV |
254 | #define CONFIG_SYS_CPLD_BASE 0x82000000 |
| 255 | #define CONFIG_SYS_CPLD_SIZE 0x00010000 /* 64 KB */ | |
| 8993e54b | 256 | |
| 6d0f6bcf JCPV |
257 | #define CONFIG_SYS_SRAM_BASE 0x30000000 |
| 258 | #define CONFIG_SYS_SRAM_SIZE 0x00020000 /* 128 KB */ | |
| 8993e54b | 259 | |
| 6d0f6bcf JCPV |
260 | #define CONFIG_SYS_CS0_CFG 0x05059310 /* ALE active low, data size 4bytes */ |
| 261 | #define CONFIG_SYS_CS2_CFG 0x05059010 /* ALE active low, data size 1byte */ | |
| 262 | #define CONFIG_SYS_CS_ALETIMING 0x00000005 /* Use alternative CS timing for CS0 and CS2 */ | |
| 8993e54b RJ |
263 | |
| 264 | /* Use SRAM for initial stack */ | |
| 6d0f6bcf JCPV |
265 | #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_SRAM_BASE /* Initial RAM address */ |
| 266 | #define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_SRAM_SIZE /* End of used area in RAM */ | |
| 8993e54b | 267 | |
| 6d0f6bcf JCPV |
268 | #define CONFIG_SYS_GBL_DATA_SIZE 0x100 /* num bytes initial data */ |
| 269 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) | |
| 270 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET | |
| 8993e54b | 271 | |
| 6d0f6bcf | 272 | #define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* Start of monitor */ |
| 229549a5 | 273 | #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ |
| 0e1bad47 | 274 | #ifdef CONFIG_FSL_DIU_FB |
| 6d0f6bcf | 275 | #define CONFIG_SYS_MALLOC_LEN (6 * 1024 * 1024) /* Reserved for malloc */ |
| 0e1bad47 | 276 | #else |
| 6d0f6bcf | 277 | #define CONFIG_SYS_MALLOC_LEN (512 * 1024) |
| 0e1bad47 | 278 | #endif |
| 8993e54b RJ |
279 | |
| 280 | /* | |
| 281 | * Serial Port | |
| 282 | */ | |
| 283 | #define CONFIG_CONS_INDEX 1 | |
| 284 | #undef CONFIG_SERIAL_SOFTWARE_FIFO | |
| 285 | ||
| 286 | /* | |
| 287 | * Serial console configuration | |
| 288 | */ | |
| 289 | #define CONFIG_PSC_CONSOLE 3 /* console is on PSC3 */ | |
| 290 | #if CONFIG_PSC_CONSOLE != 3 | |
| 291 | #error CONFIG_PSC_CONSOLE must be 3 | |
| 292 | #endif | |
| 293 | #define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */ | |
| 6d0f6bcf | 294 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
| 8993e54b RJ |
295 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} |
| 296 | ||
| 297 | #define CONSOLE_FIFO_TX_SIZE FIFOC_PSC3_TX_SIZE | |
| 298 | #define CONSOLE_FIFO_TX_ADDR FIFOC_PSC3_TX_ADDR | |
| 299 | #define CONSOLE_FIFO_RX_SIZE FIFOC_PSC3_RX_SIZE | |
| 300 | #define CONSOLE_FIFO_RX_ADDR FIFOC_PSC3_RX_ADDR | |
| 301 | ||
| 302 | #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ | |
| 303 | /* Use the HUSH parser */ | |
| 6d0f6bcf JCPV |
304 | #define CONFIG_SYS_HUSH_PARSER |
| 305 | #ifdef CONFIG_SYS_HUSH_PARSER | |
| 306 | #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " | |
| 8993e54b RJ |
307 | #endif |
| 308 | ||
| 5f91db7f JR |
309 | /* |
| 310 | * PCI | |
| 311 | */ | |
| 312 | #ifdef CONFIG_PCI | |
| 313 | ||
| 314 | /* | |
| 315 | * General PCI | |
| 316 | */ | |
| 6d0f6bcf JCPV |
317 | #define CONFIG_SYS_PCI_MEM_BASE 0xA0000000 |
| 318 | #define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BASE | |
| 319 | #define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 /* 256M */ | |
| 320 | #define CONFIG_SYS_PCI_MMIO_BASE (CONFIG_SYS_PCI_MEM_BASE + CONFIG_SYS_PCI_MEM_SIZE) | |
| 321 | #define CONFIG_SYS_PCI_MMIO_PHYS CONFIG_SYS_PCI_MMIO_BASE | |
| 322 | #define CONFIG_SYS_PCI_MMIO_SIZE 0x10000000 /* 256M */ | |
| 323 | #define CONFIG_SYS_PCI_IO_BASE 0x00000000 | |
| 324 | #define CONFIG_SYS_PCI_IO_PHYS 0x84000000 | |
| 325 | #define CONFIG_SYS_PCI_IO_SIZE 0x01000000 /* 16M */ | |
| 5f91db7f JR |
326 | |
| 327 | ||
| 328 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ | |
| 329 | ||
| 330 | #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ | |
| 331 | ||
| 332 | #endif | |
| 333 | ||
| 8993e54b RJ |
334 | /* I2C */ |
| 335 | #define CONFIG_HARD_I2C /* I2C with hardware support */ | |
| 336 | #undef CONFIG_SOFT_I2C /* so disable bit-banged I2C */ | |
| 337 | #define CONFIG_I2C_MULTI_BUS | |
| 6d0f6bcf JCPV |
338 | #define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed and slave address */ |
| 339 | #define CONFIG_SYS_I2C_SLAVE 0x7F | |
| 8993e54b | 340 | #if 0 |
| 6d0f6bcf | 341 | #define CONFIG_SYS_I2C_NOPROBES {{0,0x69}} /* Don't probe these addrs */ |
| 8993e54b RJ |
342 | #endif |
| 343 | ||
| abfbd0ae MM |
344 | /* |
| 345 | * IIM - IC Identification Module | |
| 346 | */ | |
| 347 | #undef CONFIG_IIM | |
| 348 | ||
| 80020120 GB |
349 | /* |
| 350 | * EEPROM configuration | |
| 351 | */ | |
| 6d0f6bcf JCPV |
352 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* 16-bit EEPROM address */ |
| 353 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Atmel: AT24C32A-10TQ-2.7 */ | |
| 354 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* 10ms of delay */ | |
| 355 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* 32-Byte Page Write Mode */ | |
| 80020120 | 356 | |
| 8993e54b RJ |
357 | /* |
| 358 | * Ethernet configuration | |
| 359 | */ | |
| 360 | #define CONFIG_MPC512x_FEC 1 | |
| 361 | #define CONFIG_NET_MULTI | |
| 362 | #define CONFIG_PHY_ADDR 0x1 | |
| 363 | #define CONFIG_MII 1 /* MII PHY management */ | |
| f31c49db | 364 | #define CONFIG_FEC_AN_TIMEOUT 1 |
| ef11df6b | 365 | #define CONFIG_HAS_ETH0 |
| 8993e54b | 366 | |
| 8993e54b RJ |
367 | /* |
| 368 | * Configure on-board RTC | |
| 369 | */ | |
| f31c49db | 370 | #define CONFIG_RTC_M41T62 /* use M41T62 rtc via i2 */ |
| 6d0f6bcf | 371 | #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */ |
| 8993e54b RJ |
372 | |
| 373 | /* | |
| 374 | * Environment | |
| 375 | */ | |
| 5a1aceb0 | 376 | #define CONFIG_ENV_IS_IN_FLASH 1 |
| 8993e54b | 377 | /* This has to be a multiple of the Flash sector size */ |
| 6d0f6bcf | 378 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) |
| 0e8d1586 | 379 | #define CONFIG_ENV_SIZE 0x2000 |
| f31c49db | 380 | #ifdef CONFIG_BKUP_FLASH |
| 0e8d1586 | 381 | #define CONFIG_ENV_SECT_SIZE 0x20000 /* one sector (256K) for env */ |
| f31c49db | 382 | #else |
| 0e8d1586 | 383 | #define CONFIG_ENV_SECT_SIZE 0x40000 /* one sector (256K) for env */ |
| f31c49db | 384 | #endif |
| 8993e54b RJ |
385 | |
| 386 | /* Address and size of Redundant Environment Sector */ | |
| 0e8d1586 JCPV |
387 | #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) |
| 388 | #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) | |
| 8993e54b RJ |
389 | |
| 390 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
| 6d0f6bcf | 391 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
| 8993e54b | 392 | |
| e27f3a6e WD |
393 | #include <config_cmd_default.h> |
| 394 | ||
| 395 | #define CONFIG_CMD_ASKENV | |
| 7d4450a9 | 396 | #define CONFIG_CMD_DATE |
| e27f3a6e | 397 | #define CONFIG_CMD_DHCP |
| 7d4450a9 WD |
398 | #define CONFIG_CMD_EEPROM |
| 399 | #define CONFIG_CMD_EXT2 | |
| e27f3a6e | 400 | #define CONFIG_CMD_I2C |
| 7d4450a9 WD |
401 | #define CONFIG_CMD_IDE |
| 402 | #define CONFIG_CMD_JFFS2 | |
| e27f3a6e WD |
403 | #define CONFIG_CMD_MII |
| 404 | #define CONFIG_CMD_NFS | |
| 405 | #define CONFIG_CMD_PING | |
| 406 | #define CONFIG_CMD_REGINFO | |
| 7d4450a9 | 407 | |
| abfbd0ae | 408 | #undef CONFIG_CMD_FUSE |
| e27f3a6e | 409 | |
| 8993e54b | 410 | #if defined(CONFIG_PCI) |
| e27f3a6e | 411 | #define CONFIG_CMD_PCI |
| 8993e54b RJ |
412 | #endif |
| 413 | ||
| 7d4450a9 WD |
414 | /* |
| 415 | * Dynamic MTD partition support | |
| 416 | */ | |
| 417 | #define CONFIG_CMD_MTDPARTS | |
| 418 | #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ | |
| 419 | #define CONFIG_FLASH_CFI_MTD | |
| 420 | #define MTDIDS_DEFAULT "nor0=fc000000.flash,nand0=mpc5121.nand" | |
| 421 | ||
| 422 | /* | |
| 423 | * NOR flash layout: | |
| 424 | * | |
| 425 | * FC000000 - FEABFFFF 42.75 MiB User Data | |
| 426 | * FEAC0000 - FFABFFFF 16 MiB Root File System | |
| 427 | * FFAC0000 - FFEBFFFF 4 MiB Linux Kernel | |
| 428 | * FFEC0000 - FFEFFFFF 256 KiB Device Tree | |
| 429 | * FFF00000 - FFFFFFFF 1 MiB U-Boot (up to 512 KiB) and 2 x * env | |
| 430 | * | |
| 431 | * NAND flash layout: one big partition | |
| 432 | */ | |
| 433 | #define MTDPARTS_DEFAULT "mtdparts=fc000000.flash:43776k(user)," \ | |
| 434 | "16m(rootfs)," \ | |
| 435 | "4m(kernel)," \ | |
| 436 | "256k(dtb)," \ | |
| 437 | "1m(u-boot);" \ | |
| 438 | "mpc5121.nand:-(data)" | |
| 439 | ||
| 440 | ||
| 441 | #if defined(CONFIG_CMD_IDE) || defined(CONFIG_CMD_EXT2) | |
| 70a4da45 RK |
442 | #define CONFIG_DOS_PARTITION |
| 443 | #define CONFIG_MAC_PARTITION | |
| 444 | #define CONFIG_ISO_PARTITION | |
| 445 | #endif /* defined(CONFIG_CMD_IDE) */ | |
| 446 | ||
| 8993e54b | 447 | /* |
| 6d0f6bcf JCPV |
448 | * Watchdog timeout = CONFIG_SYS_WATCHDOG_VALUE * 65536 / IPS clock. |
| 449 | * For example, when IPS is set to 66MHz and CONFIG_SYS_WATCHDOG_VALUE is set | |
| 8993e54b RJ |
450 | * to 0xFFFF, watchdog timeouts after about 64s. For details refer |
| 451 | * to chapter 36 of the MPC5121e Reference Manual. | |
| 452 | */ | |
| 66ffb188 | 453 | /* #define CONFIG_WATCHDOG */ /* enable watchdog */ |
| 6d0f6bcf | 454 | #define CONFIG_SYS_WATCHDOG_VALUE 0xFFFF |
| 8993e54b RJ |
455 | |
| 456 | /* | |
| 457 | * Miscellaneous configurable options | |
| 458 | */ | |
| 6d0f6bcf JCPV |
459 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
| 460 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ | |
| 461 | #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ | |
| 8993e54b | 462 | |
| e27f3a6e | 463 | #ifdef CONFIG_CMD_KGDB |
| 6d0f6bcf | 464 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
| 8993e54b | 465 | #else |
| 6d0f6bcf | 466 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
| 8993e54b RJ |
467 | #endif |
| 468 | ||
| 469 | ||
| 6d0f6bcf JCPV |
470 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buffer Size */ |
| 471 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
| 472 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
| 473 | #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ | |
| 8993e54b RJ |
474 | |
| 475 | /* | |
| 476 | * For booting Linux, the board info and command line data | |
| 477 | * have to be in the first 8 MB of memory, since this is | |
| 478 | * the maximum mapped by the Linux kernel during initialization. | |
| 479 | */ | |
| 6d0f6bcf | 480 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ |
| 8993e54b RJ |
481 | |
| 482 | /* Cache Configuration */ | |
| 6d0f6bcf JCPV |
483 | #define CONFIG_SYS_DCACHE_SIZE 32768 |
| 484 | #define CONFIG_SYS_CACHELINE_SIZE 32 | |
| e27f3a6e | 485 | #ifdef CONFIG_CMD_KGDB |
| 6d0f6bcf | 486 | #define CONFIG_SYS_CACHELINE_SHIFT 5 /*log base 2 of the above value*/ |
| 8993e54b RJ |
487 | #endif |
| 488 | ||
| 6d0f6bcf | 489 | #define CONFIG_SYS_HID0_INIT 0x000000000 |
| e2b66fe4 | 490 | #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | HID0_ICE) |
| 6d0f6bcf | 491 | #define CONFIG_SYS_HID2 HID2_HBE |
| 8993e54b | 492 | |
| 31d82672 BB |
493 | #define CONFIG_HIGH_BATS 1 /* High BATs supported */ |
| 494 | ||
| 8993e54b RJ |
495 | /* |
| 496 | * Internal Definitions | |
| 497 | * | |
| 498 | * Boot Flags | |
| 499 | */ | |
| 66ffb188 WD |
500 | #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ |
| 501 | #define BOOTFLAG_WARM 0x02 /* Software reboot */ | |
| 8993e54b | 502 | |
| e27f3a6e | 503 | #ifdef CONFIG_CMD_KGDB |
| 8993e54b RJ |
504 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ |
| 505 | #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ | |
| 506 | #endif | |
| 507 | ||
| 508 | /* | |
| 509 | * Environment Configuration | |
| 510 | */ | |
| 66ffb188 | 511 | #define CONFIG_TIMESTAMP |
| 8993e54b | 512 | |
| 72601d04 WD |
513 | #define CONFIG_HOSTNAME mpc5121ads |
| 514 | #define CONFIG_BOOTFILE mpc5121ads/uImage | |
| dd820b03 | 515 | #define CONFIG_ROOTPATH /opt/eldk/ppc_6xx |
| 8993e54b | 516 | |
| 8d103071 | 517 | #define CONFIG_LOADADDR 400000 /* default location for tftp and bootm */ |
| 8993e54b | 518 | |
| e27f3a6e | 519 | #define CONFIG_BOOTDELAY 5 /* -1 disables auto-boot */ |
| 8993e54b RJ |
520 | #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ |
| 521 | ||
| 522 | #define CONFIG_BAUDRATE 115200 | |
| 523 | ||
| 524 | #define CONFIG_PREBOOT "echo;" \ | |
| 5b0b2b6f | 525 | "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ |
| 8993e54b RJ |
526 | "echo" |
| 527 | ||
| 528 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
| 8d103071 | 529 | "u-boot_addr_r=200000\0" \ |
| 51e46e28 WD |
530 | "kernel_addr_r=600000\0" \ |
| 531 | "fdt_addr_r=880000\0" \ | |
| 532 | "ramdisk_addr_r=900000\0" \ | |
| 8d103071 | 533 | "u-boot_addr=FFF00000\0" \ |
| 7d4450a9 | 534 | "kernel_addr=FFAC0000\0" \ |
| 51e46e28 | 535 | "fdt_addr=FFEC0000\0" \ |
| 7d4450a9 | 536 | "ramdisk_addr=FEAC0000\0" \ |
| 72601d04 WD |
537 | "ramdiskfile=mpc5121ads/uRamdisk\0" \ |
| 538 | "u-boot=mpc5121ads/u-boot.bin\0" \ | |
| 539 | "bootfile=mpc5121ads/uImage\0" \ | |
| 540 | "fdtfile=mpc5121ads/mpc5121ads.dtb\0" \ | |
| 51e46e28 | 541 | "rootpath=/opt/eldk/ppc_6xx\n" \ |
| 8993e54b | 542 | "netdev=eth0\0" \ |
| 8d103071 | 543 | "consdev=ttyPSC0\0" \ |
| 8993e54b RJ |
544 | "nfsargs=setenv bootargs root=/dev/nfs rw " \ |
| 545 | "nfsroot=${serverip}:${rootpath}\0" \ | |
| 546 | "ramargs=setenv bootargs root=/dev/ram rw\0" \ | |
| 547 | "addip=setenv bootargs ${bootargs} " \ | |
| 548 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ | |
| 549 | ":${hostname}:${netdev}:off panic=1\0" \ | |
| 8d103071 WD |
550 | "addtty=setenv bootargs ${bootargs} " \ |
| 551 | "console=${consdev},${baudrate}\0" \ | |
| 8993e54b | 552 | "flash_nfs=run nfsargs addip addtty;" \ |
| a99715b8 | 553 | "bootm ${kernel_addr} - ${fdt_addr}\0" \ |
| 8993e54b | 554 | "flash_self=run ramargs addip addtty;" \ |
| 8d103071 WD |
555 | "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \ |
| 556 | "net_nfs=tftp ${kernel_addr_r} ${bootfile};" \ | |
| 557 | "tftp ${fdt_addr_r} ${fdtfile};" \ | |
| 558 | "run nfsargs addip addtty;" \ | |
| 559 | "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \ | |
| 560 | "net_self=tftp ${kernel_addr_r} ${bootfile};" \ | |
| 561 | "tftp ${ramdisk_addr_r} ${ramdiskfile};" \ | |
| a99715b8 | 562 | "tftp ${fdt_addr_r} ${fdtfile};" \ |
| 8d103071 | 563 | "run ramargs addip addtty;" \ |
| 5b0b2b6f | 564 | "bootm ${kernel_addr_r} ${ramdisk_addr_r} ${fdt_addr_r}\0"\ |
| a99715b8 | 565 | "load=tftp ${u-boot_addr_r} ${u-boot}\0" \ |
| 8d103071 WD |
566 | "update=protect off ${u-boot_addr} +${filesize};" \ |
| 567 | "era ${u-boot_addr} +${filesize};" \ | |
| 568 | "cp.b ${u-boot_addr_r} ${u-boot_addr} ${filesize}\0" \ | |
| 569 | "upd=run load update\0" \ | |
| 8993e54b RJ |
570 | "" |
| 571 | ||
| 8993e54b RJ |
572 | #define CONFIG_BOOTCOMMAND "run flash_self" |
| 573 | ||
| 281ff9a4 GB |
574 | #define CONFIG_OF_LIBFDT 1 |
| 575 | #define CONFIG_OF_BOARD_SETUP 1 | |
| ef11df6b | 576 | #define CONFIG_OF_SUPPORT_OLD_DEVICE_TREES 1 |
| 281ff9a4 GB |
577 | |
| 578 | #define OF_CPU "PowerPC,5121@0" | |
| ef11df6b | 579 | #define OF_SOC_COMPAT "fsl,mpc5121-immr" |
| 281ff9a4 | 580 | #define OF_TBCLK (bd->bi_busfreq / 4) |
| ac915283 | 581 | #define OF_STDOUT_PATH "/soc@80000000/serial@11300" |
| 281ff9a4 | 582 | |
| 70a4da45 RK |
583 | /*----------------------------------------------------------------------- |
| 584 | * IDE/ATA stuff | |
| 585 | *----------------------------------------------------------------------- | |
| 586 | */ | |
| 587 | ||
| 588 | #undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */ | |
| 589 | #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ | |
| 590 | #undef CONFIG_IDE_LED /* LED for IDE not supported */ | |
| 591 | ||
| 592 | #define CONFIG_IDE_RESET /* reset for IDE supported */ | |
| 593 | #define CONFIG_IDE_PREINIT | |
| 594 | ||
| 595 | #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ | |
| 596 | #define CONFIG_SYS_IDE_MAXDEVICE 2 /* max. 1 drive per IDE bus */ | |
| 597 | ||
| 598 | #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 | |
| 3b74e7ec | 599 | #define CONFIG_SYS_ATA_BASE_ADDR get_pata_base() |
| 70a4da45 RK |
600 | |
| 601 | /* Offset for data I/O RefMan MPC5121EE Table 28-10 */ | |
| 602 | #define CONFIG_SYS_ATA_DATA_OFFSET (0x00A0) | |
| 603 | ||
| 604 | /* Offset for normal register accesses */ | |
| 605 | #define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET) | |
| 606 | ||
| 607 | /* Offset for alternate registers RefMan MPC5121EE Table 28-23 */ | |
| 608 | #define CONFIG_SYS_ATA_ALT_OFFSET (0x00D8) | |
| 609 | ||
| 610 | /* Interval between registers */ | |
| 611 | #define CONFIG_SYS_ATA_STRIDE 4 | |
| 612 | ||
| 3b74e7ec | 613 | #define ATA_BASE_ADDR get_pata_base() |
| 70a4da45 RK |
614 | |
| 615 | /* | |
| 616 | * Control register bit definitions | |
| 617 | */ | |
| 618 | #define FSL_ATA_CTRL_FIFO_RST_B 0x80000000 | |
| 619 | #define FSL_ATA_CTRL_ATA_RST_B 0x40000000 | |
| 620 | #define FSL_ATA_CTRL_FIFO_TX_EN 0x20000000 | |
| 621 | #define FSL_ATA_CTRL_FIFO_RCV_EN 0x10000000 | |
| 622 | #define FSL_ATA_CTRL_DMA_PENDING 0x08000000 | |
| 623 | #define FSL_ATA_CTRL_DMA_ULTRA 0x04000000 | |
| 624 | #define FSL_ATA_CTRL_DMA_WRITE 0x02000000 | |
| 625 | #define FSL_ATA_CTRL_IORDY_EN 0x01000000 | |
| 626 | ||
| 8993e54b | 627 | #endif /* __CONFIG_H */ |