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8993e54b | 1 | /* |
3b74e7ec | 2 | * (C) Copyright 2007-2009 DENX Software Engineering |
8993e54b | 3 | * |
3765b3e7 | 4 | * SPDX-License-Identifier: GPL-2.0+ |
8993e54b RJ |
5 | */ |
6 | ||
7 | /* | |
72601d04 | 8 | * MPC5121ADS board configuration file |
8993e54b RJ |
9 | */ |
10 | ||
11 | #ifndef __CONFIG_H | |
12 | #define __CONFIG_H | |
13 | ||
72601d04 | 14 | #define CONFIG_MPC5121ADS 1 |
10e99d8f | 15 | |
8993e54b | 16 | /* |
72601d04 | 17 | * Memory map for the MPC5121ADS board: |
8993e54b RJ |
18 | * |
19 | * 0x0000_0000 - 0x0FFF_FFFF DDR RAM (256 MB) | |
20 | * 0x3000_0000 - 0x3001_FFFF SRAM (128 KB) | |
21 | * 0x8000_0000 - 0x803F_FFFF IMMR (4 MB) | |
22 | * 0x8200_0000 - 0x8200_001F CPLD (32 B) | |
5f91db7f JR |
23 | * 0x8400_0000 - 0x82FF_FFFF PCI I/O space (16 MB) |
24 | * 0xA000_0000 - 0xAFFF_FFFF PCI memory space (256 MB) | |
25 | * 0xB000_0000 - 0xBFFF_FFFF PCI memory mapped I/O space (256 MB) | |
8993e54b RJ |
26 | * 0xFC00_0000 - 0xFFFF_FFFF NOR Boot FLASH (64 MB) |
27 | */ | |
28 | ||
29 | /* | |
30 | * High Level Configuration Options | |
31 | */ | |
32 | #define CONFIG_E300 1 /* E300 Family */ | |
0e1bad47 | 33 | |
2ae18241 WD |
34 | #define CONFIG_SYS_TEXT_BASE 0xFFF00000 |
35 | ||
0e1bad47 | 36 | /* video */ |
7d3053fb TT |
37 | #ifdef CONFIG_FSL_DIU_FB |
38 | #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_IMMR + 0x2100) | |
39 | #define CONFIG_VIDEO | |
e69e520f | 40 | #define CONFIG_CMD_BMP |
0e1bad47 | 41 | #define CONFIG_CFB_CONSOLE |
7d3053fb | 42 | #define CONFIG_VIDEO_SW_CURSOR |
0e1bad47 | 43 | #define CONFIG_VGA_AS_SINGLE_DEVICE |
e69e520f TT |
44 | #define CONFIG_VIDEO_LOGO |
45 | #define CONFIG_VIDEO_BMP_LOGO | |
0e1bad47 | 46 | #endif |
8993e54b | 47 | |
5f91db7f | 48 | /* CONFIG_PCI is defined at config time */ |
8993e54b | 49 | |
72601d04 | 50 | #ifdef CONFIG_MPC5121ADS_REV2 |
6d0f6bcf | 51 | #define CONFIG_SYS_MPC512X_CLKIN 66000000 /* in Hz */ |
f31c49db | 52 | #else |
6d0f6bcf | 53 | #define CONFIG_SYS_MPC512X_CLKIN 33333333 /* in Hz */ |
f31c49db MM |
54 | #define CONFIG_PCI |
55 | #endif | |
8993e54b RJ |
56 | |
57 | #define CONFIG_BOARD_EARLY_INIT_F /* call board_early_init_f() */ | |
0e1bad47 | 58 | #define CONFIG_MISC_INIT_R |
8993e54b | 59 | |
6d0f6bcf | 60 | #define CONFIG_SYS_IMMR 0x80000000 |
8993e54b | 61 | |
6d0f6bcf JCPV |
62 | #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */ |
63 | #define CONFIG_SYS_MEMTEST_END 0x00400000 | |
8993e54b RJ |
64 | |
65 | /* | |
66 | * DDR Setup - manually set all parameters as there's no SPD etc. | |
67 | */ | |
72601d04 | 68 | #ifdef CONFIG_MPC5121ADS_REV2 |
6d0f6bcf | 69 | #define CONFIG_SYS_DDR_SIZE 256 /* MB */ |
f31c49db | 70 | #else |
6d0f6bcf | 71 | #define CONFIG_SYS_DDR_SIZE 512 /* MB */ |
f31c49db | 72 | #endif |
6d0f6bcf JCPV |
73 | #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/ |
74 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE | |
b9947bbb | 75 | #define CONFIG_SYS_MAX_RAM_SIZE 0x20000000 |
8993e54b | 76 | |
5d937e8b AG |
77 | #define CONFIG_SYS_IOCTRL_MUX_DDR 0x00000036 |
78 | ||
8993e54b | 79 | /* DDR Controller Configuration |
b1b54e35 WD |
80 | * |
81 | * SYS_CFG: | |
82 | * [31:31] MDDRC Soft Reset: Diabled | |
83 | * [30:30] DRAM CKE pin: Enabled | |
84 | * [29:29] DRAM CLK: Enabled | |
85 | * [28:28] Command Mode: Enabled (For initialization only) | |
86 | * [27:25] DRAM Row Select: dram_row[15:0] = magenta_address[25:10] | |
87 | * [24:21] DRAM Bank Select: dram_bank[1:0] = magenta_address[11:10] | |
88 | * [20:19] Read Test: DON'T USE | |
89 | * [18:18] Self Refresh: Enabled | |
90 | * [17:17] 16bit Mode: Disabled | |
91 | * [16:13] Ready Delay: 2 | |
92 | * [12:12] Half DQS Delay: Disabled | |
93 | * [11:11] Quarter DQS Delay: Disabled | |
94 | * [10:08] Write Delay: 2 | |
95 | * [07:07] Early ODT: Disabled | |
96 | * [06:06] On DIE Termination: Disabled | |
97 | * [05:05] FIFO Overflow Clear: DON'T USE here | |
98 | * [04:04] FIFO Underflow Clear: DON'T USE here | |
99 | * [03:03] FIFO Overflow Pending: DON'T USE here | |
100 | * [02:02] FIFO Underlfow Pending: DON'T USE here | |
101 | * [01:01] FIFO Overlfow Enabled: Enabled | |
102 | * [00:00] FIFO Underflow Enabled: Enabled | |
103 | * TIME_CFG0 | |
104 | * [31:16] DRAM Refresh Time: 0 CSB clocks | |
105 | * [15:8] DRAM Command Time: 0 CSB clocks | |
106 | * [07:00] DRAM Precharge Time: 0 CSB clocks | |
107 | * TIME_CFG1 | |
108 | * [31:26] DRAM tRFC: | |
109 | * [25:21] DRAM tWR1: | |
110 | * [20:17] DRAM tWRT1: | |
111 | * [16:11] DRAM tDRR: | |
112 | * [10:05] DRAM tRC: | |
113 | * [04:00] DRAM tRAS: | |
114 | * TIME_CFG2 | |
115 | * [31:28] DRAM tRCD: | |
116 | * [27:23] DRAM tFAW: | |
117 | * [22:19] DRAM tRTW1: | |
118 | * [18:15] DRAM tCCD: | |
119 | * [14:10] DRAM tRTP: | |
120 | * [09:05] DRAM tRP: | |
121 | * [04:00] DRAM tRPA | |
122 | */ | |
72601d04 | 123 | #ifdef CONFIG_MPC5121ADS_REV2 |
054197ba | 124 | #define CONFIG_SYS_MDDRC_SYS_CFG 0xE8604A00 |
6d0f6bcf JCPV |
125 | #define CONFIG_SYS_MDDRC_TIME_CFG1 0x54EC1168 |
126 | #define CONFIG_SYS_MDDRC_TIME_CFG2 0x35210864 | |
f31c49db | 127 | #else |
054197ba MS |
128 | #define CONFIG_SYS_MDDRC_SYS_CFG 0xEA804A00 |
129 | #define CONFIG_SYS_MDDRC_TIME_CFG1 0x68EC1168 | |
130 | #define CONFIG_SYS_MDDRC_TIME_CFG2 0x34310864 | |
f31c49db | 131 | #endif |
054197ba | 132 | #define CONFIG_SYS_MDDRC_TIME_CFG0 0x06183D2E |
6d0f6bcf | 133 | |
a5aa3998 MS |
134 | #define CONFIG_SYS_MDDRC_SYS_CFG_ELPIDA 0xEA802B00 |
135 | #define CONFIG_SYS_MDDRC_TIME_CFG1_ELPIDA 0x690e1189 | |
136 | #define CONFIG_SYS_MDDRC_TIME_CFG2_ELPIDA 0x35310864 | |
137 | ||
054197ba MS |
138 | #define CONFIG_SYS_DDRCMD_NOP 0x01380000 |
139 | #define CONFIG_SYS_DDRCMD_PCHG_ALL 0x01100400 | |
140 | #define CONFIG_SYS_DDRCMD_EM2 0x01020000 | |
141 | #define CONFIG_SYS_DDRCMD_EM3 0x01030000 | |
142 | #define CONFIG_SYS_DDRCMD_EN_DLL 0x01010000 | |
143 | #define CONFIG_SYS_DDRCMD_RFSH 0x01080000 | |
a5aa3998 MS |
144 | |
145 | #define DDRCMD_EMR_OCD(pr, ohm) ( \ | |
146 | (1 << 24) | /* MDDRC Command Request */ \ | |
147 | (1 << 16) | /* MODE Reg BA[2:0] */ \ | |
148 | (0 << 12) | /* Outputs 0=Enabled */ \ | |
149 | (0 << 11) | /* RDQS */ \ | |
150 | (1 << 10) | /* DQS# */ \ | |
151 | (pr << 7) | /* OCD prog 7=deflt,0=exit */ \ | |
152 | /* ODT Rtt[1:0] 0=0,1=75,2=150,3=50 */ \ | |
153 | ((ohm & 0x2) << 5)| /* Rtt1 */ \ | |
154 | (0 << 3) | /* additive posted CAS# */ \ | |
155 | ((ohm & 0x1) << 2)| /* Rtt0 */ \ | |
156 | (0 << 0) | /* Output Drive Strength */ \ | |
157 | (0 << 0)) /* DLL Enable 0=Normal */ | |
158 | ||
159 | #define CONFIG_SYS_DDRCMD_OCD_DEFAULT DDRCMD_EMR_OCD(7, 0) | |
160 | #define CONFIG_SYS_ELPIDA_OCD_EXIT DDRCMD_EMR_OCD(0, 0) | |
161 | ||
162 | #define DDRCMD_MODE_REG(cas, wr) ( \ | |
163 | (1 << 24) | /* MDDRC Command Request */ \ | |
164 | (0 << 16) | /* MODE Reg BA[2:0] */ \ | |
165 | ((wr-1) << 9)| /* Write Recovery */ \ | |
166 | (cas << 4) | /* CAS */ \ | |
167 | (0 << 3) | /* Burst Type:0=Sequential,1=Interleaved */ \ | |
168 | (2 << 0)) /* 4 or 8 Burst Length:0x2=4 0x3=8 */ | |
169 | ||
170 | #define CONFIG_SYS_MICRON_INIT_DEV_OP DDRCMD_MODE_REG(3, 3) | |
171 | #define CONFIG_SYS_ELPIDA_INIT_DEV_OP DDRCMD_MODE_REG(4, 4) | |
172 | #define CONFIG_SYS_ELPIDA_RES_DLL (DDRCMD_MODE_REG(4, 4) | (1 << 8)) | |
8993e54b RJ |
173 | |
174 | /* DDR Priority Manager Configuration */ | |
6d0f6bcf JCPV |
175 | #define CONFIG_SYS_MDDRCGRP_PM_CFG1 0x00077777 |
176 | #define CONFIG_SYS_MDDRCGRP_PM_CFG2 0x00000000 | |
177 | #define CONFIG_SYS_MDDRCGRP_HIPRIO_CFG 0x00000001 | |
178 | #define CONFIG_SYS_MDDRCGRP_LUT0_MU 0xFFEEDDCC | |
179 | #define CONFIG_SYS_MDDRCGRP_LUT0_ML 0xBBAAAAAA | |
180 | #define CONFIG_SYS_MDDRCGRP_LUT1_MU 0x66666666 | |
181 | #define CONFIG_SYS_MDDRCGRP_LUT1_ML 0x55555555 | |
182 | #define CONFIG_SYS_MDDRCGRP_LUT2_MU 0x44444444 | |
183 | #define CONFIG_SYS_MDDRCGRP_LUT2_ML 0x44444444 | |
184 | #define CONFIG_SYS_MDDRCGRP_LUT3_MU 0x55555555 | |
185 | #define CONFIG_SYS_MDDRCGRP_LUT3_ML 0x55555558 | |
186 | #define CONFIG_SYS_MDDRCGRP_LUT4_MU 0x11111111 | |
187 | #define CONFIG_SYS_MDDRCGRP_LUT4_ML 0x11111122 | |
188 | #define CONFIG_SYS_MDDRCGRP_LUT0_AU 0xaaaaaaaa | |
189 | #define CONFIG_SYS_MDDRCGRP_LUT0_AL 0xaaaaaaaa | |
190 | #define CONFIG_SYS_MDDRCGRP_LUT1_AU 0x66666666 | |
191 | #define CONFIG_SYS_MDDRCGRP_LUT1_AL 0x66666666 | |
192 | #define CONFIG_SYS_MDDRCGRP_LUT2_AU 0x11111111 | |
193 | #define CONFIG_SYS_MDDRCGRP_LUT2_AL 0x11111111 | |
194 | #define CONFIG_SYS_MDDRCGRP_LUT3_AU 0x11111111 | |
195 | #define CONFIG_SYS_MDDRCGRP_LUT3_AL 0x11111111 | |
196 | #define CONFIG_SYS_MDDRCGRP_LUT4_AU 0x11111111 | |
197 | #define CONFIG_SYS_MDDRCGRP_LUT4_AL 0x11111111 | |
8993e54b RJ |
198 | |
199 | /* | |
200 | * NOR FLASH on the Local Bus | |
201 | */ | |
f31c49db | 202 | #undef CONFIG_BKUP_FLASH |
6d0f6bcf | 203 | #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ |
00b1883a | 204 | #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ |
f31c49db | 205 | #ifdef CONFIG_BKUP_FLASH |
6d0f6bcf JCPV |
206 | #define CONFIG_SYS_FLASH_BASE 0xFF800000 /* start of FLASH */ |
207 | #define CONFIG_SYS_FLASH_SIZE 0x00800000 /* max flash size in bytes */ | |
f31c49db | 208 | #else |
6d0f6bcf JCPV |
209 | #define CONFIG_SYS_FLASH_BASE 0xFC000000 /* start of FLASH */ |
210 | #define CONFIG_SYS_FLASH_SIZE 0x04000000 /* max flash size in bytes */ | |
f31c49db | 211 | #endif |
6d0f6bcf JCPV |
212 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE |
213 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ | |
214 | #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE} | |
215 | #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */ | |
8993e54b | 216 | |
6d0f6bcf | 217 | #undef CONFIG_SYS_FLASH_CHECKSUM |
8993e54b | 218 | |
229549a5 SR |
219 | /* |
220 | * NAND FLASH | |
13946925 | 221 | * drivers/mtd/nand/mpc5121_nfc.c (rev 2 silicon only) |
229549a5 | 222 | */ |
7d4450a9 WD |
223 | #define CONFIG_CMD_NAND /* enable NAND support */ |
224 | #define CONFIG_JFFS2_NAND /* with JFFS2 on it */ | |
229549a5 SR |
225 | #define CONFIG_NAND_MPC5121_NFC |
226 | #define CONFIG_SYS_NAND_BASE 0x40000000 | |
227 | ||
228 | #define CONFIG_SYS_MAX_NAND_DEVICE 2 | |
229549a5 SR |
229 | #define CONFIG_SYS_NAND_SELECT_DEVICE /* driver supports mutipl. chips */ |
230 | ||
231 | /* | |
232 | * Configuration parameters for MPC5121 NAND driver | |
233 | */ | |
234 | #define CONFIG_FSL_NFC_WIDTH 1 | |
235 | #define CONFIG_FSL_NFC_WRITE_SIZE 2048 | |
236 | #define CONFIG_FSL_NFC_SPARE_SIZE 64 | |
237 | #define CONFIG_FSL_NFC_CHIPS CONFIG_SYS_MAX_NAND_DEVICE | |
238 | ||
8993e54b RJ |
239 | /* |
240 | * CPLD registers area is really only 32 bytes in size, but the smallest possible LP | |
241 | * window is 64KB | |
242 | */ | |
6d0f6bcf JCPV |
243 | #define CONFIG_SYS_CPLD_BASE 0x82000000 |
244 | #define CONFIG_SYS_CPLD_SIZE 0x00010000 /* 64 KB */ | |
676c6691 AG |
245 | #define CONFIG_SYS_CS2_START CONFIG_SYS_CPLD_BASE |
246 | #define CONFIG_SYS_CS2_SIZE CONFIG_SYS_CPLD_SIZE | |
8993e54b | 247 | |
6d0f6bcf JCPV |
248 | #define CONFIG_SYS_SRAM_BASE 0x30000000 |
249 | #define CONFIG_SYS_SRAM_SIZE 0x00020000 /* 128 KB */ | |
8993e54b | 250 | |
6d0f6bcf JCPV |
251 | #define CONFIG_SYS_CS0_CFG 0x05059310 /* ALE active low, data size 4bytes */ |
252 | #define CONFIG_SYS_CS2_CFG 0x05059010 /* ALE active low, data size 1byte */ | |
253 | #define CONFIG_SYS_CS_ALETIMING 0x00000005 /* Use alternative CS timing for CS0 and CS2 */ | |
8993e54b RJ |
254 | |
255 | /* Use SRAM for initial stack */ | |
6d0f6bcf | 256 | #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_SRAM_BASE /* Initial RAM address */ |
553f0982 | 257 | #define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_SRAM_SIZE /* Size of used area in RAM */ |
8993e54b | 258 | |
25ddd1fb | 259 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
6d0f6bcf | 260 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
8993e54b | 261 | |
14d0a02a | 262 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* Start of monitor */ |
229549a5 | 263 | #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ |
0e1bad47 | 264 | #ifdef CONFIG_FSL_DIU_FB |
6d0f6bcf | 265 | #define CONFIG_SYS_MALLOC_LEN (6 * 1024 * 1024) /* Reserved for malloc */ |
0e1bad47 | 266 | #else |
6d0f6bcf | 267 | #define CONFIG_SYS_MALLOC_LEN (512 * 1024) |
0e1bad47 | 268 | #endif |
8993e54b RJ |
269 | |
270 | /* | |
271 | * Serial Port | |
272 | */ | |
273 | #define CONFIG_CONS_INDEX 1 | |
8993e54b RJ |
274 | |
275 | /* | |
276 | * Serial console configuration | |
277 | */ | |
278 | #define CONFIG_PSC_CONSOLE 3 /* console is on PSC3 */ | |
bfb31279 | 279 | #define CONFIG_SYS_PSC3 |
8993e54b RJ |
280 | #if CONFIG_PSC_CONSOLE != 3 |
281 | #error CONFIG_PSC_CONSOLE must be 3 | |
282 | #endif | |
283 | #define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */ | |
6d0f6bcf | 284 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
8993e54b RJ |
285 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} |
286 | ||
287 | #define CONSOLE_FIFO_TX_SIZE FIFOC_PSC3_TX_SIZE | |
288 | #define CONSOLE_FIFO_TX_ADDR FIFOC_PSC3_TX_ADDR | |
289 | #define CONSOLE_FIFO_RX_SIZE FIFOC_PSC3_RX_SIZE | |
290 | #define CONSOLE_FIFO_RX_ADDR FIFOC_PSC3_RX_ADDR | |
291 | ||
292 | #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ | |
8993e54b | 293 | |
e5f53864 AG |
294 | /* |
295 | * Clocks in use | |
296 | */ | |
297 | #define SCCR1_CLOCKS_EN (CLOCK_SCCR1_CFG_EN | \ | |
298 | CLOCK_SCCR1_DDR_EN | \ | |
299 | CLOCK_SCCR1_FEC_EN | \ | |
300 | CLOCK_SCCR1_LPC_EN | \ | |
301 | CLOCK_SCCR1_NFC_EN | \ | |
302 | CLOCK_SCCR1_PATA_EN | \ | |
303 | CLOCK_SCCR1_PCI_EN | \ | |
304 | CLOCK_SCCR1_PSC_EN(CONFIG_PSC_CONSOLE) | \ | |
305 | CLOCK_SCCR1_PSCFIFO_EN | \ | |
306 | CLOCK_SCCR1_TPR_EN) | |
307 | ||
308 | #define SCCR2_CLOCKS_EN (CLOCK_SCCR2_DIU_EN | \ | |
309 | CLOCK_SCCR2_I2C_EN | \ | |
310 | CLOCK_SCCR2_MEM_EN | \ | |
311 | CLOCK_SCCR2_SPDIF_EN | \ | |
312 | CLOCK_SCCR2_USB1_EN | \ | |
313 | CLOCK_SCCR2_USB2_EN) | |
314 | ||
5f91db7f JR |
315 | /* |
316 | * PCI | |
317 | */ | |
318 | #ifdef CONFIG_PCI | |
842033e6 | 319 | #define CONFIG_PCI_INDIRECT_BRIDGE |
5f91db7f JR |
320 | |
321 | /* | |
322 | * General PCI | |
323 | */ | |
6d0f6bcf JCPV |
324 | #define CONFIG_SYS_PCI_MEM_BASE 0xA0000000 |
325 | #define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BASE | |
326 | #define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 /* 256M */ | |
327 | #define CONFIG_SYS_PCI_MMIO_BASE (CONFIG_SYS_PCI_MEM_BASE + CONFIG_SYS_PCI_MEM_SIZE) | |
328 | #define CONFIG_SYS_PCI_MMIO_PHYS CONFIG_SYS_PCI_MMIO_BASE | |
329 | #define CONFIG_SYS_PCI_MMIO_SIZE 0x10000000 /* 256M */ | |
330 | #define CONFIG_SYS_PCI_IO_BASE 0x00000000 | |
331 | #define CONFIG_SYS_PCI_IO_PHYS 0x84000000 | |
332 | #define CONFIG_SYS_PCI_IO_SIZE 0x01000000 /* 16M */ | |
5f91db7f | 333 | |
5f91db7f JR |
334 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ |
335 | ||
336 | #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ | |
337 | ||
338 | #endif | |
339 | ||
8993e54b RJ |
340 | /* I2C */ |
341 | #define CONFIG_HARD_I2C /* I2C with hardware support */ | |
8993e54b | 342 | #define CONFIG_I2C_MULTI_BUS |
6d0f6bcf JCPV |
343 | #define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed and slave address */ |
344 | #define CONFIG_SYS_I2C_SLAVE 0x7F | |
8993e54b | 345 | #if 0 |
6d0f6bcf | 346 | #define CONFIG_SYS_I2C_NOPROBES {{0,0x69}} /* Don't probe these addrs */ |
8993e54b RJ |
347 | #endif |
348 | ||
abfbd0ae MM |
349 | /* |
350 | * IIM - IC Identification Module | |
351 | */ | |
83306927 | 352 | #undef CONFIG_FSL_IIM |
abfbd0ae | 353 | |
80020120 GB |
354 | /* |
355 | * EEPROM configuration | |
356 | */ | |
6d0f6bcf JCPV |
357 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* 16-bit EEPROM address */ |
358 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Atmel: AT24C32A-10TQ-2.7 */ | |
359 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* 10ms of delay */ | |
360 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* 32-Byte Page Write Mode */ | |
80020120 | 361 | |
8993e54b RJ |
362 | /* |
363 | * Ethernet configuration | |
364 | */ | |
365 | #define CONFIG_MPC512x_FEC 1 | |
8993e54b RJ |
366 | #define CONFIG_PHY_ADDR 0x1 |
367 | #define CONFIG_MII 1 /* MII PHY management */ | |
f31c49db | 368 | #define CONFIG_FEC_AN_TIMEOUT 1 |
ef11df6b | 369 | #define CONFIG_HAS_ETH0 |
8993e54b | 370 | |
8993e54b RJ |
371 | /* |
372 | * Configure on-board RTC | |
373 | */ | |
f31c49db | 374 | #define CONFIG_RTC_M41T62 /* use M41T62 rtc via i2 */ |
6d0f6bcf | 375 | #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */ |
8993e54b | 376 | |
29c6fbe0 DD |
377 | /* |
378 | * USB Support | |
379 | */ | |
29c6fbe0 DD |
380 | |
381 | #if defined(CONFIG_CMD_USB) | |
382 | #define CONFIG_USB_EHCI /* Enable EHCI Support */ | |
383 | #define CONFIG_USB_EHCI_FSL /* On a FSL platform */ | |
384 | #define CONFIG_EHCI_MMIO_BIG_ENDIAN /* With big-endian regs */ | |
385 | #define CONFIG_EHCI_DESC_BIG_ENDIAN | |
386 | #define CONFIG_EHCI_IS_TDI | |
29c6fbe0 DD |
387 | #endif |
388 | ||
8993e54b RJ |
389 | /* |
390 | * Environment | |
391 | */ | |
5a1aceb0 | 392 | #define CONFIG_ENV_IS_IN_FLASH 1 |
8993e54b | 393 | /* This has to be a multiple of the Flash sector size */ |
6d0f6bcf | 394 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) |
0e8d1586 | 395 | #define CONFIG_ENV_SIZE 0x2000 |
f31c49db | 396 | #ifdef CONFIG_BKUP_FLASH |
0e8d1586 | 397 | #define CONFIG_ENV_SECT_SIZE 0x20000 /* one sector (256K) for env */ |
f31c49db | 398 | #else |
0e8d1586 | 399 | #define CONFIG_ENV_SECT_SIZE 0x40000 /* one sector (256K) for env */ |
f31c49db | 400 | #endif |
8993e54b RJ |
401 | |
402 | /* Address and size of Redundant Environment Sector */ | |
0e8d1586 JCPV |
403 | #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) |
404 | #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) | |
8993e54b RJ |
405 | |
406 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
6d0f6bcf | 407 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
8993e54b | 408 | |
7d4450a9 | 409 | #define CONFIG_CMD_DATE |
7d4450a9 | 410 | #define CONFIG_CMD_EEPROM |
7d4450a9 WD |
411 | #define CONFIG_CMD_IDE |
412 | #define CONFIG_CMD_JFFS2 | |
e27f3a6e | 413 | #define CONFIG_CMD_REGINFO |
7d4450a9 | 414 | |
abfbd0ae | 415 | #undef CONFIG_CMD_FUSE |
e27f3a6e | 416 | |
8993e54b | 417 | #if defined(CONFIG_PCI) |
e27f3a6e | 418 | #define CONFIG_CMD_PCI |
8993e54b RJ |
419 | #endif |
420 | ||
7d4450a9 WD |
421 | /* |
422 | * Dynamic MTD partition support | |
423 | */ | |
424 | #define CONFIG_CMD_MTDPARTS | |
425 | #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ | |
426 | #define CONFIG_FLASH_CFI_MTD | |
427 | #define MTDIDS_DEFAULT "nor0=fc000000.flash,nand0=mpc5121.nand" | |
428 | ||
429 | /* | |
430 | * NOR flash layout: | |
431 | * | |
432 | * FC000000 - FEABFFFF 42.75 MiB User Data | |
433 | * FEAC0000 - FFABFFFF 16 MiB Root File System | |
434 | * FFAC0000 - FFEBFFFF 4 MiB Linux Kernel | |
435 | * FFEC0000 - FFEFFFFF 256 KiB Device Tree | |
436 | * FFF00000 - FFFFFFFF 1 MiB U-Boot (up to 512 KiB) and 2 x * env | |
437 | * | |
438 | * NAND flash layout: one big partition | |
439 | */ | |
440 | #define MTDPARTS_DEFAULT "mtdparts=fc000000.flash:43776k(user)," \ | |
441 | "16m(rootfs)," \ | |
442 | "4m(kernel)," \ | |
443 | "256k(dtb)," \ | |
444 | "1m(u-boot);" \ | |
445 | "mpc5121.nand:-(data)" | |
446 | ||
29c6fbe0 DD |
447 | #if defined(CONFIG_CMD_IDE) || defined(CONFIG_CMD_EXT2) || defined(CONFIG_CMD_USB) |
448 | ||
70a4da45 RK |
449 | #define CONFIG_DOS_PARTITION |
450 | #define CONFIG_MAC_PARTITION | |
451 | #define CONFIG_ISO_PARTITION | |
29c6fbe0 | 452 | |
29c6fbe0 DD |
453 | #define CONFIG_SUPPORT_VFAT |
454 | ||
70a4da45 RK |
455 | #endif /* defined(CONFIG_CMD_IDE) */ |
456 | ||
8993e54b | 457 | /* |
6d0f6bcf JCPV |
458 | * Watchdog timeout = CONFIG_SYS_WATCHDOG_VALUE * 65536 / IPS clock. |
459 | * For example, when IPS is set to 66MHz and CONFIG_SYS_WATCHDOG_VALUE is set | |
8993e54b RJ |
460 | * to 0xFFFF, watchdog timeouts after about 64s. For details refer |
461 | * to chapter 36 of the MPC5121e Reference Manual. | |
462 | */ | |
66ffb188 | 463 | /* #define CONFIG_WATCHDOG */ /* enable watchdog */ |
6d0f6bcf | 464 | #define CONFIG_SYS_WATCHDOG_VALUE 0xFFFF |
8993e54b RJ |
465 | |
466 | /* | |
467 | * Miscellaneous configurable options | |
468 | */ | |
6d0f6bcf JCPV |
469 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
470 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ | |
8993e54b | 471 | |
e27f3a6e | 472 | #ifdef CONFIG_CMD_KGDB |
6d0f6bcf | 473 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
8993e54b | 474 | #else |
6d0f6bcf | 475 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
8993e54b RJ |
476 | #endif |
477 | ||
6d0f6bcf JCPV |
478 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buffer Size */ |
479 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
480 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
8993e54b RJ |
481 | |
482 | /* | |
483 | * For booting Linux, the board info and command line data | |
9f530d59 | 484 | * have to be in the first 256 MB of memory, since this is |
8993e54b RJ |
485 | * the maximum mapped by the Linux kernel during initialization. |
486 | */ | |
9f530d59 | 487 | #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux*/ |
8993e54b RJ |
488 | |
489 | /* Cache Configuration */ | |
6d0f6bcf JCPV |
490 | #define CONFIG_SYS_DCACHE_SIZE 32768 |
491 | #define CONFIG_SYS_CACHELINE_SIZE 32 | |
e27f3a6e | 492 | #ifdef CONFIG_CMD_KGDB |
6d0f6bcf | 493 | #define CONFIG_SYS_CACHELINE_SHIFT 5 /*log base 2 of the above value*/ |
8993e54b RJ |
494 | #endif |
495 | ||
6d0f6bcf | 496 | #define CONFIG_SYS_HID0_INIT 0x000000000 |
e2b66fe4 | 497 | #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | HID0_ICE) |
6d0f6bcf | 498 | #define CONFIG_SYS_HID2 HID2_HBE |
8993e54b | 499 | |
31d82672 BB |
500 | #define CONFIG_HIGH_BATS 1 /* High BATs supported */ |
501 | ||
e27f3a6e | 502 | #ifdef CONFIG_CMD_KGDB |
8993e54b | 503 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ |
8993e54b RJ |
504 | #endif |
505 | ||
506 | /* | |
507 | * Environment Configuration | |
508 | */ | |
66ffb188 | 509 | #define CONFIG_TIMESTAMP |
8993e54b | 510 | |
72601d04 | 511 | #define CONFIG_HOSTNAME mpc5121ads |
b3f44c21 | 512 | #define CONFIG_BOOTFILE "mpc5121ads/uImage" |
8b3637c6 | 513 | #define CONFIG_ROOTPATH "/opt/eldk/ppc_6xx" |
8993e54b | 514 | |
8d103071 | 515 | #define CONFIG_LOADADDR 400000 /* default location for tftp and bootm */ |
8993e54b | 516 | |
8993e54b RJ |
517 | #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ |
518 | ||
519 | #define CONFIG_BAUDRATE 115200 | |
520 | ||
521 | #define CONFIG_PREBOOT "echo;" \ | |
5b0b2b6f | 522 | "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ |
8993e54b RJ |
523 | "echo" |
524 | ||
525 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
8d103071 | 526 | "u-boot_addr_r=200000\0" \ |
51e46e28 WD |
527 | "kernel_addr_r=600000\0" \ |
528 | "fdt_addr_r=880000\0" \ | |
529 | "ramdisk_addr_r=900000\0" \ | |
8d103071 | 530 | "u-boot_addr=FFF00000\0" \ |
7d4450a9 | 531 | "kernel_addr=FFAC0000\0" \ |
51e46e28 | 532 | "fdt_addr=FFEC0000\0" \ |
7d4450a9 | 533 | "ramdisk_addr=FEAC0000\0" \ |
72601d04 WD |
534 | "ramdiskfile=mpc5121ads/uRamdisk\0" \ |
535 | "u-boot=mpc5121ads/u-boot.bin\0" \ | |
536 | "bootfile=mpc5121ads/uImage\0" \ | |
537 | "fdtfile=mpc5121ads/mpc5121ads.dtb\0" \ | |
51e46e28 | 538 | "rootpath=/opt/eldk/ppc_6xx\n" \ |
8993e54b | 539 | "netdev=eth0\0" \ |
8d103071 | 540 | "consdev=ttyPSC0\0" \ |
8993e54b RJ |
541 | "nfsargs=setenv bootargs root=/dev/nfs rw " \ |
542 | "nfsroot=${serverip}:${rootpath}\0" \ | |
543 | "ramargs=setenv bootargs root=/dev/ram rw\0" \ | |
544 | "addip=setenv bootargs ${bootargs} " \ | |
545 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ | |
546 | ":${hostname}:${netdev}:off panic=1\0" \ | |
8d103071 WD |
547 | "addtty=setenv bootargs ${bootargs} " \ |
548 | "console=${consdev},${baudrate}\0" \ | |
8993e54b | 549 | "flash_nfs=run nfsargs addip addtty;" \ |
a99715b8 | 550 | "bootm ${kernel_addr} - ${fdt_addr}\0" \ |
8993e54b | 551 | "flash_self=run ramargs addip addtty;" \ |
8d103071 WD |
552 | "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \ |
553 | "net_nfs=tftp ${kernel_addr_r} ${bootfile};" \ | |
554 | "tftp ${fdt_addr_r} ${fdtfile};" \ | |
555 | "run nfsargs addip addtty;" \ | |
556 | "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \ | |
557 | "net_self=tftp ${kernel_addr_r} ${bootfile};" \ | |
558 | "tftp ${ramdisk_addr_r} ${ramdiskfile};" \ | |
a99715b8 | 559 | "tftp ${fdt_addr_r} ${fdtfile};" \ |
8d103071 | 560 | "run ramargs addip addtty;" \ |
5b0b2b6f | 561 | "bootm ${kernel_addr_r} ${ramdisk_addr_r} ${fdt_addr_r}\0"\ |
a99715b8 | 562 | "load=tftp ${u-boot_addr_r} ${u-boot}\0" \ |
8d103071 WD |
563 | "update=protect off ${u-boot_addr} +${filesize};" \ |
564 | "era ${u-boot_addr} +${filesize};" \ | |
565 | "cp.b ${u-boot_addr_r} ${u-boot_addr} ${filesize}\0" \ | |
566 | "upd=run load update\0" \ | |
8993e54b RJ |
567 | "" |
568 | ||
8993e54b RJ |
569 | #define CONFIG_BOOTCOMMAND "run flash_self" |
570 | ||
ef11df6b | 571 | #define CONFIG_OF_SUPPORT_OLD_DEVICE_TREES 1 |
281ff9a4 GB |
572 | |
573 | #define OF_CPU "PowerPC,5121@0" | |
ef11df6b | 574 | #define OF_SOC_COMPAT "fsl,mpc5121-immr" |
281ff9a4 | 575 | #define OF_TBCLK (bd->bi_busfreq / 4) |
ac915283 | 576 | #define OF_STDOUT_PATH "/soc@80000000/serial@11300" |
281ff9a4 | 577 | |
70a4da45 RK |
578 | /*----------------------------------------------------------------------- |
579 | * IDE/ATA stuff | |
580 | *----------------------------------------------------------------------- | |
581 | */ | |
582 | ||
583 | #undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */ | |
584 | #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ | |
585 | #undef CONFIG_IDE_LED /* LED for IDE not supported */ | |
586 | ||
587 | #define CONFIG_IDE_RESET /* reset for IDE supported */ | |
588 | #define CONFIG_IDE_PREINIT | |
589 | ||
590 | #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ | |
591 | #define CONFIG_SYS_IDE_MAXDEVICE 2 /* max. 1 drive per IDE bus */ | |
592 | ||
593 | #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 | |
3b74e7ec | 594 | #define CONFIG_SYS_ATA_BASE_ADDR get_pata_base() |
70a4da45 RK |
595 | |
596 | /* Offset for data I/O RefMan MPC5121EE Table 28-10 */ | |
597 | #define CONFIG_SYS_ATA_DATA_OFFSET (0x00A0) | |
598 | ||
599 | /* Offset for normal register accesses */ | |
600 | #define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET) | |
601 | ||
602 | /* Offset for alternate registers RefMan MPC5121EE Table 28-23 */ | |
603 | #define CONFIG_SYS_ATA_ALT_OFFSET (0x00D8) | |
604 | ||
605 | /* Interval between registers */ | |
606 | #define CONFIG_SYS_ATA_STRIDE 4 | |
607 | ||
3b74e7ec | 608 | #define ATA_BASE_ADDR get_pata_base() |
70a4da45 RK |
609 | |
610 | /* | |
611 | * Control register bit definitions | |
612 | */ | |
613 | #define FSL_ATA_CTRL_FIFO_RST_B 0x80000000 | |
614 | #define FSL_ATA_CTRL_ATA_RST_B 0x40000000 | |
615 | #define FSL_ATA_CTRL_FIFO_TX_EN 0x20000000 | |
616 | #define FSL_ATA_CTRL_FIFO_RCV_EN 0x10000000 | |
617 | #define FSL_ATA_CTRL_DMA_PENDING 0x08000000 | |
618 | #define FSL_ATA_CTRL_DMA_ULTRA 0x04000000 | |
619 | #define FSL_ATA_CTRL_DMA_WRITE 0x02000000 | |
620 | #define FSL_ATA_CTRL_IORDY_EN 0x01000000 | |
621 | ||
8993e54b | 622 | #endif /* __CONFIG_H */ |